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From: Manasi Navare <manasi.d.navare@intel.com>
To: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"Singh, Gaurav K" <gaurav.k.singh@intel.com>
Subject: Re: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe
Date: Thu, 23 Aug 2018 13:08:14 -0700	[thread overview]
Message-ID: <20180823200813.GB3015@intel.com> (raw)
In-Reply-To: <83F5C7385F545743AD4FB2A62F75B07347F42421@ORSMSX108.amr.corp.intel.com>

On Fri, Aug 17, 2018 at 12:31:51PM -0700, Srivatsa, Anusha wrote:
> This patch needs to now incorporate the newly added slice_row_per_frame parameter in PPS_16.

Nope, the slice_row_per_frame and slice_per_line are only required to configure PPS
on the source side. They are not DSC spec related PPS parameters.

Manasi

> 
> Anusha 
> 
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Tuesday, July 31, 2018 2:07 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Singh, Gaurav K
> ><gaurav.k.singh@intel.com>; dri-devel@lists.freedesktop.org; Jani Nikula
> ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
> >Srivatsa, Anusha <anusha.srivatsa@intel.com>; Harry Wentland
> ><harry.wentland@amd.com>
> >Subject: [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS
> >infoframe
> >
> >This patch defines a new header file for all the DSC 1.2 structures and creates a
> >structure for PPS infoframe which will be used to send picture parameter set
> >secondary data packet for display stream compression.
> >All the PPS infoframe syntax elements are taken from DSC 1.2 specification from
> >VESA.
> >
> >Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> >Cc: dri-devel@lists.freedesktop.org
> >Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >Cc: Harry Wentland <harry.wentland@amd.com>
> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> >---
> > include/drm/drm_dsc.h | 365
> >++++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 365 insertions(+)
> > create mode 100644 include/drm/drm_dsc.h
> >
> >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h new file mode
> >100644 index 0000000..678e8e6
> >--- /dev/null
> >+++ b/include/drm/drm_dsc.h
> >@@ -0,0 +1,365 @@
> >+/*
> >+ * Copyright (C) 2018 Intel Corp.
> >+ *
> >+ * Permission is hereby granted, free of charge, to any person
> >+obtaining a
> >+ * copy of this software and associated documentation files (the
> >+"Software"),
> >+ * to deal in the Software without restriction, including without
> >+limitation
> >+ * the rights to use, copy, modify, merge, publish, distribute,
> >+sublicense,
> >+ * and/or sell copies of the Software, and to permit persons to whom
> >+the
> >+ * Software is furnished to do so, subject to the following conditions:
> >+ *
> >+ * The above copyright notice and this permission notice shall be
> >+included in
> >+ * all copies or substantial portions of the Software.
> >+ *
> >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >+EXPRESS OR
> >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >+MERCHANTABILITY,
> >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> >EVENT
> >+SHALL
> >+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> >+DAMAGES OR
> >+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> >+OTHERWISE,
> >+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> >USE
> >+OR
> >+ * OTHER DEALINGS IN THE SOFTWARE.
> >+ *
> >+ * Authors:
> >+ * Manasi Navare <manasi.d.navare@intel.com>  */
> >+
> >+#ifndef DRM_DSC_H_
> >+#define DRM_DSC_H_
> >+
> >+#include <drm/drm_dp_helper.h>
> >+
> >+/* VESA Display Stream Compression DSC 1.2 constants */
> >+#define DSC_NUM_BUF_RANGES	15
> >+
> >+/**
> >+ * struct picture_parameter_set - Represents 128 bytes of Picture
> >+Parameter Set
> >+ *
> >+ * The VESA DSC standard defines picture parameter set (PPS) which
> >+display
> >+ * stream compression encoders must communicate to decoders.
> >+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The
> >+fields in
> >+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
> >+ * The PPS fields that span over more than a byte should be stored in
> >+Big Endian
> >+ * format.
> >+ */
> >+struct picture_parameter_set {
> >+	/**
> >+	 * @dsc_version:
> >+	 * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
> >+	 * PPS0[7:4] - dsc_version_major: Contains major version of DSC
> >+	 */
> >+	u8 dsc_version;
> >+	/**
> >+	 * @pps_identifier:
> >+	 * PPS1[7:0] - Application specific identifier that can be
> >+	 * used to differentiate between different PPS tables.
> >+	 */
> >+	u8 pps_identifier;
> >+	/**
> >+	 * @pps_reserved:
> >+	 * PPS2[7:0]- RESERVED Byte
> >+	 */
> >+	u8 pps_reserved;
> >+	/**
> >+	 * @pps_3:
> >+	 * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
> >+	 * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
> >+	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> >+	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> >+	 * PPS3[7:4] - bits_per_component: Bits per component for the original
> >+	 * pixels of the encoded picture.
> >+	 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
> >+	 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
> >+	 * allowed only when dsc_minor_version = 0x2)
> >+	 */
> >+	u8 pps_3;
> >+	/**
> >+	 * @pps_4:
> >+	 * PPS4[1:0] -These are the most significant 2 bits of
> >+	 * compressed BPP bits_per_pixel[9:0] syntax element.
> >+	 * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
> >+	 * PPS4[3] - simple_422: Indicates if decoder drops samples to
> >+	 * reconstruct the 4:2:2 picture.
> >+	 * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
> >+	 * active.
> >+	 * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
> >+	 * groups in picture
> >+	 * PPS4[7:6] - Reseved bits
> >+	 */
> >+	u8 pps_4;
> >+	/**
> >+	 * @bits_per_pixel_low:
> >+	 * PPS5[7:0] - This indicates the lower significant 8 bits of
> >+	 * the compressed BPP bits_per_pixel[9:0] element.
> >+	 */
> >+	u8 bits_per_pixel_low;
> >+	/**
> >+	 * @pic_height:
> >+	 * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
> >+	 * within the raster.
> >+	 */
> >+	__be16 pic_height;
> >+	/**
> >+	 * @pic_width:
> >+	 * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
> >+	 * the raster.
> >+	 */
> >+	__be16 pic_width;
> >+	/**
> >+	 * @slice_height:
> >+	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> >+	 */
> >+	__be16 slice_height;
> >+	/**
> >+	 * @slice_width:
> >+	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> >+	 */
> >+	__be16 slice_width;
> >+	/**
> >+	 * @chunk_size:
> >+	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> >+	 * that are used for slice multiplexing.
> >+	 */
> >+	__be16 chunk_size;
> >+	/**
> >+	 * @initial_xmit_delay_high:
> >+	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> >+	 * It specifies the number of pixel times that the encoder waits before
> >+	 * transmitting data from its rate buffer.
> >+	 * PPS16[7:2] - Reserved
> >+	 */
> >+	u8 initial_xmit_delay_high;
> >+	/**
> >+	 * @initial_xmit_delay_low:
> >+	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> >+	 */
> >+	u8 initial_xmit_delay_low;
> >+	/**
> >+	 * @initial_dec_delay:
> >+	 *
> >+	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> >+	 * of pixel times that the decoder accumulates data in its rate buffer
> >+	 * before starting to decode and output pixels.
> >+	 */
> >+	__be16 initial_dec_delay;
> >+	/**
> >+	 * @pps20_reserved:
> >+	 *
> >+	 * PPS20[7:0] - Reserved
> >+	 */
> >+	u8 pps20_reserved;
> >+	/**
> >+	 * @initial_scale_value:
> >+	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
> >+	 * of a slice.
> >+	 * PPS21[7:6] - Reserved
> >+	 */
> >+	u8 initial_scale_value;
> >+	/**
> >+	 * @scale_increment_interval:
> >+	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> >+	 * the rcXformScale factor at end of a slice.
> >+	 */
> >+	__be16 scale_increment_interval;
> >+	/**
> >+	 * @scale_decrement_interval_high:
> >+	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
> >+	 * decrementing the rcXformScale factor at beginning of a slice.
> >+	 * PPS24[7:4] - Reserved
> >+	 */
> >+	u8 scale_decrement_interval_high;
> >+	/**
> >+	 * @scale_decrement_interval_low:
> >+	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
> >+	 */
> >+	u8 scale_decrement_interval_low;
> >+	/**
> >+	 * @pps26_reserved:
> >+	 * PPS26[7:0]
> >+	 */
> >+	u8 pps26_reserved;
> >+	/**
> >+	 * @first_line_bpg_offset:
> >+	 * PPS27[4:0] - Number of additional bits that are allocated
> >+	 * for each group on first line of a slice.
> >+	 * PPS27[7:5] - Reserved
> >+	 */
> >+	u8 first_line_bpg_offset;
> >+	/**
> >+	 * @nfl_bpg_offset:
> >+	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> >+	 * deallocated for each group for groups after the first line of slice.
> >+	 */
> >+	__be16 nfl_bpg_offset;
> >+	/**
> >+	 * @slice_bpg_offset:
> >+	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
> >+	 * group to enforce the slice constraint.
> >+	 */
> >+	__be16 slice_bpg_offset;
> >+	/**
> >+	 * @initial_offset:
> >+	 * PPS32,33[7:0] - Initial value for rcXformOffset
> >+	 */
> >+	__be16 initial_offset;
> >+	/**
> >+	 * @final_offset:
> >+	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> >+	 */
> >+	__be16 final_offset;
> >+	/**
> >+	 * @flatness_min_qp:
> >+	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
> >+	 * flatness QP adjustment is made.
> >+	 * PPS36[7:5] - Reserved
> >+	 */
> >+	u8 flatness_min_qp;
> >+	/**
> >+	 * @flatness_max_qp:
> >+	 * PPS37[4:0] - Max QP at which flatness is signalled and
> >+	 * the flatness adjustment is made.
> >+	 * PPS37[7:5] - Reserved
> >+	 */
> >+	u8 flatness_max_qp;
> >+	/**
> >+	 * @rc_model_size:
> >+	 * PPS38,39[7:0] - Number of bits within RC Model.
> >+	 */
> >+	__be16 rc_model_size;
> >+	/**
> >+	 * @rc_edge_factor:
> >+	 * PPS40[3:0] - Ratio of current activity vs, previous
> >+	 * activity to determine presence of edge.
> >+	 * PPS40[7:4] - Reserved
> >+	 */
> >+	u8 rc_edge_factor;
> >+	/**
> >+	 * @rc_quant_incr_limit0:
> >+	 * PPS41[4:0] - QP threshold used in short term RC
> >+	 * PPS41[7:5] - Reserved
> >+	 */
> >+	u8 rc_quant_incr_limit0;
> >+	/**
> >+	 * @rc_quant_incr_limit1:
> >+	 * PPS42[4:0] - QP threshold used in short term RC
> >+	 * PPS42[7:5] - Reserved
> >+	 */
> >+	u8 rc_quant_incr_limit1;
> >+	/**
> >+	 * @rc_tgt_offset:
> >+	 * PPS43[3:0] - Lower end of the variability range around the target
> >+	 * bits per group that is allowed by short term RC.
> >+	 * PPS43[7:4]- Upper end of the variability range around the target
> >+	 * bits per group that i allowed by short term rc.
> >+	 */
> >+	u8 rc_tgt_offset;
> >+	/**
> >+	 * @rc_buf_thresh:
> >+	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> >+	 * the 15 ranges defined by 14 thresholds.
> >+	 */
> >+	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> >+	/**
> >+	 * @rc_range_parameters:
> >+	 * PPS58[7:0] - PPS87[7:0]
> >+	 * Parameters that correspond to each of the 15 ranges.
> >+	 */
> >+	__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> >+	/**
> >+	 * @native_422_420:
> >+	 * PPS88[0] - 0 = Native 4:2:2 not used
> >+	 * 1 = Native 4:2:2 used
> >+	 * PPS88[1] - 0 = Native 4:2:0 not use
> >+	 * 1 = Native 4:2:0 used
> >+	 * PPS88[7:2] - Reserved 6 bits
> >+	 */
> >+	u8 native_422_420;
> >+	/**
> >+	 * @second_line_bpg_offset:
> >+	 * PPS89[4:0] - Additional bits/group budget for the
> >+	 * second line of a slice in Native 4:2:0 mode.
> >+	 * Set to 0 if DSC minor version is 1 or native420 is 0.
> >+	 * PPS89[7:5] - Reserved
> >+	 */
> >+	u8 second_line_bpg_offset;
> >+	/**
> >+	 * @nsl_bpg_offset:
> >+	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> >+	 * for each group that is not in the second line of a slice.
> >+	 */
> >+	__be16 nsl_bpg_offset;
> >+	/**
> >+	 * @second_line_offset_adj:
> >+	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> >+	 * line in Native 4:2:0 mode.
> >+	 */
> >+	__be16 second_line_offset_adj;
> >+	/**
> >+	 * @pps_long_94_reserved:
> >+	 * PPS 94, 95, 96, 97 - Reserved
> >+	 */
> >+	u32 pps_long_94_reserved;
> >+	/**
> >+	 * @pps_long_98_reserved:
> >+	 * PPS 98, 99, 100, 101 - Reserved
> >+	 */
> >+	u32 pps_long_98_reserved;
> >+	/**
> >+	 * @pps_long_102_reserved:
> >+	 * PPS 102, 103, 104, 105 - Reserved
> >+	 */
> >+	u32 pps_long_102_reserved;
> >+	/**
> >+	 * @pps_long_106_reserved:
> >+	 * PPS 106, 107, 108, 109 - reserved
> >+	 */
> >+	u32 pps_long_106_reserved;
> >+	/**
> >+	 * @pps_long_110_reserved:
> >+	 * PPS 110, 111, 112, 113 - reserved
> >+	 */
> >+	u32 pps_long_110_reserved;
> >+	/**
> >+	 * @pps_long_114_reserved:
> >+	 * PPS 114 - 117 - reserved
> >+	 */
> >+	u32 pps_long_114_reserved;
> >+	/**
> >+	 * @pps_long_118_reserved:
> >+	 * PPS 118 - 121 - reserved
> >+	 */
> >+	u32 pps_long_118_reserved;
> >+	/**
> >+	 * @pps_long_122_reserved:
> >+	 * PPS 122- 125 - reserved
> >+	 */
> >+	u32 pps_long_122_reserved;
> >+	/**
> >+	 * @pps_short_126_reserved:
> >+	 * PPS 126, 127 - reserved
> >+	 */
> >+	__be16 pps_short_126_reserved;
> >+};
> >+
> >+/**
> >+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture
> >+Parameter
> >+ * Set Metadata
> >+ *
> >+ * This structure represents the DSC PPS infoframe required to send the
> >+Picture
> >+ * Parameter Set metadata required before enabling VESA Display Stream
> >+ * Compression. This is based on the DP Secondary Data Packet structure
> >+and
> >+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
> >+ *
> >+ * @pps_header:
> >+ *
> >+ * Header for PPS as per DP SDP header format
> >+ *
> >+ * @pps_payload:
> >+ *
> >+ * PPS payload fields as per DSC specification Table 4-1  */ struct
> >+drm_dsc_pps_infoframe {
> >+	struct dp_sdp_header pps_header;
> >+	struct picture_parameter_set pps_payload; } __packed;
> >+
> >+#endif /* _DRM_DSC_H_ */
> >--
> >2.7.4
> 
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  reply	other threads:[~2018-08-23 20:08 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31 21:06 [PATCH v2 00/23] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-07-31 21:06 ` [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-07-31 22:17   ` Srivatsa, Anusha
2018-07-31 21:06 ` [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-07-31 22:32   ` Srivatsa, Anusha
2018-09-11 11:22   ` Singh, Gaurav K
2018-07-31 21:06 ` [PATCH v2 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-07-31 23:33   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-08-17 19:21   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-08-17 19:20   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-07-31 21:07 ` [PATCH v2 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-08-17 19:31   ` Srivatsa, Anusha
2018-08-23 20:08     ` Manasi Navare [this message]
2018-08-23 19:40   ` Harry Wentland
2018-08-23 20:12     ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-08-23 20:01   ` Harry Wentland
2018-08-28 21:12     ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-09-10 19:41   ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-07-31 21:16   ` Chris Wilson
2018-08-03 19:18     ` Manasi Navare
2018-08-03 19:43       ` Chris Wilson
2018-08-03 19:55         ` Manasi Navare
2018-08-23 19:58   ` Harry Wentland
2018-07-31 21:07 ` [PATCH v2 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-08-17 19:51   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-08-28 23:40   ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-08-09  5:55   ` Rodrigo Vivi
2018-08-23 19:22     ` Manasi Navare
2018-08-23 20:26       ` Rodrigo Vivi
2018-08-23 20:34     ` Dhinakaran Pandiyan
2018-08-23 20:57       ` Rodrigo Vivi
2018-08-29  6:52         ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-07-31 21:07 ` [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-08-28 22:18   ` Srivatsa, Anusha
2018-08-28 22:47     ` Manasi Navare
2018-08-28 23:31       ` Manasi Navare
2018-09-05 20:04   ` Manasi Navare
2018-09-05 20:33     ` Manasi Navare
2018-09-07  2:14       ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-09-05 21:10   ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-08-31 18:21   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-08-06 19:41   ` [PATCH v3] " Manasi Navare
2018-08-06 19:50   ` Manasi Navare
2018-07-31 21:07 ` [PATCH v2 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-08-28 22:57   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-08-31 18:35   ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 21/23] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-07-31 21:07 ` [PATCH v2 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-08-06 19:41   ` [PATCH v3] " Manasi Navare
2018-08-31 18:52     ` Srivatsa, Anusha
2018-07-31 21:07 ` [PATCH v2 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-08-31 21:42   ` Srivatsa, Anusha
2018-07-31 22:07 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP Patchwork
2018-07-31 22:08 ` Patchwork
2018-07-31 22:40 ` Patchwork
2018-08-06 19:40 ` ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP (rev2) Patchwork
2018-08-06 20:15 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev3) Patchwork
2018-08-06 20:25 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-08-06 20:31 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-07  0:21 ` ✓ Fi.CI.IGT: " Patchwork

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