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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: raviraj.p.sitaram@intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v1] drm/i915/chv: Update csc coefficient matrix during modeset
Date: Tue, 11 Sep 2018 16:51:24 +0300	[thread overview]
Message-ID: <20180911135124.GD5565@intel.com> (raw)
In-Reply-To: <1536589634-29680-1-git-send-email-raviraj.p.sitaram@intel.com>

On Mon, Sep 10, 2018 at 07:57:14PM +0530, raviraj.p.sitaram@intel.com wrote:
> From: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
> 
> During modeset, previously configured csc coefficient matrix,if any, will
> not persist. This can result in blank screen as csc mode will be programmed
> while loading LUT but csc coefficient matrix remains unprogrammed.
> 
> Changes since V1:
> - Removed platform check
> 
> Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>

Thanks for the patch. Pushed to dinq.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..2b77d9350a3a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6014,6 +6014,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_set_pipeconf(intel_crtc);
>  
> +	intel_color_set_csc(&pipe_config->base);
> +
>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      parent reply	other threads:[~2018-09-11 13:51 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-10 14:27 [PATCH v1] drm/i915/chv: Update csc coefficient matrix during modeset raviraj.p.sitaram
2018-09-10 16:11 ` ✓ Fi.CI.BAT: success for drm/i915/chv: Update csc coefficient matrix during modeset (rev2) Patchwork
2018-09-10 17:47 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 13:51 ` Ville Syrjälä [this message]

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