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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
	intel-gfx@lists.freedesktop.org, paulo.r.zanoni@intel.com,
	rodrigo.vivi@intel.com
Subject: Re: [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Date: Wed, 12 Sep 2018 21:00:21 +0300	[thread overview]
Message-ID: <20180912180021.GH5565@intel.com> (raw)
In-Reply-To: <2b6bcd05-0448-023c-19e1-d8be9f190690@intel.com>

On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> > On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> >> DSI transcoder registers.
> >>
> >> Credits-to: Jani N
> >>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >>   1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 1d13ba9..62bc76e 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >>   #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
> >>   #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
> >>   
> >> +/* gen11 DSI */
> >> +#define _DSI_TRANS(tc, dsi0, dsi1)	(((tc) == TRANSCODER_DSI_0) ?	\
> >> +					 (dsi0) : (dsi1))
> > _PIPE() etc. should result in slughtly better code IIRC.
> 
> Can you please clarify on this??

Plenty of examples in i915_reg.h for using _PIPE().

> 
> Regards,
> Madhav
> 
> >
> >> +#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> >> +
> >>   #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
> >>   #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
> >>   #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
> >> -- 
> >> 2.7.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-09-12 18:00 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-10  9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-19 16:11   ` Ville Syrjälä
2018-07-19 18:35     ` Chauhan, Madhav
2018-07-27 11:57       ` Chauhan, Madhav
2018-09-11 17:46         ` Jani Nikula
2018-09-12  6:32           ` Madhav Chauhan
2018-09-10 12:20   ` Lisovskiy, Stanislav
2018-09-10 15:27     ` Madhav Chauhan
2018-09-11  8:08       ` Lisovskiy, Stanislav
2018-07-10  9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-06 14:01   ` [v5, " Kulkarni, Vandita
2018-09-10  7:43     ` Madhav Chauhan
2018-09-11 18:16       ` Jani Nikula
2018-09-12  6:34         ` Madhav Chauhan
2018-09-11 18:50   ` [PATCH v5 " Jani Nikula
2018-09-12  9:03     ` Madhav Chauhan
2018-09-12  9:10       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-11 18:54   ` Jani Nikula
2018-09-12  9:06     ` Madhav Chauhan
2018-09-12  9:10       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-09-11 19:18   ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
2018-09-11 19:17   ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-11 19:14   ` Jani Nikula
2018-09-12  9:11     ` Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-19 16:17   ` Ville Syrjälä
2018-07-10  9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-09-11 19:23   ` Jani Nikula
2018-09-12  9:13     ` Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
2018-07-19 16:21   ` Ville Syrjälä
2018-07-20  8:08     ` Chauhan, Madhav
2018-09-11 19:26       ` Jani Nikula
2018-09-12  9:25         ` Madhav Chauhan
2018-09-12  9:39           ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-10  9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-19 16:22   ` Ville Syrjälä
2018-07-20  8:55     ` Chauhan, Madhav
2018-09-12  9:36     ` Madhav Chauhan
2018-09-12 18:00       ` Ville Syrjälä [this message]
2018-09-14  6:12         ` Madhav Chauhan
2018-09-14 12:25           ` Ville Syrjälä
2018-09-14 13:06             ` Madhav Chauhan
2018-09-14 13:27               ` Madhav Chauhan
2018-09-14 13:41                 ` Ville Syrjälä
2018-07-10  9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-09-11 19:30   ` Jani Nikula
2018-09-12  9:35     ` Madhav Chauhan
2018-09-12  9:47       ` Jani Nikula
2018-07-10  9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
2018-09-12  6:16   ` Madhav Chauhan
2018-09-12  7:31     ` Jani Nikula

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