Re: [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v7)

Chris Wilson
2018-10-29T21:47:12Z

Quoting Bob Paauwe (2018-10-29 21:39:49)
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
>
> Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> Also rename other functions and comments from 48bit to 4-level.
>
> Making use of the device info address range for gen6 highlights
> simularities in the gen6 and gen8 code paths so move the common
> code in to a common function.
>
> v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
> Remove unnecessary line coninuations (Bob)
> Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
> Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
> Gen 7 is 31 bits, not 32 (Chris)
> v5: Mock device is 64b(63b) not 48b (Chris)
> v6: Rebase to latest drm-tip (Bob)
> v7: Combine common code for gen6/gen8 ppgtt create (Chris)
> Improve comment on device info field (Chris)
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 139 ++++++++----------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
> drivers/gpu/drm/i915/i915_pci.c | 6 +
> drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> drivers/gpu/drm/i915/i915_vgpu.c | 4 +-
> drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 3 +
> drivers/gpu/drm/i915/intel_lrc.c | 6 +-
> drivers/gpu/drm/i915/selftests/huge_pages.c | 8 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 2 +
> 15 files changed, 90 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index c628be05fbfe..6002ded0042b 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;

The cap is actually full-ppgtt support. The 48b was accidental and gvt
now does both 3-lvl and 4-lvl aiui.
-Chris