Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v6)

Chris Wilson
2018-10-02T17:43:50Z

Quoting Bob Paauwe (2018-10-02 18:39:14)
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
>
> Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> Also rename other functions and comments from 48bit to 4-level.
>
> v2: keep HAS_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
> Remove unnecessary line coninuations (Bob)
> Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
> Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
> Gen 7 is 31 bits, not 32 (Chris)
> v5: mock device is 64b(63b) not 48b (Chris)
> v6: rebase to latest drm-tip (Bob)
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 5 +++++
> drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 3 +++
> drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
> drivers/gpu/drm/i915/selftests/huge_pages.c | 8 ++++----
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
> 14 files changed, 31 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index c628be05fbfe..6002ded0042b 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1b028f429e92..3b4852a89441 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1365,7 +1365,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>
> if (HAS_PPGTT(dev_priv)) {
> if (intel_vgpu_active(dev_priv) &&
> - !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> + !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
> i915_report_error(dev_priv,
> "incompatible vGPU found, support for isolated ppGTT required\n");
> return -ENXIO;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 30191523c309..54a44270d350 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2602,7 +2602,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> #define HAS_FULL_PPGTT(dev_priv) \
> (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> -#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> +#define HAS_4LVL_PPGTT(dev_priv) \
> (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
>
> #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 15c92f75b1b8..5de54ae949c3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
> desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>
> address_mode = INTEL_LEGACY_32B_CONTEXT;
> - if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> + if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> address_mode = INTEL_LEGACY_64B_CONTEXT;
> desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 29ca9007a704..06a91f67bc14 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> * page-table operating in 64K mode must point to a properly aligned 64K
> * region, including any PTEs which happen to point to scratch.
> *
> - * This is only relevant for the 48b PPGTT where we support
> + * This is only relevant for the 4-level PPGTT where we support
> * huge-gtt-pages, see also i915_vma_insert().
> *
> * TODO: we should really consider write-protecting the scratch-page and
> * sharing between ppgtt
> */
> size = I915_GTT_PAGE_SIZE_4K;
> - if (i915_vm_is_48bit(vm) &&
> + if (i915_vm_is_4lvl(vm) &&
> HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
> size = I915_GTT_PAGE_SIZE_64K;
> gfp |= __GFP_NOWARN;
> @@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
>
> static inline bool use_4lvl(const struct i915_address_space *vm)
> {
> - return i915_vm_is_48bit(vm);
> + return i915_vm_is_4lvl(vm);
> }
>
> static struct i915_page_directory_pointer *
> @@ -1598,9 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = &i915->drm.pdev->dev;
>
> - ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> - 1ULL << 48 :
> - 1ULL << 32;
> + ppgtt->vm.total = BIT_ULL(i915->info.ppgtt_bits);
>
> /*
> * From bdw, there is support for read-only pages in the PPGTT.
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 7e2af5f4f39b..b2a709a27cb9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -363,7 +363,7 @@ struct i915_address_space {
> #define i915_is_ggtt(vm) ((vm)->is_ggtt)
>
> static inline bool
> -i915_vm_is_48bit(const struct i915_address_space *vm)
> +i915_vm_is_4lvl(const struct i915_address_space *vm)
> {
> return (vm->total - 1) >> 32;
> }
> @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
> static inline unsigned int
> i915_pdpes_per_pdp(const struct i915_address_space *vm)
> {
> - if (i915_vm_is_48bit(vm))
> + if (i915_vm_is_4lvl(vm))
> return GEN8_PML4ES_PER_PML4;
>
> return GEN8_3LVL_PDPES;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9ddd2db906ce..acc33504ece0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -298,6 +298,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> .ppgtt = INTEL_PPGTT_FULL, \
> + .ppgtt_bits = 31, \
> GEN_DEFAULT_PIPEOFFSETS, \
> GEN_DEFAULT_PAGE_SIZES, \
> IVB_CURSOR_OFFSETS
> @@ -351,6 +352,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .has_gmch_display = 1,
> .has_hotplug = 1,
> .ppgtt = INTEL_PPGTT_FULL,
> + .ppgtt_bits = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -398,6 +400,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> I915_GTT_PAGE_SIZE_2M, \
> .has_logical_ring_contexts = 1, \
> .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_bits = 48, \
> .has_64bit_reloc = 1, \
> .has_reset_engine = 1
>
> @@ -442,6 +445,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_logical_ring_contexts = 1,
> .has_gmch_display = 1,
> .ppgtt = INTEL_PPGTT_FULL,
> + .ppgtt_bits = 32,
> .has_reset_engine = 1,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> @@ -518,6 +522,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .has_logical_ring_preemption = 1, \
> .has_guc = 1, \
> .ppgtt = INTEL_PPGTT_FULL_4LVL, \

You appear to have only written half the patch.

> + .ppgtt_bits = 48, \
> .has_reset_engine = 1, \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..bc7cbdca02aa 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
> /*
> * VGT capabilities type
> */
> -#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
> +#define VGT_CAPS_4LVL_PPGTT BIT(2)
> #define VGT_CAPS_HWSP_EMULATION BIT(3)
> #define VGT_CAPS_HUGE_GTT BIT(4)
>
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..4ecb4d6e67f8 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> }
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
> {
> - return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> + return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
> }
>
> struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..5265b6357fba 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>
> void i915_check_vgpu(struct drm_i915_private *dev_priv);
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
>
> static inline bool
> intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index af7002640cdf..1b14d7df324b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -189,6 +189,9 @@ struct intel_device_info {
> u16 degamma_lut_size;
> u16 gamma_lut_size;
> } color;
> +
> + /* PPGTT address limit */
> + int ppgtt_bits;

Comment doesn't help very much, should be associated with the
ppgtt_type.
-Chris