From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915/execlists: Use coherent writes into the context image
Date: Fri, 14 Sep 2018 16:39:23 +0300 [thread overview]
Message-ID: <20180914133923.GC5565@intel.com> (raw)
In-Reply-To: <153693097198.4114.13742793742769508199@skylake-alporthouse-com>
On Fri, Sep 14, 2018 at 02:16:12PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-14 14:03:35)
> > On Fri, Sep 14, 2018 at 10:42:15AM +0100, Chris Wilson wrote:
> > > That we use a WB mapping for updating the RING_TAIL register inside the
> > > context image even on !llc machines has been a source of consternation
> > > for every reader. It appears to work on bsw+, but it may just have been
> > > that we have been incredibly bad at detecting the errors.
> >
> > Presumably it's due to the "all ggtt accesses go through pat[0]" and
> > we make pat[0] snoop. So presumably the hw should snoop when loading
> > the context... maybe.
>
> Shows how much attention I pay, I thought we made pat[0] uncached. Seems
> strange to suggest that we should always be snooping when reading GGTT
> from the GPU.
IIRC I did it originally that way for the status page. Sadly it's
either "all snooped" or "none snooped" due to the hw not having
wired up the bits for ggtt.
>
> We still have the same PTE bits for GGTT as for ppGTT, do we not?
Same, except the pwt/pcd/pat bits do nothing for ggtt.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2018-09-14 13:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-14 9:42 [PATCH 1/4] drm/i915/execlists: Delay updating ring register state after resume Chris Wilson
2018-09-14 9:42 ` [PATCH 2/4] drm/i915: Park the GPU on module load Chris Wilson
2018-09-14 9:42 ` [PATCH 3/4] drm/i915: Check engine->default_state mapping " Chris Wilson
2018-09-14 11:02 ` Tvrtko Ursulin
2018-09-14 9:42 ` [PATCH 4/4] drm/i915/execlists: Use coherent writes into the context image Chris Wilson
2018-09-14 13:03 ` Ville Syrjälä
2018-09-14 13:16 ` Chris Wilson
2018-09-14 13:39 ` Ville Syrjälä [this message]
2018-09-14 12:29 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/execlists: Delay updating ring register state after resume Patchwork
2018-09-14 12:47 ` ✗ Fi.CI.BAT: failure " Patchwork
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