* [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
@ 2018-09-14 14:18 José Roberto de Souza
2018-09-14 14:18 ` [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: José Roberto de Souza @ 2018-09-14 14:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Instead of have the same code spread into 4 platforms lets share it.
BXT do not have a PCH so here also handling this case by unseting
RESET_PCH_HANDSHAKE_ENABLE.
v2(Rodrigo):
- renamed to intel_pch_reset_handshake()
- added comment about why BXT need the bit to be unset
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++-------------
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9bebec389de1..1bcd0e51fca1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3239,18 +3239,29 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
I915_WRITE(MBUS_ABOX_CTL, val);
}
+static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
+{
+ u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+ /* BXT don't have PCH and it requires that this bit is always unset */
+ if (HAS_PCH_SPLIT(dev_priv))
+ val |= RESET_PCH_HANDSHAKE_ENABLE;
+ else
+ val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+
+ I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+}
+
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- uint32_t val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* enable PCH reset handshake */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
+ intel_pch_reset_handshake(dev_priv);
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
@@ -3306,19 +3317,10 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
- uint32_t val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /*
- * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
- * or else the reset will hang because there is no PCH to respond.
- * Move the handshake programming to initialization sequence.
- * Previously was left up to BIOS.
- */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val &= ~RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ intel_pch_reset_handshake(dev_priv);
/* Enable PG1 */
mutex_lock(&power_domains->lock);
@@ -3439,9 +3441,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH Reset Handshake */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ intel_pch_reset_handshake(dev_priv);
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
@@ -3524,9 +3524,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
/* 1. Enable PCH reset handshake. */
- val = I915_READ(HSW_NDE_RSTWRN_OPT);
- val |= RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+ intel_pch_reset_handshake(dev_priv);
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
--
2.19.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place
2018-09-14 14:18 [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake José Roberto de Souza
@ 2018-09-14 14:18 ` José Roberto de Souza
2018-09-14 14:54 ` Ville Syrjälä
2018-09-14 14:18 ` [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC José Roberto de Souza
2018-09-14 14:52 ` [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Ville Syrjälä
2 siblings, 1 reply; 8+ messages in thread
From: José Roberto de Souza @ 2018-09-14 14:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
i915_gem_init_hw().
So making skl_pch_reset_handshake() handle both cases and calling
it for the missing gens in intel_power_domains_init_hw().
Ivybridge have a different register and bits but with the same
objective so moving it too.
v2(Rodrigo):
- handling IVYBRIDGE case inside intel_pch_reset_handshake()
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 12 ------------
drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++++++++++---
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 89834ce19acd..b389e084c8c6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5296,18 +5296,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
- if (HAS_PCH_NOP(dev_priv)) {
- if (IS_IVYBRIDGE(dev_priv)) {
- u32 temp = I915_READ(GEN7_MSG_CTL);
- temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
- I915_WRITE(GEN7_MSG_CTL, temp);
- } else if (INTEL_GEN(dev_priv) >= 7) {
- u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
- temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
- I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
- }
- }
-
intel_gt_workarounds_apply(dev_priv);
i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1bcd0e51fca1..bca1976fdb1d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3241,10 +3241,22 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
{
- u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+ u32 val;
+
+ if (IS_IVYBRIDGE(dev_priv)) {
+ if (HAS_PCH_NOP(dev_priv)) {
+ val = I915_READ(GEN7_MSG_CTL);
+ val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+ I915_WRITE(GEN7_MSG_CTL, val);
+ }
+
+ return;
+ }
+
+ val = I915_READ(HSW_NDE_RSTWRN_OPT);
/* BXT don't have PCH and it requires that this bit is always unset */
- if (HAS_PCH_SPLIT(dev_priv))
+ if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv))
val |= RESET_PCH_HANDSHAKE_ENABLE;
else
val &= ~RESET_PCH_HANDSHAKE_ENABLE;
@@ -3756,7 +3768,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
- }
+ } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
+ intel_pch_reset_handshake(dev_priv);
/*
* Keep all power wells enabled for any dependent HW access during
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place
2018-09-14 14:18 ` [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
@ 2018-09-14 14:54 ` Ville Syrjälä
0 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2018-09-14 14:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Sep 14, 2018 at 07:18:45AM -0700, José Roberto de Souza wrote:
> Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> i915_gem_init_hw().
> So making skl_pch_reset_handshake() handle both cases and calling
> it for the missing gens in intel_power_domains_init_hw().
> Ivybridge have a different register and bits but with the same
> objective so moving it too.
>
> v2(Rodrigo):
> - handling IVYBRIDGE case inside intel_pch_reset_handshake()
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 12 ------------
> drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++++++++++---
> 2 files changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 89834ce19acd..b389e084c8c6 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5296,18 +5296,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> - if (HAS_PCH_NOP(dev_priv)) {
> - if (IS_IVYBRIDGE(dev_priv)) {
> - u32 temp = I915_READ(GEN7_MSG_CTL);
> - temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> - I915_WRITE(GEN7_MSG_CTL, temp);
> - } else if (INTEL_GEN(dev_priv) >= 7) {
> - u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
> - temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> - }
> - }
> -
> intel_gt_workarounds_apply(dev_priv);
>
> i915_gem_init_swizzling(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1bcd0e51fca1..bca1976fdb1d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3241,10 +3241,22 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>
> static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
> {
> - u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> + u32 val;
> +
> + if (IS_IVYBRIDGE(dev_priv)) {
> + if (HAS_PCH_NOP(dev_priv)) {
> + val = I915_READ(GEN7_MSG_CTL);
> + val &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> + I915_WRITE(GEN7_MSG_CTL, val);
> + }
> +
> + return;
> + }
I'd go with if-else since both sides are pretty much equal.
> +
> + val = I915_READ(HSW_NDE_RSTWRN_OPT);
>
> /* BXT don't have PCH and it requires that this bit is always unset */
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv))
> val |= RESET_PCH_HANDSHAKE_ENABLE;
> else
> val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> @@ -3756,7 +3768,8 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> mutex_lock(&power_domains->lock);
> vlv_cmnlane_wa(dev_priv);
> mutex_unlock(&power_domains->lock);
> - }
> + } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7)
> + intel_pch_reset_handshake(dev_priv);
>
> /*
> * Keep all power wells enabled for any dependent HW access during
> --
> 2.19.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC
2018-09-14 14:18 [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake José Roberto de Souza
2018-09-14 14:18 ` [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
@ 2018-09-14 14:18 ` José Roberto de Souza
2018-09-14 15:36 ` Rodrigo Vivi
2018-09-14 14:52 ` [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Ville Syrjälä
2 siblings, 1 reply; 8+ messages in thread
From: José Roberto de Souza @ 2018-09-14 14:18 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
IPC was only added in SKL+(actually we don't even enable for SKL due
WA) so without this change, driver was writing to a reserved bit.
Also removing the uncessary dev_priv->ipc_enabled = false; as now
gens without IPC will not have IPC enabled.
v2(Rodrigo):
- moved the new handling of WA #0477 to the next patch
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db9b8328275..e2ca04534e23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6117,6 +6117,9 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
{
u32 val;
+ if (!HAS_IPC(dev_priv))
+ return;
+
/* Display WA #0477 WaDisableIPC: skl */
if (IS_SKYLAKE(dev_priv))
dev_priv->ipc_enabled = false;
@@ -6138,7 +6141,6 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
void intel_init_ipc(struct drm_i915_private *dev_priv)
{
- dev_priv->ipc_enabled = false;
if (!HAS_IPC(dev_priv))
return;
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC
2018-09-14 14:18 ` [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC José Roberto de Souza
@ 2018-09-14 15:36 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2018-09-14 15:36 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Sep 14, 2018 at 07:18:46AM -0700, José Roberto de Souza wrote:
> IPC was only added in SKL+(actually we don't even enable for SKL due
> WA) so without this change, driver was writing to a reserved bit.
>
> Also removing the uncessary dev_priv->ipc_enabled = false; as now
> gens without IPC will not have IPC enabled.
>
> v2(Rodrigo):
> - moved the new handling of WA #0477 to the next patch
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1db9b8328275..e2ca04534e23 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6117,6 +6117,9 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> + if (!HAS_IPC(dev_priv))
> + return;
> +
> /* Display WA #0477 WaDisableIPC: skl */
> if (IS_SKYLAKE(dev_priv))
> dev_priv->ipc_enabled = false;
> @@ -6138,7 +6141,6 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
>
> void intel_init_ipc(struct drm_i915_private *dev_priv)
> {
> - dev_priv->ipc_enabled = false;
> if (!HAS_IPC(dev_priv))
> return;
>
> --
> 2.19.0
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
2018-09-14 14:18 [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake José Roberto de Souza
2018-09-14 14:18 ` [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
2018-09-14 14:18 ` [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC José Roberto de Souza
@ 2018-09-14 14:52 ` Ville Syrjälä
2018-09-14 15:37 ` Rodrigo Vivi
2 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2018-09-14 14:52 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Sep 14, 2018 at 07:18:44AM -0700, José Roberto de Souza wrote:
> Instead of have the same code spread into 4 platforms lets share it.
> BXT do not have a PCH so here also handling this case by unseting
> RESET_PCH_HANDSHAKE_ENABLE.
>
> v2(Rodrigo):
> - renamed to intel_pch_reset_handshake()
> - added comment about why BXT need the bit to be unset
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++-------------
> 1 file changed, 17 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 9bebec389de1..1bcd0e51fca1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3239,18 +3239,29 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
> I915_WRITE(MBUS_ABOX_CTL, val);
> }
>
> +static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
> +{
> + u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +
> + /* BXT don't have PCH and it requires that this bit is always unset */
> + if (HAS_PCH_SPLIT(dev_priv))
Still would prefer 'bool enable' etc. rather than this magic inside.
> + val |= RESET_PCH_HANDSHAKE_ENABLE;
> + else
> + val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +
> + I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +}
> +
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> - uint32_t val;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> /* enable PCH reset handshake */
> - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
> + intel_pch_reset_handshake(dev_priv);
>
> /* enable PG1 and Misc I/O */
> mutex_lock(&power_domains->lock);
> @@ -3306,19 +3317,10 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> - uint32_t val;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - /*
> - * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> - * or else the reset will hang because there is no PCH to respond.
> - * Move the handshake programming to initialization sequence.
> - * Previously was left up to BIOS.
> - */
> - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> - val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> + intel_pch_reset_handshake(dev_priv);
>
> /* Enable PG1 */
> mutex_lock(&power_domains->lock);
> @@ -3439,9 +3441,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> /* 1. Enable PCH Reset Handshake */
> - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> - val |= RESET_PCH_HANDSHAKE_ENABLE;
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> + intel_pch_reset_handshake(dev_priv);
>
> /* 2. Enable Comp */
> val = I915_READ(CHICKEN_MISC_2);
> @@ -3524,9 +3524,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> /* 1. Enable PCH reset handshake. */
> - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> - val |= RESET_PCH_HANDSHAKE_ENABLE;
> - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> + intel_pch_reset_handshake(dev_priv);
>
> for (port = PORT_A; port <= PORT_B; port++) {
> /* 2. Enable DDI combo PHY comp. */
> --
> 2.19.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
2018-09-14 14:52 ` [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Ville Syrjälä
@ 2018-09-14 15:37 ` Rodrigo Vivi
2018-09-17 21:28 ` Souza, Jose
0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2018-09-14 15:37 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Sep 14, 2018 at 05:52:39PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 14, 2018 at 07:18:44AM -0700, José Roberto de Souza wrote:
> > Instead of have the same code spread into 4 platforms lets share it.
> > BXT do not have a PCH so here also handling this case by unseting
> > RESET_PCH_HANDSHAKE_ENABLE.
> >
> > v2(Rodrigo):
> > - renamed to intel_pch_reset_handshake()
> > - added comment about why BXT need the bit to be unset
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++-------------
> > 1 file changed, 17 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 9bebec389de1..1bcd0e51fca1 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3239,18 +3239,29 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
> > I915_WRITE(MBUS_ABOX_CTL, val);
> > }
> >
> > +static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv)
> > +{
> > + u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > +
> > + /* BXT don't have PCH and it requires that this bit is always unset */
> > + if (HAS_PCH_SPLIT(dev_priv))
>
> Still would prefer 'bool enable' etc. rather than this magic inside.
I agree. So we could keep the original BXT comment where it is...
>
> > + val |= RESET_PCH_HANDSHAKE_ENABLE;
> > + else
> > + val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > +
> > + I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > +}
> > +
> > static void skl_display_core_init(struct drm_i915_private *dev_priv,
> > bool resume)
> > {
> > struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > struct i915_power_well *well;
> > - uint32_t val;
> >
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >
> > /* enable PCH reset handshake */
> > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
> > + intel_pch_reset_handshake(dev_priv);
> >
> > /* enable PG1 and Misc I/O */
> > mutex_lock(&power_domains->lock);
> > @@ -3306,19 +3317,10 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> > {
> > struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > struct i915_power_well *well;
> > - uint32_t val;
> >
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >
> > - /*
> > - * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> > - * or else the reset will hang because there is no PCH to respond.
> > - * Move the handshake programming to initialization sequence.
> > - * Previously was left up to BIOS.
> > - */
> > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > - val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > + intel_pch_reset_handshake(dev_priv);
> >
> > /* Enable PG1 */
> > mutex_lock(&power_domains->lock);
> > @@ -3439,9 +3441,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >
> > /* 1. Enable PCH Reset Handshake */
> > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > - val |= RESET_PCH_HANDSHAKE_ENABLE;
> > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > + intel_pch_reset_handshake(dev_priv);
> >
> > /* 2. Enable Comp */
> > val = I915_READ(CHICKEN_MISC_2);
> > @@ -3524,9 +3524,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >
> > /* 1. Enable PCH reset handshake. */
> > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > - val |= RESET_PCH_HANDSHAKE_ENABLE;
> > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > + intel_pch_reset_handshake(dev_priv);
> >
> > for (port = PORT_A; port <= PORT_B; port++) {
> > /* 2. Enable DDI combo PHY comp. */
> > --
> > 2.19.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake
2018-09-14 15:37 ` Rodrigo Vivi
@ 2018-09-17 21:28 ` Souza, Jose
0 siblings, 0 replies; 8+ messages in thread
From: Souza, Jose @ 2018-09-17 21:28 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, Vivi, Rodrigo
Cc: intel-gfx@lists.freedesktop.org
On Fri, 2018-09-14 at 08:37 -0700, Rodrigo Vivi wrote:
> On Fri, Sep 14, 2018 at 05:52:39PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 14, 2018 at 07:18:44AM -0700, José Roberto de Souza
> > wrote:
> > > Instead of have the same code spread into 4 platforms lets share
> > > it.
> > > BXT do not have a PCH so here also handling this case by unseting
> > > RESET_PCH_HANDSHAKE_ENABLE.
> > >
> > > v2(Rodrigo):
> > > - renamed to intel_pch_reset_handshake()
> > > - added comment about why BXT need the bit to be unset
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++-------
> > > ------
> > > 1 file changed, 17 insertions(+), 19 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 9bebec389de1..1bcd0e51fca1 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -3239,18 +3239,29 @@ static void icl_mbus_init(struct
> > > drm_i915_private *dev_priv)
> > > I915_WRITE(MBUS_ABOX_CTL, val);
> > > }
> > >
> > > +static void intel_pch_reset_handshake(struct drm_i915_private
> > > *dev_priv)
> > > +{
> > > + u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > +
> > > + /* BXT don't have PCH and it requires that this bit is always
> > > unset */
> > > + if (HAS_PCH_SPLIT(dev_priv))
> >
> > Still would prefer 'bool enable' etc. rather than this magic
> > inside.
>
> I agree. So we could keep the original BXT comment where it is...
Several other places also uses HAS_PCH_SPLIT() to differentiate BXT of
other platforms so it is not something new, also adding the 'bool
enable' would move part of the "magic" to the callers as we need to
check if HAS_PCH_NOP(dev_priv) is true in the next patch and unset the
handshake.
>
> >
> > > + val |= RESET_PCH_HANDSHAKE_ENABLE;
> > > + else
> > > + val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > > +
> > > + I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > > +}
> > > +
> > > static void skl_display_core_init(struct drm_i915_private
> > > *dev_priv,
> > > bool resume)
> > > {
> > > struct i915_power_domains *power_domains = &dev_priv-
> > > >power_domains;
> > > struct i915_power_well *well;
> > > - uint32_t val;
> > >
> > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >
> > > /* enable PCH reset handshake */
> > > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val |
> > > RESET_PCH_HANDSHAKE_ENABLE);
> > > + intel_pch_reset_handshake(dev_priv);
> > >
> > > /* enable PG1 and Misc I/O */
> > > mutex_lock(&power_domains->lock);
> > > @@ -3306,19 +3317,10 @@ void bxt_display_core_init(struct
> > > drm_i915_private *dev_priv,
> > > {
> > > struct i915_power_domains *power_domains = &dev_priv-
> > > >power_domains;
> > > struct i915_power_well *well;
> > > - uint32_t val;
> > >
> > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >
> > > - /*
> > > - * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
> > > - * or else the reset will hang because there is no PCH to
> > > respond.
> > > - * Move the handshake programming to initialization sequence.
> > > - * Previously was left up to BIOS.
> > > - */
> > > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > - val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> > > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > > + intel_pch_reset_handshake(dev_priv);
> > >
> > > /* Enable PG1 */
> > > mutex_lock(&power_domains->lock);
> > > @@ -3439,9 +3441,7 @@ static void cnl_display_core_init(struct
> > > drm_i915_private *dev_priv, bool resume
> > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >
> > > /* 1. Enable PCH Reset Handshake */
> > > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > - val |= RESET_PCH_HANDSHAKE_ENABLE;
> > > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > > + intel_pch_reset_handshake(dev_priv);
> > >
> > > /* 2. Enable Comp */
> > > val = I915_READ(CHICKEN_MISC_2);
> > > @@ -3524,9 +3524,7 @@ static void icl_display_core_init(struct
> > > drm_i915_private *dev_priv,
> > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >
> > > /* 1. Enable PCH reset handshake. */
> > > - val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > - val |= RESET_PCH_HANDSHAKE_ENABLE;
> > > - I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > > + intel_pch_reset_handshake(dev_priv);
> > >
> > > for (port = PORT_A; port <= PORT_B; port++) {
> > > /* 2. Enable DDI combo PHY comp. */
> > > --
> > > 2.19.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-09-17 21:28 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-09-14 14:18 [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake José Roberto de Souza
2018-09-14 14:18 ` [PATCH v2 2/6] drm/i915: Unset reset pch handshake when PCH is not present in one place José Roberto de Souza
2018-09-14 14:54 ` Ville Syrjälä
2018-09-14 14:18 ` [PATCH v2 3/6] drm/i915: Do not modifiy reserved bit in gens that do not have IPC José Roberto de Souza
2018-09-14 15:36 ` Rodrigo Vivi
2018-09-14 14:52 ` [PATCH v2 1/6] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake Ville Syrjälä
2018-09-14 15:37 ` Rodrigo Vivi
2018-09-17 21:28 ` Souza, Jose
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