[PATCH v6 00/20] ICELAKE DSI DRIVER

[PATCH v6 00/20] ICELAKE DSI DRIVER

[Madhav Chauhan]

From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.

So, a new DSI driver has been added inside I915.

Given below patches are the part of new DSI driver which implements BSPEC
sequence till panel programming. Rest of the patches will be published
to GITHUB.

v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
    Ville. Also addressed review comments for couple of patches.
v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
v5: Rebase on drm-tip after initial 7 patches got merged.
v6: Addressed various review comments from Jani N, Ville, Vandita.

Madhav Chauhan (20):
  drm/i915/icl: Configure lane sequencing of combo phy transmitter
  drm/i915/icl: DSI vswing programming sequence
  drm/i915/icl: Enable DDI Buffer
  drm/i915/icl: Program T_INIT_MASTER registers
  drm/i915/icl: Define data/clock lanes dphy timing registers
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Define TA_TIMING_PARAM registers
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders
  drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
  drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
  drm/i915/icl: Define DSI transcoder timing registers
  drm/i915/icl: Configure DSI transcoder timings
  drm/i915/icl: Define TRANS_CONF register for DSI
  drm/i915/icl: Enable DSI transcoders
  drm/i915/icl: Define DSI panel programming registers
  drm/i915/icl: Set max return packet size for DSI panel

 drivers/gpu/drm/i915/i915_pci.c      |   6 +-
 drivers/gpu/drm/i915/i915_reg.h      | 208 +++++++++++++
 drivers/gpu/drm/i915/icl_dsi.c       | 567 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.h     |   7 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++++++++----
 6 files changed, 934 insertions(+), 62 deletions(-)

-- 
2.7.4

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[PATCH v6 01/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter

[Madhav Chauhan]

This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.

v2: Rebase
v3: Add empty line to make code more legible (Ville).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 13830e4..1607cac 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -105,10 +105,49 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	/* Step 4b(i) set loadgen select for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp &= ~LOADGEN_SELECT;
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+		for (lane = 0; lane <= 3; lane++) {
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp &= ~LOADGEN_SELECT;
+			if (lane != 2)
+				tmp |= LOADGEN_SELECT;
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+
+	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp &= ~FRC_LATENCY_OPTIM_MASK;
+		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+	}
+
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
+
+	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
+	gen11_dsi_config_phy_lanes_sequence(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v6 02/20] drm/i915/icl: DSI vswing programming sequence

[Madhav Chauhan]

This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.

v2: Rebase
v3: Address various review comments related to VSWING
    programming (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 120 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 1607cac..e5c18a8 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,71 @@
 
 #include "intel_dsi.h"
 
+static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+	int lane;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+
+		/*
+		 * Program voltage swing and pre-emphasis level values as per
+		 * table in BSPEC under DDI buffer programing
+		 */
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
+		tmp |= SCALING_MODE_SEL(0x2);
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		tmp |= RTERM_SELECT(0x6);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
+		tmp |= SCALING_MODE_SEL(0x2);
+		tmp |= TAP2_DISABLE | TAP3_DISABLE;
+		tmp |= RTERM_SELECT(0x6);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+			 RCOMP_SCALAR_MASK);
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+			 RCOMP_SCALAR_MASK);
+		tmp |= SWING_SEL_UPPER(0x2);
+		tmp |= SWING_SEL_LOWER(0x2);
+		tmp |= RCOMP_SCALAR(0x98);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+			 CURSOR_COEFF_MASK);
+		tmp |= POST_CURSOR_1(0x0);
+		tmp |= POST_CURSOR_2(0x0);
+		tmp |= CURSOR_COEFF(0x3f);
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+
+		for (lane = 0; lane <= 3; lane++) {
+			/* Bspec: must not use GRP register for write */
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+			tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
+				 CURSOR_COEFF_MASK);
+			tmp |= POST_CURSOR_1(0x0);
+			tmp |= POST_CURSOR_2(0x0);
+			tmp |= CURSOR_COEFF(0x3f);
+			I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+		}
+	}
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -141,6 +206,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 
 }
 
+static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* clear common keeper enable bit */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+		tmp &= ~COMMON_KEEPER_EN;
+		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+	}
+
+	/*
+	 * Set SUS Clock Config bitfield to 11b
+	 * Note: loadgen select program is done
+	 * as part of lane phy sequence configuration
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_CL_DW5(port));
+		tmp |= SUS_CLOCK_CONFIG;
+		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+	}
+
+	/* Clear training enable to change swing values */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp &= ~TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+
+	/* Program swing and de-emphasis */
+	dsi_program_swing_and_deemphasis(encoder);
+
+	/* Set training enable to trigger update */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp |= TX_TRAINING_EN;
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -148,6 +265,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 	gen11_dsi_config_phy_lanes_sequence(encoder);
+
+	/* step 4c: configure voltage swing and skew */
+	gen11_dsi_voltage_swing_program_seq(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v6 03/20] drm/i915/icl: Enable DDI Buffer

[Madhav Chauhan]

This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.

v2: Rebase
v3: Remove step hard coding comments (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index e5c18a8..190316c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -258,6 +258,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(DDI_BUF_CTL(port));
+		tmp |= DDI_BUF_CTL_ENABLE;
+		I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+		if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
+				  DDI_BUF_IS_IDLE),
+				  500))
+			DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -268,6 +287,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* step 4c: configure voltage swing and skew */
 	gen11_dsi_voltage_swing_program_seq(encoder);
+
+	/* enable DDI buffer */
+	gen11_dsi_enable_ddi_buffer(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v6 04/20] drm/i915/icl: Program T_INIT_MASTER registers

[Madhav Chauhan]

This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.

v2: Rebase
v3: Remove step hard coding comments (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 190316c..ff5b285 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -277,6 +277,22 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	/* Program T-INIT master registers */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
+		tmp &= ~MASTER_INIT_TIMER_MASK;
+		tmp |= intel_dsi->init_count;
+		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -290,6 +306,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* enable DDI buffer */
 	gen11_dsi_enable_ddi_buffer(encoder);
+
+	/* setup D-PHY timings */
+	gen11_dsi_setup_dphy_timings(encoder);
 }
 
 static void __attribute__((unused))
-- 
2.7.4

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[PATCH v6 05/20] drm/i915/icl: Define data/clock lanes dphy timing registers

[Madhav Chauhan]

This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 58 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4948b35..6c8999d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10285,6 +10285,64 @@ enum skl_power_gate {
 						   _ICL_DSI_T_INIT_MASTER_0,\
 						   _ICL_DSI_T_INIT_MASTER_1)
 
+#define _DPHY_CLK_TIMING_PARAM_0	0x162180
+#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
+#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_CLK_TIMING_PARAM_0,\
+						   _DPHY_CLK_TIMING_PARAM_1)
+#define _DSI_CLK_TIMING_PARAM_0		0x6b080
+#define _DSI_CLK_TIMING_PARAM_1		0x6b880
+#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_CLK_TIMING_PARAM_0,\
+						   _DSI_CLK_TIMING_PARAM_1)
+#define  CLK_PREPARE_OVERRIDE		(1 << 31)
+#define  CLK_PREPARE(x)		((x) << 28)
+#define  CLK_PREPARE_MASK		(0x7 << 28)
+#define  CLK_PREPARE_SHIFT		28
+#define  CLK_ZERO_OVERRIDE		(1 << 27)
+#define  CLK_ZERO(x)			((x) << 20)
+#define  CLK_ZERO_MASK			(0xf << 20)
+#define  CLK_ZERO_SHIFT		20
+#define  CLK_PRE_OVERRIDE		(1 << 19)
+#define  CLK_PRE(x)			((x) << 16)
+#define  CLK_PRE_MASK			(0x3 << 16)
+#define  CLK_PRE_SHIFT			16
+#define  CLK_POST_OVERRIDE		(1 << 15)
+#define  CLK_POST(x)			((x) << 8)
+#define  CLK_POST_MASK			(0x7 << 8)
+#define  CLK_POST_SHIFT		8
+#define  CLK_TRAIL_OVERRIDE		(1 << 7)
+#define  CLK_TRAIL(x)			((x) << 0)
+#define  CLK_TRAIL_MASK		(0xf << 0)
+#define  CLK_TRAIL_SHIFT		0
+
+#define _DPHY_DATA_TIMING_PARAM_0	0x162184
+#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
+#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_DATA_TIMING_PARAM_0,\
+						   _DPHY_DATA_TIMING_PARAM_1)
+#define _DSI_DATA_TIMING_PARAM_0	0x6B084
+#define _DSI_DATA_TIMING_PARAM_1	0x6B884
+#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_DATA_TIMING_PARAM_0,\
+						   _DSI_DATA_TIMING_PARAM_1)
+#define  HS_PREPARE_OVERRIDE		(1 << 31)
+#define  HS_PREPARE(x)			((x) << 24)
+#define  HS_PREPARE_MASK		(0x7 << 24)
+#define  HS_PREPARE_SHIFT		24
+#define  HS_ZERO_OVERRIDE		(1 << 23)
+#define  HS_ZERO(x)			((x) << 16)
+#define  HS_ZERO_MASK			(0xf << 16)
+#define  HS_ZERO_SHIFT			16
+#define  HS_TRAIL_OVERRIDE		(1 << 15)
+#define  HS_TRAIL(x)			((x) << 8)
+#define  HS_TRAIL_MASK			(0x7 << 8)
+#define  HS_TRAIL_SHIFT		8
+#define  HS_EXIT_OVERRIDE		(1 << 7)
+#define  HS_EXIT(x)			((x) << 0)
+#define  HS_EXIT_MASK			(0x7 << 0)
+#define  HS_EXIT_SHIFT			0
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v6 06/20] drm/i915/icl: Program DSI clock and data lane timing params

[Madhav Chauhan]

This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.

v2: Use newly defined bitfields for data and clock lane

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++
 drivers/gpu/drm/i915/intel_dsi.h     |   3 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +++++++++++++++++++++++++----------
 3 files changed, 165 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ff5b285..9602b65 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		tmp |= intel_dsi->init_count;
 		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 	}
+
+	/* Program DPHY clock lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+	}
+
+	/* Program DPHY data lanes timings */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+
+		/* shadow register inside display core */
+		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+			   intel_dsi->dphy_data_lane_reg);
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ad7c1cb..9fd8526 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
+
+	/* data lanes dphy timing */
+	u32 dphy_data_lane_reg;
 	u32 video_frmt_cfg_bits;
 	u16 lp_byte_clk;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index ac83d6b..fbb159b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	u32 bpp;
 	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 	u32 ui_num, ui_den;
-	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
+	u32 tclk_pre_cnt, tclk_post_cnt;
+	u32 tclk_pre_ns, tclk_post_ns;
 	u32 ths_prepare_ns, tclk_trail_ns;
 	u32 tclk_prepare_clkzero, ths_prepare_hszero;
 	u32 lp_to_hs_switch, hs_to_lp_switch;
@@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-
+	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);
 	/*
 	 * B060
 	 * LP byte clock = TLPX/ (8UI)
 	 */
 	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 
-	/* DDR clock period = 2 * UI
-	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
-	 * UI(nsec) = 10^6 / bitrate
-	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
-	 * DDR clock count  = ns_value / DDR clock period
-	 *
+	/*
 	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
 	 * HS byte clock count for other platform in HS ddr clock count
 	 */
 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
-	ths_prepare_ns = max(mipi_config->ths_prepare,
-			     mipi_config->tclk_prepare);
 
-	/* prepare count */
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
+	if (IS_ICELAKE(dev_priv)) {
+		/*
+		 * prepare cnt in escape clocks
+		 * this field represents a hexadecimal value with a precision
+		 * of 1.2 – i.e. the most significant bit is the integer
+		 * and the least significant 2 bits are fraction bits.
+		 * so, the field can represent a range of 0.25 to 1.75
+		 */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+
+		/* clk zero count in escape clocks */
+		clk_zero_cnt = DIV_ROUND_UP(
+					(tclk_prepare_clkzero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* trail cnt in escape clocks*/
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
+
+		/* tclk pre/post count in escape clocks */
+		tclk_post_ns = mipi_config->tclk_post;
+		tclk_pre_ns = mipi_config->tclk_pre;
+		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
+		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
+
+		/* hs zero cnt in escape clocks */
+		hs_zero_cnt = DIV_ROUND_UP(
+					(ths_prepare_hszero - ths_prepare_ns),
+					tlpx_ns);
+
+		/* hs exit zero cnt in escape clocks */
+		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
+
+		if (prepare_cnt > 0x7 ||
+		    clk_zero_cnt > 0xF ||
+		    tclk_pre_cnt > 0x3 ||
+		    tclk_post_cnt > 0x7 ||
+		    trail_cnt > 0x7 ||
+		    hs_zero_cnt > 0xF ||
+		    exit_zero_cnt > 0x7) {
+			DRM_DEBUG_DRIVER("DPHY values crossing max limits,");
+			DRM_DEBUG_DRIVER("restricting to max values\n");
+		}
+
+		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
+		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
+		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
+		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
+		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
+		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
+		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
+
+		/* clock lane dphy timings */
+		intel_dsi->dphy_reg |= (CLK_PREPARE_OVERRIDE |
+					CLK_PREPARE(prepare_cnt) |
+					CLK_ZERO_OVERRIDE |
+					CLK_ZERO(clk_zero_cnt) |
+					CLK_PRE_OVERRIDE |
+					CLK_PRE(tclk_pre_cnt) |
+					CLK_POST_OVERRIDE |
+					CLK_POST(tclk_post_cnt) |
+					CLK_TRAIL_OVERRIDE |
+					CLK_TRAIL(trail_cnt));
+
+		/* data lanes dphy timings */
+		intel_dsi->dphy_data_lane_reg = HS_PREPARE_OVERRIDE |
+						HS_PREPARE(prepare_cnt) |
+						HS_ZERO_OVERRIDE |
+						HS_ZERO(hs_zero_cnt) |
+						HS_TRAIL_OVERRIDE |
+						HS_TRAIL(trail_cnt) |
+						HS_EXIT_OVERRIDE |
+						HS_EXIT(exit_zero_cnt);
+	} else {
+		/*
+		 * DDR clock period = 2 * UI
+		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+		 * UI(nsec) = 10^6 / bitrate
+		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+		 * DDR clock count  = ns_value / DDR clock period
+		 */
 
-	if (prepare_cnt > PREPARE_CNT_MAX) {
-		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
-		prepare_cnt = PREPARE_CNT_MAX;
-	}
+		/* prepare count */
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);
 
-	/* exit zero count */
-	exit_zero_cnt = DIV_ROUND_UP(
+		if (prepare_cnt > PREPARE_CNT_MAX) {
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);
+			prepare_cnt = PREPARE_CNT_MAX;
+		}
+
+		/* exit zero count */
+		exit_zero_cnt = DIV_ROUND_UP(
 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
 				ui_num * mul
 				);
 
-	/*
-	 * Exit zero is unified val ths_zero and ths_exit
-	 * minimum value for ths_exit = 110ns
-	 * min (exit_zero_cnt * 2) = 110/UI
-	 * exit_zero_cnt = 55/UI
-	 */
-	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
-		exit_zero_cnt += 1;
-
-	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
-		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
-	}
+		/*
+		 * Exit zero is unified val ths_zero and ths_exit
+		 * minimum value for ths_exit = 110ns
+		 * min (exit_zero_cnt * 2) = 110/UI
+		 * exit_zero_cnt = 55/UI
+		 */
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)
+			exit_zero_cnt += 1;
+
+		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);
+			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
+		}
 
-	/* clk zero count */
-	clk_zero_cnt = DIV_ROUND_UP(
-				(tclk_prepare_clkzero -	ths_prepare_ns)
-				* ui_den, ui_num * mul);
+		/* clk zero count */
+		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
+						ths_prepare_ns)
+						* ui_den, ui_num * mul);
 
-	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
-		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
-		clk_zero_cnt = CLK_ZERO_CNT_MAX;
-	}
+		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);
+			clk_zero_cnt = CLK_ZERO_CNT_MAX;
+		}
 
-	/* trail count */
-	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
+		/* trail cnt */
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
 
-	if (trail_cnt > TRAIL_CNT_MAX) {
-		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
-		trail_cnt = TRAIL_CNT_MAX;
-	}
+		if (trail_cnt > TRAIL_CNT_MAX) {
+			DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
+			trail_cnt = TRAIL_CNT_MAX;
+		}
 
-	/* B080 */
-	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
+		/* B080 */
+		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 						clk_zero_cnt << 8 | prepare_cnt;
+	}
 
 	/*
 	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
@@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	 */
 	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 
-	/* B044 */
-	/* FIXME:
-	 * The comment above does not match with the code */
+	/*
+	 * B044
+	 * FIXME: comment above does not match with the code
+	 */
 	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
 						exit_zero_cnt * mul + 10, 8);
 
@@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 	intel_dsi->hs_to_lp_count += extra_byte_count;
 
-	/* B088 */
-	/* LP -> HS for clock lanes
+	/*
+	 * B088
+	 * LP -> HS for clock lanes
 	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 	 *						extra byte count
 	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
@@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 
 	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 
-	/* HS->LP for Clock Lanes
+	/*
+	 * HS->LP for Clock Lanes
 	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 	 *						Extra byte count
 	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
@@ -782,9 +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	DRM_DEBUG_KMS("BTA %s\n",
 			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 
-	/* delays in VBT are in unit of 100us, so need to convert
+	/*
+	 * delays in VBT are in unit of 100us, so need to convert
 	 * here in ms
-	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
+	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
+	 */
 	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
-- 
2.7.4

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Re: [PATCH v6 06/20] drm/i915/icl: Program DSI clock and data lane timing params

[Jani Nikula]

On Sun, 16 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch programs D-PHY timing parameters for the
> clock and data lane (in escape clocks) of DSI
> controller (DSI port 0 and 1).
> These programmed timings would be used by DSI Controller
> to calculate link transition latencies of the data and
> clock lanes.
>
> v2: Use newly defined bitfields for data and clock lane

Ville's review [1] hasn't been addressed.

BR,
Jani.

[1] http://mid.mail-archive.com/20180719161739.GC5565@intel.com

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++
>  drivers/gpu/drm/i915/intel_dsi.h     |   3 +
>  drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +++++++++++++++++++++++++----------
>  3 files changed, 165 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index ff5b285..9602b65 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>  		tmp |= intel_dsi->init_count;
>  		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
>  	}
> +
> +	/* Program DPHY clock lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
> +	}
> +
> +	/* Program DPHY data lanes timings */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +
> +		/* shadow register inside display core */
> +		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> +			   intel_dsi->dphy_data_lane_reg);
> +	}
>  }
>  
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index ad7c1cb..9fd8526 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -85,6 +85,9 @@ struct intel_dsi {
>  	u32 port_bits;
>  	u32 bw_timer;
>  	u32 dphy_reg;
> +
> +	/* data lanes dphy timing */
> +	u32 dphy_data_lane_reg;
>  	u32 video_frmt_cfg_bits;
>  	u16 lp_byte_clk;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index ac83d6b..fbb159b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	u32 bpp;
>  	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
>  	u32 ui_num, ui_den;
> -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
> +	u32 tclk_pre_cnt, tclk_post_cnt;
> +	u32 tclk_pre_ns, tclk_post_ns;
>  	u32 ths_prepare_ns, tclk_trail_ns;
>  	u32 tclk_prepare_clkzero, ths_prepare_hszero;
>  	u32 lp_to_hs_switch, hs_to_lp_switch;
> @@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
>  	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
> -
> +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> +	ths_prepare_ns = max(mipi_config->ths_prepare,
> +				mipi_config->tclk_prepare);
>  	/*
>  	 * B060
>  	 * LP byte clock = TLPX/ (8UI)
>  	 */
>  	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>  
> -	/* DDR clock period = 2 * UI
> -	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> -	 * UI(nsec) = 10^6 / bitrate
> -	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> -	 * DDR clock count  = ns_value / DDR clock period
> -	 *
> +	/*
>  	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
>  	 * HS byte clock count for other platform in HS ddr clock count
>  	 */
>  	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> -	ths_prepare_ns = max(mipi_config->ths_prepare,
> -			     mipi_config->tclk_prepare);
>  
> -	/* prepare count */
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
> +	if (IS_ICELAKE(dev_priv)) {
> +		/*
> +		 * prepare cnt in escape clocks
> +		 * this field represents a hexadecimal value with a precision
> +		 * of 1.2 – i.e. the most significant bit is the integer
> +		 * and the least significant 2 bits are fraction bits.
> +		 * so, the field can represent a range of 0.25 to 1.75
> +		 */
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> +
> +		/* clk zero count in escape clocks */
> +		clk_zero_cnt = DIV_ROUND_UP(
> +					(tclk_prepare_clkzero - ths_prepare_ns),
> +					tlpx_ns);
> +
> +		/* trail cnt in escape clocks*/
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> +
> +		/* tclk pre/post count in escape clocks */
> +		tclk_post_ns = mipi_config->tclk_post;
> +		tclk_pre_ns = mipi_config->tclk_pre;
> +		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
> +		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
> +
> +		/* hs zero cnt in escape clocks */
> +		hs_zero_cnt = DIV_ROUND_UP(
> +					(ths_prepare_hszero - ths_prepare_ns),
> +					tlpx_ns);
> +
> +		/* hs exit zero cnt in escape clocks */
> +		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> +
> +		if (prepare_cnt > 0x7 ||
> +		    clk_zero_cnt > 0xF ||
> +		    tclk_pre_cnt > 0x3 ||
> +		    tclk_post_cnt > 0x7 ||
> +		    trail_cnt > 0x7 ||
> +		    hs_zero_cnt > 0xF ||
> +		    exit_zero_cnt > 0x7) {
> +			DRM_DEBUG_DRIVER("DPHY values crossing max limits,");
> +			DRM_DEBUG_DRIVER("restricting to max values\n");
> +		}
> +
> +		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
> +		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
> +		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
> +		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
> +		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
> +		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
> +		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
> +
> +		/* clock lane dphy timings */
> +		intel_dsi->dphy_reg |= (CLK_PREPARE_OVERRIDE |
> +					CLK_PREPARE(prepare_cnt) |
> +					CLK_ZERO_OVERRIDE |
> +					CLK_ZERO(clk_zero_cnt) |
> +					CLK_PRE_OVERRIDE |
> +					CLK_PRE(tclk_pre_cnt) |
> +					CLK_POST_OVERRIDE |
> +					CLK_POST(tclk_post_cnt) |
> +					CLK_TRAIL_OVERRIDE |
> +					CLK_TRAIL(trail_cnt));
> +
> +		/* data lanes dphy timings */
> +		intel_dsi->dphy_data_lane_reg = HS_PREPARE_OVERRIDE |
> +						HS_PREPARE(prepare_cnt) |
> +						HS_ZERO_OVERRIDE |
> +						HS_ZERO(hs_zero_cnt) |
> +						HS_TRAIL_OVERRIDE |
> +						HS_TRAIL(trail_cnt) |
> +						HS_EXIT_OVERRIDE |
> +						HS_EXIT(exit_zero_cnt);
> +	} else {
> +		/*
> +		 * DDR clock period = 2 * UI
> +		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> +		 * UI(nsec) = 10^6 / bitrate
> +		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> +		 * DDR clock count  = ns_value / DDR clock period
> +		 */
>  
> -	if (prepare_cnt > PREPARE_CNT_MAX) {
> -		DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
> -		prepare_cnt = PREPARE_CNT_MAX;
> -	}
> +		/* prepare count */
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> +							ui_num * mul);
>  
> -	/* exit zero count */
> -	exit_zero_cnt = DIV_ROUND_UP(
> +		if (prepare_cnt > PREPARE_CNT_MAX) {
> +			DRM_DEBUG_KMS("prepare count too high %u\n",
> +								prepare_cnt);
> +			prepare_cnt = PREPARE_CNT_MAX;
> +		}
> +
> +		/* exit zero count */
> +		exit_zero_cnt = DIV_ROUND_UP(
>  				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>  				ui_num * mul
>  				);
>  
> -	/*
> -	 * Exit zero is unified val ths_zero and ths_exit
> -	 * minimum value for ths_exit = 110ns
> -	 * min (exit_zero_cnt * 2) = 110/UI
> -	 * exit_zero_cnt = 55/UI
> -	 */
> -	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
> -		exit_zero_cnt += 1;
> -
> -	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
> -		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> -	}
> +		/*
> +		 * Exit zero is unified val ths_zero and ths_exit
> +		 * minimum value for ths_exit = 110ns
> +		 * min (exit_zero_cnt * 2) = 110/UI
> +		 * exit_zero_cnt = 55/UI
> +		 */
> +		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
> +					(55 * ui_den) % ui_num)
> +			exit_zero_cnt += 1;
> +
> +		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> +			DRM_DEBUG_KMS("exit zero count too high %u\n",
> +								exit_zero_cnt);
> +			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> +		}
>  
> -	/* clk zero count */
> -	clk_zero_cnt = DIV_ROUND_UP(
> -				(tclk_prepare_clkzero -	ths_prepare_ns)
> -				* ui_den, ui_num * mul);
> +		/* clk zero count */
> +		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
> +						ths_prepare_ns)
> +						* ui_den, ui_num * mul);
>  
> -	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> -		DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
> -		clk_zero_cnt = CLK_ZERO_CNT_MAX;
> -	}
> +		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> +			DRM_DEBUG_KMS("clock zero count too high %u\n",
> +								clk_zero_cnt);
> +			clk_zero_cnt = CLK_ZERO_CNT_MAX;
> +		}
>  
> -	/* trail count */
> -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
> +		/* trail cnt */
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
>  
> -	if (trail_cnt > TRAIL_CNT_MAX) {
> -		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> -		trail_cnt = TRAIL_CNT_MAX;
> -	}
> +		if (trail_cnt > TRAIL_CNT_MAX) {
> +			DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> +			trail_cnt = TRAIL_CNT_MAX;
> +		}
>  
> -	/* B080 */
> -	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> +		/* B080 */
> +		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
>  						clk_zero_cnt << 8 | prepare_cnt;
> +	}
>  
>  	/*
>  	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
> @@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	 */
>  	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
>  
> -	/* B044 */
> -	/* FIXME:
> -	 * The comment above does not match with the code */
> +	/*
> +	 * B044
> +	 * FIXME: comment above does not match with the code
> +	 */
>  	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
>  						exit_zero_cnt * mul + 10, 8);
>  
> @@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
>  	intel_dsi->hs_to_lp_count += extra_byte_count;
>  
> -	/* B088 */
> -	/* LP -> HS for clock lanes
> +	/*
> +	 * B088
> +	 * LP -> HS for clock lanes
>  	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
>  	 *						extra byte count
>  	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
> @@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  
>  	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
>  
> -	/* HS->LP for Clock Lanes
> +	/*
> +	 * HS->LP for Clock Lanes
>  	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
>  	 *						Extra byte count
>  	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
> @@ -782,9 +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	DRM_DEBUG_KMS("BTA %s\n",
>  			enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
>  
> -	/* delays in VBT are in unit of 100us, so need to convert
> +	/*
> +	 * delays in VBT are in unit of 100us, so need to convert
>  	 * here in ms
> -	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
> +	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
> +	 */
>  	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
>  	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
>  	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [PATCH v6 06/20] drm/i915/icl: Program DSI clock and data lane timing params

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, September 26, 2018 6:29 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Kulkarni, Vandita <vandita.kulkarni@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; Rangappa, Komala B
> <komala.b.rangappa@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: Re: [PATCH v6 06/20] drm/i915/icl: Program DSI clock and data lane
> timing params
> 
> On Sun, 16 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > This patch programs D-PHY timing parameters for the clock and data
> > lane (in escape clocks) of DSI controller (DSI port 0 and 1).
> > These programmed timings would be used by DSI Controller to calculate
> > link transition latencies of the data and clock lanes.
> >
> > v2: Use newly defined bitfields for data and clock lane
> 
> Ville's review [1] hasn't been addressed.

Oh..Overlooked the comments. My bad.
Will address them while publishing v7.

Regards,
Madhav

> 
> BR,
> Jani.
> 
> [1] http://mid.mail-archive.com/20180719161739.GC5565@intel.com
> 
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/icl_dsi.c       |  18 ++++
> >  drivers/gpu/drm/i915/intel_dsi.h     |   3 +
> >  drivers/gpu/drm/i915/intel_dsi_vbt.c | 200
> > +++++++++++++++++++++++++----------
> >  3 files changed, 165 insertions(+), 56 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index ff5b285..9602b65 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -291,6 +291,24 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> >  		tmp |= intel_dsi->init_count;
> >  		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
> >  	}
> > +
> > +	/* Program DPHY clock lanes timings */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi-
> >dphy_reg);
> > +
> > +		/* shadow register inside display core */
> > +		I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi-
> >dphy_reg);
> > +	}
> > +
> > +	/* Program DPHY data lanes timings */
> > +	for_each_dsi_port(port, intel_dsi->ports) {
> > +		I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
> > +			   intel_dsi->dphy_data_lane_reg);
> > +
> > +		/* shadow register inside display core */
> > +		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
> > +			   intel_dsi->dphy_data_lane_reg);
> > +	}
> >  }
> >
> >  static void gen11_dsi_enable_port_and_phy(struct intel_encoder
> > *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> > b/drivers/gpu/drm/i915/intel_dsi.h
> > index ad7c1cb..9fd8526 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.h
> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
> > @@ -85,6 +85,9 @@ struct intel_dsi {
> >  	u32 port_bits;
> >  	u32 bw_timer;
> >  	u32 dphy_reg;
> > +
> > +	/* data lanes dphy timing */
> > +	u32 dphy_data_lane_reg;
> >  	u32 video_frmt_cfg_bits;
> >  	u16 lp_byte_clk;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > index ac83d6b..fbb159b 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> > @@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
> u16 panel_id)
> >  	u32 bpp;
> >  	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
> >  	u32 ui_num, ui_den;
> > -	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
> > +	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
> > +	u32 tclk_pre_cnt, tclk_post_cnt;
> > +	u32 tclk_pre_ns, tclk_post_ns;
> >  	u32 ths_prepare_ns, tclk_trail_ns;
> >  	u32 tclk_prepare_clkzero, ths_prepare_hszero;
> >  	u32 lp_to_hs_switch, hs_to_lp_switch; @@ -624,76 +626,157 @@
> bool
> > intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
> >
> >  	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
> >  	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
> > -
> > +	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> > +	ths_prepare_ns = max(mipi_config->ths_prepare,
> > +				mipi_config->tclk_prepare);
> >  	/*
> >  	 * B060
> >  	 * LP byte clock = TLPX/ (8UI)
> >  	 */
> >  	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 *
> ui_num);
> >
> > -	/* DDR clock period = 2 * UI
> > -	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> > -	 * UI(nsec) = 10^6 / bitrate
> > -	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> > -	 * DDR clock count  = ns_value / DDR clock period
> > -	 *
> > +	/*
> >  	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
> >  	 * HS byte clock count for other platform in HS ddr clock count
> >  	 */
> >  	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> > -	ths_prepare_ns = max(mipi_config->ths_prepare,
> > -			     mipi_config->tclk_prepare);
> >
> > -	/* prepare count */
> > -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num *
> mul);
> > +	if (IS_ICELAKE(dev_priv)) {
> > +		/*
> > +		 * prepare cnt in escape clocks
> > +		 * this field represents a hexadecimal value with a precision
> > +		 * of 1.2 – i.e. the most significant bit is the integer
> > +		 * and the least significant 2 bits are fraction bits.
> > +		 * so, the field can represent a range of 0.25 to 1.75
> > +		 */
> > +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> > +
> > +		/* clk zero count in escape clocks */
> > +		clk_zero_cnt = DIV_ROUND_UP(
> > +					(tclk_prepare_clkzero -
> ths_prepare_ns),
> > +					tlpx_ns);
> > +
> > +		/* trail cnt in escape clocks*/
> > +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> > +
> > +		/* tclk pre/post count in escape clocks */
> > +		tclk_post_ns = mipi_config->tclk_post;
> > +		tclk_pre_ns = mipi_config->tclk_pre;
> > +		tclk_pre_cnt = DIV_ROUND_UP(tclk_pre_ns, tlpx_ns);
> > +		tclk_post_cnt = DIV_ROUND_UP(tclk_post_ns, tlpx_ns);
> > +
> > +		/* hs zero cnt in escape clocks */
> > +		hs_zero_cnt = DIV_ROUND_UP(
> > +					(ths_prepare_hszero -
> ths_prepare_ns),
> > +					tlpx_ns);
> > +
> > +		/* hs exit zero cnt in escape clocks */
> > +		exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit,
> tlpx_ns);
> > +
> > +		if (prepare_cnt > 0x7 ||
> > +		    clk_zero_cnt > 0xF ||
> > +		    tclk_pre_cnt > 0x3 ||
> > +		    tclk_post_cnt > 0x7 ||
> > +		    trail_cnt > 0x7 ||
> > +		    hs_zero_cnt > 0xF ||
> > +		    exit_zero_cnt > 0x7) {
> > +			DRM_DEBUG_DRIVER("DPHY values crossing max
> limits,");
> > +			DRM_DEBUG_DRIVER("restricting to max values\n");
> > +		}
> > +
> > +		prepare_cnt = (prepare_cnt > 0x7) ? 0x7 : prepare_cnt;
> > +		clk_zero_cnt = (clk_zero_cnt > 0xF) ? 0xF : clk_zero_cnt;
> > +		tclk_pre_cnt = (tclk_pre_cnt > 0x3) ? 0x3 : tclk_pre_cnt;
> > +		tclk_post_cnt = (tclk_post_cnt > 0x7) ? 0x7 : tclk_post_cnt;
> > +		trail_cnt = (trail_cnt > 0x7) ? 0x7 : trail_cnt;
> > +		hs_zero_cnt = (hs_zero_cnt > 0xF) ? 0xF : hs_zero_cnt;
> > +		exit_zero_cnt = (exit_zero_cnt > 0x7) ? 0x7 : exit_zero_cnt;
> > +
> > +		/* clock lane dphy timings */
> > +		intel_dsi->dphy_reg |= (CLK_PREPARE_OVERRIDE |
> > +					CLK_PREPARE(prepare_cnt) |
> > +					CLK_ZERO_OVERRIDE |
> > +					CLK_ZERO(clk_zero_cnt) |
> > +					CLK_PRE_OVERRIDE |
> > +					CLK_PRE(tclk_pre_cnt) |
> > +					CLK_POST_OVERRIDE |
> > +					CLK_POST(tclk_post_cnt) |
> > +					CLK_TRAIL_OVERRIDE |
> > +					CLK_TRAIL(trail_cnt));
> > +
> > +		/* data lanes dphy timings */
> > +		intel_dsi->dphy_data_lane_reg = HS_PREPARE_OVERRIDE |
> > +						HS_PREPARE(prepare_cnt) |
> > +						HS_ZERO_OVERRIDE |
> > +						HS_ZERO(hs_zero_cnt) |
> > +						HS_TRAIL_OVERRIDE |
> > +						HS_TRAIL(trail_cnt) |
> > +						HS_EXIT_OVERRIDE |
> > +						HS_EXIT(exit_zero_cnt);
> > +	} else {
> > +		/*
> > +		 * DDR clock period = 2 * UI
> > +		 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> > +		 * UI(nsec) = 10^6 / bitrate
> > +		 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> > +		 * DDR clock count  = ns_value / DDR clock period
> > +		 */
> >
> > -	if (prepare_cnt > PREPARE_CNT_MAX) {
> > -		DRM_DEBUG_KMS("prepare count too high %u\n",
> prepare_cnt);
> > -		prepare_cnt = PREPARE_CNT_MAX;
> > -	}
> > +		/* prepare count */
> > +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> > +							ui_num * mul);
> >
> > -	/* exit zero count */
> > -	exit_zero_cnt = DIV_ROUND_UP(
> > +		if (prepare_cnt > PREPARE_CNT_MAX) {
> > +			DRM_DEBUG_KMS("prepare count too high %u\n",
> > +								prepare_cnt);
> > +			prepare_cnt = PREPARE_CNT_MAX;
> > +		}
> > +
> > +		/* exit zero count */
> > +		exit_zero_cnt = DIV_ROUND_UP(
> >  				(ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> >  				ui_num * mul
> >  				);
> >
> > -	/*
> > -	 * Exit zero is unified val ths_zero and ths_exit
> > -	 * minimum value for ths_exit = 110ns
> > -	 * min (exit_zero_cnt * 2) = 110/UI
> > -	 * exit_zero_cnt = 55/UI
> > -	 */
> > -	if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) %
> ui_num)
> > -		exit_zero_cnt += 1;
> > -
> > -	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> > -		DRM_DEBUG_KMS("exit zero count too high %u\n",
> exit_zero_cnt);
> > -		exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> > -	}
> > +		/*
> > +		 * Exit zero is unified val ths_zero and ths_exit
> > +		 * minimum value for ths_exit = 110ns
> > +		 * min (exit_zero_cnt * 2) = 110/UI
> > +		 * exit_zero_cnt = 55/UI
> > +		 */
> > +		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
> > +					(55 * ui_den) % ui_num)
> > +			exit_zero_cnt += 1;
> > +
> > +		if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
> > +			DRM_DEBUG_KMS("exit zero count too high %u\n",
> > +
> 	exit_zero_cnt);
> > +			exit_zero_cnt = EXIT_ZERO_CNT_MAX;
> > +		}
> >
> > -	/* clk zero count */
> > -	clk_zero_cnt = DIV_ROUND_UP(
> > -				(tclk_prepare_clkzero -	ths_prepare_ns)
> > -				* ui_den, ui_num * mul);
> > +		/* clk zero count */
> > +		clk_zero_cnt = DIV_ROUND_UP((tclk_prepare_clkzero -
> > +						ths_prepare_ns)
> > +						* ui_den, ui_num * mul);
> >
> > -	if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> > -		DRM_DEBUG_KMS("clock zero count too high %u\n",
> clk_zero_cnt);
> > -		clk_zero_cnt = CLK_ZERO_CNT_MAX;
> > -	}
> > +		if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
> > +			DRM_DEBUG_KMS("clock zero count too high %u\n",
> > +								clk_zero_cnt);
> > +			clk_zero_cnt = CLK_ZERO_CNT_MAX;
> > +		}
> >
> > -	/* trail count */
> > -	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> > -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
> > +		/* trail cnt */
> > +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num *
> mul);
> >
> > -	if (trail_cnt > TRAIL_CNT_MAX) {
> > -		DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
> > -		trail_cnt = TRAIL_CNT_MAX;
> > -	}
> > +		if (trail_cnt > TRAIL_CNT_MAX) {
> > +			DRM_DEBUG_KMS("trail count too high %u\n",
> trail_cnt);
> > +			trail_cnt = TRAIL_CNT_MAX;
> > +		}
> >
> > -	/* B080 */
> > -	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> > +		/* B080 */
> > +		intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
> >  						clk_zero_cnt << 8 |
> prepare_cnt;
> > +	}
> >
> >  	/*
> >  	 * LP to HS switch count = 4TLPX + PREP_COUNT * mul +
> > EXIT_ZERO_COUNT * @@ -707,9 +790,10 @@ bool intel_dsi_vbt_init(struct
> intel_dsi *intel_dsi, u16 panel_id)
> >  	 */
> >  	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
> >
> > -	/* B044 */
> > -	/* FIXME:
> > -	 * The comment above does not match with the code */
> > +	/*
> > +	 * B044
> > +	 * FIXME: comment above does not match with the code
> > +	 */
> >  	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
> >  						exit_zero_cnt * mul + 10, 8);
> >
> > @@ -718,8 +802,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
> u16 panel_id)
> >  	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
> >  	intel_dsi->hs_to_lp_count += extra_byte_count;
> >
> > -	/* B088 */
> > -	/* LP -> HS for clock lanes
> > +	/*
> > +	 * B088
> > +	 * LP -> HS for clock lanes
> >  	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
> >  	 *						extra byte count
> >  	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
> > @@ -735,7 +820,8 @@ bool intel_dsi_vbt_init(struct intel_dsi
> > *intel_dsi, u16 panel_id)
> >
> >  	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
> >
> > -	/* HS->LP for Clock Lanes
> > +	/*
> > +	 * HS->LP for Clock Lanes
> >  	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
> >  	 *						Extra byte count
> >  	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count @@ -782,9
> > +868,11 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
> panel_id)
> >  	DRM_DEBUG_KMS("BTA %s\n",
> >  			enableddisabled(!(intel_dsi->video_frmt_cfg_bits &
> > DISABLE_VIDEO_BTA)));
> >
> > -	/* delays in VBT are in unit of 100us, so need to convert
> > +	/*
> > +	 * delays in VBT are in unit of 100us, so need to convert
> >  	 * here in ms
> > -	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
> > +	 * Delay (100us) * 100 /1000 = Delay / 10 (ms)
> > +	 */
> >  	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
> >  	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
> >  	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
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[PATCH v6 07/20] drm/i915/icl: Define TA_TIMING_PARAM registers

[Madhav Chauhan]

This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.

v2: Changes (Jani N)
    - Define mask/shift for bitfields
    - Use bitfields name as per BSPEC
    - Define remaining bitfields

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c8999d..b27d0c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10343,6 +10343,29 @@ enum skl_power_gate {
 #define  HS_EXIT_MASK			(0x7 << 0)
 #define  HS_EXIT_SHIFT			0
 
+#define _DPHY_TA_TIMING_PARAM_0		0x162188
+#define _DPHY_TA_TIMING_PARAM_1		0x6c188
+#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_TA_TIMING_PARAM_0,\
+						   _DPHY_TA_TIMING_PARAM_1)
+#define _DSI_TA_TIMING_PARAM_0		0x6b098
+#define _DSI_TA_TIMING_PARAM_1		0x6b898
+#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_TA_TIMING_PARAM_0,\
+						   _DSI_TA_TIMING_PARAM_1)
+#define  TA_SURE_OVERRIDE		(1 << 31)
+#define  TA_SURE(x)			((x) << 16)
+#define  TA_SURE_MASK			(0x1f << 16)
+#define  TA_SURE_SHIFT			16
+#define  TA_GO_OVERRIDE		(1 << 15)
+#define  TA_GO(x)			((x) << 8)
+#define  TA_GO_MASK			(0xf << 8)
+#define  TA_GO_SHIFT			8
+#define  TA_GET_OVERRIDE		(1 << 7)
+#define  TA_GET(x)			((x) << 0)
+#define  TA_GET_MASK			(0xf << 0)
+#define  TA_GET_SHIFT			0
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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Re: [PATCH v6 07/20] drm/i915/icl: Define TA_TIMING_PARAM registers

[Jani Nikula]

On Sun, 16 Sep 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch defines DSI_TA_TIMING_PARAM and
> DPHY_TA_TIMING_PARAM registers used in
> dphy programming.
>
> v2: Changes (Jani N)
>     - Define mask/shift for bitfields
>     - Use bitfields name as per BSPEC
>     - Define remaining bitfields
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

I've pushed patches 1-5 and 7 to dinq. Thanks for the patches.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6c8999d..b27d0c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10343,6 +10343,29 @@ enum skl_power_gate {
>  #define  HS_EXIT_MASK			(0x7 << 0)
>  #define  HS_EXIT_SHIFT			0
>  
> +#define _DPHY_TA_TIMING_PARAM_0		0x162188
> +#define _DPHY_TA_TIMING_PARAM_1		0x6c188
> +#define DPHY_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DPHY_TA_TIMING_PARAM_0,\
> +						   _DPHY_TA_TIMING_PARAM_1)
> +#define _DSI_TA_TIMING_PARAM_0		0x6b098
> +#define _DSI_TA_TIMING_PARAM_1		0x6b898
> +#define DSI_TA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
> +						   _DSI_TA_TIMING_PARAM_0,\
> +						   _DSI_TA_TIMING_PARAM_1)
> +#define  TA_SURE_OVERRIDE		(1 << 31)
> +#define  TA_SURE(x)			((x) << 16)
> +#define  TA_SURE_MASK			(0x1f << 16)
> +#define  TA_SURE_SHIFT			16
> +#define  TA_GO_OVERRIDE		(1 << 15)
> +#define  TA_GO(x)			((x) << 8)
> +#define  TA_GO_MASK			(0xf << 8)
> +#define  TA_GO_SHIFT			8
> +#define  TA_GET_OVERRIDE		(1 << 7)
> +#define  TA_GET(x)			((x) << 0)
> +#define  TA_GET_MASK			(0xf << 0)
> +#define  TA_GET_SHIFT			0
> +
>  /* bits 31:0 */
>  #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
>  #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)

-- 
Jani Nikula, Intel Open Source Graphics Center
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[PATCH v6 08/20] drm/i915/icl: Program TA_TIMING_PARAM registers

[Madhav Chauhan]

This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).

v2: Changes
    - Don't use KHz() macro (Ville/Jani N)
    - Use newly defined bitfields

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h     |  1 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9602b65..0fb7b6f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -309,6 +309,27 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 		I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 			   intel_dsi->dphy_data_lane_reg);
 	}
+
+	/*
+	 * If DSI link operating at or below an 800 MHz,
+	 * TA_SURE should be override and programmed to
+	 * a value '0' inside TA_PARAM_REGISTERS otherwise
+	 * leave all fields at HW default values.
+	 */
+	if (intel_dsi->bitrate_khz <= 800000) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE(0));
+			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+			/* shadow register inside display core */
+			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+			tmp &= ~TA_SURE_MASK;
+			tmp |= (TA_SURE_OVERRIDE | TA_SURE(0));
+			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+		}
+	}
 }
 
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 9fd8526..25e7396 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -101,6 +101,7 @@ struct intel_dsi {
 
 	u16 init_count;
 	u32 pclk;
+	u32 bitrate_khz;
 	u16 burst_mode_ratio;
 
 	/* all delays in ms */
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index fbb159b..11f184f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->pclk = pclk;
 
 	bitrate = (pclk * bpp) / intel_dsi->lane_count;
+	intel_dsi->bitrate_khz = bitrate;
 
 	switch (intel_dsi->escape_clk_div) {
 	case 0:
-- 
2.7.4

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[PATCH v6 09/20] drm/i915/icl: Get DSI transcoder for a given port

[Madhav Chauhan]

This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 9 +++++++++
 drivers/gpu/drm/i915/intel_display.h | 6 ++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0fb7b6f..30684f0 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,15 @@
 
 #include "intel_dsi.h"
 
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
+								enum port port)
+{
+	if (port == PORT_A)
+		return TRANSCODER_DSI_0;
+	else
+		return TRANSCODER_DSI_1;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index ed474da..dc9603e 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -61,8 +61,10 @@ enum transcoder {
 	TRANSCODER_B,
 	TRANSCODER_C,
 	TRANSCODER_EDP,
-	TRANSCODER_DSI_A,
-	TRANSCODER_DSI_C,
+	TRANSCODER_DSI_0,
+	TRANSCODER_DSI_1,
+	TRANSCODER_DSI_A = TRANSCODER_DSI_0,	/* legacy DSI */
+	TRANSCODER_DSI_C = TRANSCODER_DSI_1,	/* legacy DSI */
 
 	I915_MAX_TRANSCODERS
 };
-- 
2.7.4

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[PATCH v6 10/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers

[Madhav Chauhan]

This patch adds _MMIO_DSI macros for accessing DSI
transcoder registers.

v2: Use _MMIO_TRANS() (Ville)

Credits-to: Jani N

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b27d0c1..58b82b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9786,6 +9786,10 @@ enum skl_power_gate {
 #define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+/* Gen11 DSI */
+#define _MMIO_DSI(tc, dsi0, dsi1)	_MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
+						    dsi0, dsi1)
+
 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
-- 
2.7.4

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[PATCH v6 11/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register

[Madhav Chauhan]

This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.

v2: Changes (Jani N)
    - Define _SHIFT and _MASK for bitfields
    - Define values for fields already shifted in place

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 48 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58b82b2..41ef285 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10370,6 +10370,54 @@ enum skl_power_gate {
 #define  TA_GET_MASK			(0xf << 0)
 #define  TA_GET_SHIFT			0
 
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0		0x6b030
+#define _DSI_TRANS_FUNC_CONF_1		0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)		_MMIO_DSI(tc,	\
+						  _DSI_TRANS_FUNC_CONF_0,\
+						  _DSI_TRANS_FUNC_CONF_1)
+#define  OP_MODE_MASK			(0x3 << 28)
+#define  OP_MODE_SHIFT			28
+#define  CMD_MODE_NO_GATE		(0x0 << 28)
+#define  CMD_MODE_TE_GATE		(0x1 << 28)
+#define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
+#define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
+#define  LINK_READY			(1 << 20)
+#define  PIX_FMT_MASK			(0x3 << 16)
+#define  PIX_FMT_SHIFT			16
+#define  PIX_FMT_RGB565		(0x0 << 16)
+#define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
+#define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
+#define  PIX_FMT_RGB888		(0x3 << 16)
+#define  PIX_FMT_RGB101010		(0x4 << 16)
+#define  PIX_FMT_RGB121212		(0x5 << 16)
+#define  PIX_FMT_COMPRESSED		(0x6 << 16)
+#define  BGR_TRANSMISSION		(1 << 15)
+#define  PIX_VIRT_CHAN(x)		(x << 12)
+#define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
+#define  PIX_VIRT_CHAN_SHIFT		12
+#define  PIX_BUF_THRESHOLD_MASK	(0x3 << 10)
+#define  PIX_BUF_THRESHOLD_SHIFT	10
+#define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
+#define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
+#define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
+#define  PIX_BUF_THRESHOLD_FULL	(0x3 << 10)
+#define  CONTINUOUS_CLK_MASK		(0x3 << 8)
+#define  CONTINUOUS_CLK_SHIFT		(0x3 << 8)
+#define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
+#define  CLK_HS_OR_LP			(0x2 << 8)
+#define  CLK_HS_CONTINUOUS		(0x3 << 8)
+#define  LINK_CALIBRATION_MASK		(0x3 << 4)
+#define  LINK_CALIBRATION_SHIFT		(0x3 << 4)
+#define  CALIBRATION_DISABLED		(0x0 << 4)
+#define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
+#define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
+#define  S3D_ORIENTATION_MASK		(0x1 << 1)
+#define  S3D_ORIENTATION_SHIFT		1
+#define  S3D_ORIENTATION_PORTRAIT	(0x0 << 1)
+#define  S3D_ORIENTATION_LANDSCAPE	(0x1 << 1)
+#define  EOTP_DISABLED			(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v6 12/20] drm/i915/icl: Configure DSI transcoders

[Madhav Chauhan]

This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.

v2: Rebase
v3: Use newly defined bitfields.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 86 +++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dsi.h     |  3 ++
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  1 +
 3 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 30684f0..03534c6 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,8 +27,7 @@
 
 #include "intel_dsi.h"
 
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
-								enum port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
 {
 	if (port == PORT_A)
 		return TRANSCODER_DSI_0;
@@ -341,6 +340,86 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+		if (intel_dsi->eotp_pkt == 0)
+			tmp |= EOTP_DISABLED;
+		else
+			tmp &= ~EOTP_DISABLED;
+
+		/* enable link calibration if freq > 1.5Gbps */
+		if (intel_dsi->bitrate_khz >= (1500 * 1000)) {
+			tmp &= ~LINK_CALIBRATION_MASK;
+			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
+		}
+
+		/* configure continuous clock */
+		tmp &= ~CONTINUOUS_CLK_MASK;
+		if (intel_dsi->clock_stop)
+			tmp |= CLK_ENTER_LP_AFTER_DATA;
+		else
+			tmp |= CLK_HS_CONTINUOUS;
+
+		/* configure buffer threshold limit to minimum */
+		tmp &= ~PIX_BUF_THRESHOLD_MASK;
+		tmp |= PIX_BUF_THRESHOLD_1_4;
+
+		/* set virtual channel to '0' */
+		tmp &= ~PIX_VIRT_CHAN_MASK;
+		tmp |= PIX_VIRT_CHAN(0x0);
+
+		/* program BGR transmission */
+		if (intel_dsi->bgr_enabled)
+			tmp |= BGR_TRANSMISSION;
+
+		/* select pixel format */
+		tmp &= ~PIX_FMT_MASK;
+
+		switch (intel_dsi->pixel_format) {
+		case MIPI_DSI_FMT_RGB888:
+			tmp |= PIX_FMT_RGB888;
+			break;
+		case MIPI_DSI_FMT_RGB666:
+			tmp |= PIX_FMT_RGB666_LOOSE;
+			break;
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			tmp |= PIX_FMT_RGB666_PACKED;
+			break;
+		case MIPI_DSI_FMT_RGB565:
+			tmp |= PIX_FMT_RGB565;
+			break;
+		default:
+			DRM_ERROR("DSI pixel format unsupported\n");
+		}
+
+		/* program DSI operation mode */
+		if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+			tmp &= ~OP_MODE_MASK;
+			if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+				tmp |= VIDEO_MODE_SYNC_PULSE;
+			} else if (intel_dsi->video_mode_format ==
+					VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS) {
+				tmp |= VIDEO_MODE_SYNC_EVENT;
+			} else {
+				DRM_ERROR("DSI Video Mode unsupported\n");
+			}
+		}
+
+		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
@@ -357,6 +436,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 
 	/* setup D-PHY timings */
 	gen11_dsi_setup_dphy_timings(encoder);
+
+	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
+	gen11_dsi_configure_transcoder(encoder);
 }
 
 static void __attribute__((unused))
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 25e7396..e3225cd 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -81,6 +81,9 @@ struct intel_dsi {
 	u16 dcs_backlight_ports;
 	u16 dcs_cabc_ports;
 
+	/* RGB or BGR */
+	unsigned int bgr_enabled;
+
 	u8 pixel_overlap;
 	u32 port_bits;
 	u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 11f184f..f8d85b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -542,6 +542,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
 		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 
 	pclk = mode->clock;
 
-- 
2.7.4

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[PATCH v6 13/20] drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers

[Madhav Chauhan]

This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.

v2: Changes:
    - Remove redundant extra line
    - Correct some of bitfield definition

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c |  3 ++-
 drivers/gpu/drm/i915/i915_reg.h | 17 +++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9f..bd4e0fd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,7 +36,8 @@
 	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
 			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
-			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
+			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
+			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
 	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
 
 #define GEN_CHV_PIPEOFFSETS \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41ef285..a7e1fce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4066,6 +4066,8 @@ enum {
 #define TRANSCODER_C_OFFSET 0x62000
 #define CHV_TRANSCODER_C_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET	0x6b000
+#define TRANSCODER_DSI1_OFFSET	0x6b800
 
 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
 	dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
@@ -9014,6 +9016,8 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
 #define _TRANS_DDI_FUNC_CTL_C		0x62400
 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
+#define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
+#define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
 
 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
@@ -9051,6 +9055,19 @@ enum skl_power_gate {
 					| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
 					| TRANS_DDI_HDMI_SCRAMBLING)
 
+#define _TRANS_DDI_FUNC_CTL2_A		0x60404
+#define _TRANS_DDI_FUNC_CTL2_B		0x61404
+#define _TRANS_DDI_FUNC_CTL2_C		0x62404
+#define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
+#define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
+#define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
+#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
+						     _TRANS_DDI_FUNC_CTL2_A)
+#define  PORT_SYNC_MODE_ENABLE			(1 << 4)
+#define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) < 0)
+#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
+#define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
+
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A			0x64040
 #define _DP_TP_CTL_B			0x64140
-- 
2.7.4

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[PATCH v6 14/20] drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers

[Madhav Chauhan]

This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 61 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 57 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 03534c6..1d39975 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -340,10 +340,13 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	u32 tmp;
 	enum port port;
 	enum transcoder dsi_trans;
@@ -418,9 +421,59 @@ static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
 
 		I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 	}
+
+	/* enable port sync mode if dual link */
+	if (intel_dsi->dual_link) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
+			tmp |= PORT_SYNC_MODE_ENABLE;
+			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
+		}
+
+		//TODO: configure DSS_CTL1
+	}
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		/*select dala lane width */
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+		tmp &= ~DDI_PORT_WIDTH_MASK;
+		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
+		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
+
+		/* select input pipe */
+		switch (pipe) {
+		case PIPE_A:
+			tmp |= TRANS_DDI_EDP_INPUT_A_ON;
+			break;
+		case PIPE_B:
+			tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
+			break;
+		case PIPE_C:
+			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
+			break;
+		default:
+			DRM_ERROR("invalid pipe select\n");
+			break;
+		}
+
+		/* enable DDI buffer */
+		tmp |= TRANS_DDI_FUNC_ENABLE;
+		I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+	}
+
+	/* wait for link ready */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
+				LINK_READY), 2500))
+			DRM_ERROR("DSI link not ready\n");
+	}
 }
 
-static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)
 {
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
@@ -438,7 +491,7 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
 	gen11_dsi_setup_dphy_timings(encoder);
 
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
-	gen11_dsi_configure_transcoder(encoder);
+	gen11_dsi_configure_transcoder(encoder, pipe_config);
 }
 
 static void __attribute__((unused))
@@ -453,5 +506,5 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	gen11_dsi_program_esc_clk_div(encoder);
 
 	/* step4: enable DSI port and DPHY */
-	gen11_dsi_enable_port_and_phy(encoder);
+	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
 }
-- 
2.7.4

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[PATCH v6 15/20] drm/i915/icl: Define DSI transcoder timing registers

[Madhav Chauhan]

This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.

v2: Remove TRANS_TIMING_SHIFT definition

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a7e1fce..a87f0ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4061,6 +4061,18 @@ enum {
 #define _VSYNCSHIFT_B	0x61028
 #define _PIPE_MULT_B	0x6102c
 
+/* DSI trancoders (0 & 1) timing regs */
+#define _HTOTAL_DSI0		0x6b000
+#define _HTOTAL_DSI1		0x6b800
+#define _HSYNC_DSI0		0x6b008
+#define _HSYNC_DSI1		0x6b808
+#define _VTOTAL_DSI0		0x6b00c
+#define _VTOTAL_DSI1		0x6b80c
+#define _VSYNC_DSI0		0x6b014
+#define _VSYNC_DSI1		0x6b814
+#define _VSYNCSHIFT_DSI0	0x6b028
+#define _VSYNCSHIFT_DSI1	0x6b828
+
 #define TRANSCODER_A_OFFSET 0x60000
 #define TRANSCODER_B_OFFSET 0x61000
 #define TRANSCODER_C_OFFSET 0x62000
-- 
2.7.4

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[PATCH v6 16/20] drm/i915/icl: Configure DSI transcoder timings

[Madhav Chauhan]

As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.

v2: Remove TRANS_TIMING_SHIFT usage

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 128 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 1d39975..e7f6005 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -472,6 +472,130 @@ static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 	}
 }
 
+static void gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	const struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+	enum port port;
+	u32 tmp;
+	enum transcoder dsi_trans;
+	/* horizontal timings */
+	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
+	u16 hfront_porch, hback_porch;
+	/* vertical timings */
+	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+
+	hactive = adjusted_mode->crtc_hdisplay;
+	htotal = adjusted_mode->crtc_htotal;
+	hsync_start = adjusted_mode->crtc_hsync_start;
+	hsync_end = adjusted_mode->crtc_hsync_end;
+	hsync_size  = hsync_end - hsync_start;
+	hfront_porch = (adjusted_mode->crtc_hsync_start -
+			adjusted_mode->crtc_hdisplay);
+	hback_porch = (adjusted_mode->crtc_htotal -
+		       adjusted_mode->crtc_hsync_end);
+	vactive = adjusted_mode->crtc_vdisplay;
+	vtotal = adjusted_mode->crtc_vtotal;
+	vsync_start = adjusted_mode->crtc_vsync_start;
+	vsync_end = adjusted_mode->crtc_vsync_end;
+	vsync_shift = hsync_start - htotal/2;
+
+	if (intel_dsi->dual_link) {
+		hactive /= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			hactive += intel_dsi->pixel_overlap;
+		htotal /= 2;
+	}
+
+	/* minimum hactive as per bspec: 256 pixels */
+	if (adjusted_mode->crtc_hdisplay < 256)
+		DRM_ERROR("hactive is less then 256 pixels\n");
+
+	/* if RGB666 format, then hactive must be multiple of 4 pixels */
+	if ((intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666) &&
+	    ((hactive % 4) != 0))
+		DRM_ERROR("hactive pixels are not multiple of 4\n");
+
+	/* program TRANS_HTOTAL register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		/* BSPEC: program required pixels minus 1 */
+		tmp = (hactive - 1);
+		tmp |= ((htotal - 1) << 16);
+		I915_WRITE(HTOTAL(dsi_trans), tmp);
+	}
+
+	/* TRANS_HSYNC register to be programmed only for video mode */
+	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+		if (intel_dsi->video_mode_format ==
+		    VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+			/* BSPEC: hsync size should be atleast 16 pixels */
+			if (hsync_size < 16)
+				DRM_ERROR("hsync size < 16 pixels\n");
+		}
+
+		if (hback_porch < 16)
+			DRM_ERROR("hback porch < 16 pixels\n");
+
+		if (intel_dsi->dual_link) {
+			hsync_start /= 2;
+			hsync_end /= 2;
+		}
+
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			/* BSPEC: program required pixels minus 1 */
+			tmp = (hsync_start - 1);
+			tmp |= ((hsync_end - 1) << 16);
+			I915_WRITE(HSYNC(dsi_trans), tmp);
+		}
+	}
+
+	/* program TRANS_VTOTAL register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		/*
+		 * FIXME: Programing this by assuming progressive mode, since
+		 * non-interlaced info from VBT is not saved inside
+		 * struct drm_display_mode.
+		 * For interlace mode: program required pixel minus 2
+		 */
+		tmp = ((vtotal - 1) << 16);
+		/* BSPEC: program required pixels minus 1 */
+		tmp |= (vactive - 1);
+		I915_WRITE(VTOTAL(dsi_trans), tmp);
+	}
+
+	if (vsync_end < vsync_start || vsync_end > vtotal)
+		DRM_ERROR("Invalid vsync_end value\n");
+
+	if (vsync_start < vactive)
+		DRM_ERROR("vsync_start less than vactive\n");
+
+	/* program TRANS_VSYNC register */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		/* BSPEC: program required pixels minus 1 */
+		tmp = (vsync_start - 1);
+		tmp |= ((vsync_end - 1) << 16);
+		I915_WRITE(VSYNC(dsi_trans), tmp);
+	}
+
+	/*
+	 * FIXME: It has to be programmed only for interlaced
+	 * modes. Put the check condition here once interlaced
+	 * info available as described above.
+	 * program TRANS_VSYNCSHIFT regsitser
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 				const struct intel_crtc_state *pipe_config)
 {
@@ -507,4 +631,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+
+	/* step6c: configure transcoder timings */
+	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
+
 }
-- 
2.7.4

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[PATCH v6 17/20] drm/i915/icl: Define TRANS_CONF register for DSI

[Madhav Chauhan]

This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.

v2: Add blank line before comment

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bd4e0fd..f1af50b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -34,7 +34,8 @@
 
 #define GEN_DEFAULT_PIPEOFFSETS \
 	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
-			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
+			  PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
+			  PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET}, \
 	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
 			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
 			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a87f0ef..34a0afa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5543,6 +5543,10 @@ enum {
 #define   DSL_LINEMASK_GEN2	0x00000fff
 #define   DSL_LINEMASK_GEN3	0x00001fff
 #define _PIPEACONF		0x70008
+
+/* gen 11 DSI transcoder '0' and '1' */
+#define _PIPEDSI0CONF		0x7b008
+#define _PIPEDSI1CONF		0x7b808
 #define   PIPECONF_ENABLE	(1 << 31)
 #define   PIPECONF_DISABLE	0
 #define   PIPECONF_DOUBLE_WIDE	(1 << 30)
@@ -5650,6 +5654,10 @@ enum {
  */
 #define PIPE_EDP_OFFSET	0x7f000
 
+/* gen 11 DSI transcoder '0' and '1' */
+#define PIPE_DSI0_OFFSET	0x7b000
+#define PIPE_DSI1_OFFSET	0x7b800
+
 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
 	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
 	dev_priv->info.display_mmio_offset)
-- 
2.7.4

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[PATCH v6 18/20] drm/i915/icl: Enable DSI transcoders

[Madhav Chauhan]

This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index e7f6005..ae8877a 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -596,6 +596,28 @@ static void gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	}
 }
 
+static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	enum transcoder dsi_trans;
+	u32 tmp;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(PIPECONF(dsi_trans));
+		tmp |= PIPECONF_ENABLE;
+		I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+		/* wait for transcoder to be enabled */
+		if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+					    I965_PIPECONF_ACTIVE,
+					    I965_PIPECONF_ACTIVE, 10))
+			DRM_ERROR("DSI transcoder not enabled\n");
+	}
+}
+
 static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 				const struct intel_crtc_state *pipe_config)
 {
@@ -635,4 +657,6 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 
+	/* step6d: enable dsi transcoder */
+	gen11_dsi_enable_transcoder(encoder);
 }
-- 
2.7.4

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[PATCH v6 19/20] drm/i915/icl: Define DSI panel programming registers

[Madhav Chauhan]

This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
bitfields, masks and macros used for configuring DSI panel.

v2: Define remaining bitfields

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34a0afa..0b10d49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10455,6 +10455,44 @@ enum skl_power_gate {
 #define  S3D_ORIENTATION_LANDSCAPE	(0x1 << 1)
 #define  EOTP_DISABLED			(1 << 0)
 
+#define _DSI_CMD_RXCTL_0		0x6b0d4
+#define _DSI_CMD_RXCTL_1		0x6b8d4
+#define DSI_CMD_RXCTL(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_RXCTL_0,\
+						  _DSI_CMD_RXCTL_1)
+#define  READ_UNLOADS_DW		(1 << 16)
+#define  RECEIVED_UNASSIGNED_TRIGGER	(1 << 15)
+#define  RECEIVED_ACKNOWLEDGE_TRIGGER	(1 << 14)
+#define  RECEIVED_TEAR_EFFECT_TRIGGER	(1 << 13)
+#define  RECEIVED_RESET_TRIGGER		(1 << 12)
+#define  RECEIVED_PAYLOAD_WAS_LOST	(1 << 11)
+#define  RECEIVED_CRC_WAS_LOST		(1 << 10)
+#define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
+#define  NUMBER_RX_PLOAD_DW_SHIFT	0
+
+#define _DSI_CMD_TXCTL_0		0x6b0d0
+#define _DSI_CMD_TXCTL_1		0x6b8d0
+#define DSI_CMD_TXCTL(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_TXCTL_0,\
+						  _DSI_CMD_TXCTL_1)
+#define  KEEP_LINK_IN_HS		(1 << 24)
+#define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
+#define  FREE_HEADER_CREDIT_SHIFT	0x8
+#define  FREE_PLOAD_CREDIT_MASK	(0xff << 0)
+#define  FREE_PLOAD_CREDIT_SHIFT	0
+#define  MAX_HEADER_CREDIT		0x10
+#define  MAX_PLOAD_CREDIT		0x40
+
+#define _DSI_LP_MSG_0			0x6b0d8
+#define _DSI_LP_MSG_1			0x6b8d8
+#define DSI_LP_MSG(tc)			_MMIO_DSI(tc,	\
+						  _DSI_LP_MSG_0,\
+						  _DSI_LP_MSG_1)
+#define  LPTX_IN_PROGRESS		(1 << 17)
+#define  LINK_IN_ULPS			(1 << 16)
+#define  LINK_ULPS_TYPE_LP11		(1 << 8)
+#define  LINK_ENTER_ULPS		(1 << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4

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[PATCH v6 20/20] drm/i915/icl: Set max return packet size for DSI panel

[Madhav Chauhan]

This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.

v2: Rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ae8877a..a243349 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
  *   Jani Nikula <jani.nikula@intel.com>
  */
 
+#include <drm/drm_mipi_dsi.h>
 #include "intel_dsi.h"
 
 static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -640,6 +641,30 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_configure_transcoder(encoder, pipe_config);
 }
 
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct mipi_dsi_device *dsi;
+	enum port port;
+	enum transcoder dsi_trans;
+	u32 tmp;
+	int ret;
+
+	/* set maximum return packet size */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+		tmp &= NUMBER_RX_PLOAD_DW_MASK;
+		/* multiply "Number Rx Payload DW" by 4 to get max value */
+		tmp = tmp * 4;
+		dsi = intel_dsi->dsi_hosts[port]->device;
+		ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+		if (ret < 0)
+			DRM_ERROR("error setting max return pkt size%d\n", tmp);
+	}
+}
+
 static void __attribute__((unused))
 gen11_dsi_pre_enable(struct intel_encoder *encoder,
 		     const struct intel_crtc_state *pipe_config,
@@ -654,6 +679,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
 
+	/* step5: program and powerup panel */
+	gen11_dsi_powerup_panel(encoder);
+
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
33aac050cb0a drm/i915/icl: Configure lane sequencing of combo phy transmitter
-:59: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#59: FILE: drivers/gpu/drm/i915/icl_dsi.c:142:
+
+}

total: 0 errors, 0 warnings, 1 checks, 49 lines checked
ef7b1857842d drm/i915/icl: DSI vswing programming sequence
-:35: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#35: FILE: drivers/gpu/drm/i915/icl_dsi.c:39:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 138 lines checked
95defd9d09d2 drm/i915/icl: Enable DDI Buffer
70390672d720 drm/i915/icl: Program T_INIT_MASTER registers
c6b328ee922e drm/i915/icl: Define data/clock lanes dphy timing registers
4f586b27f1d8 drm/i915/icl: Program DSI clock and data lane timing params
-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:116: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#116: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:130: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#130: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:192: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#192: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:198: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#198: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:203: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#203: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:228: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#228: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:233: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#233: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:252: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#252: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
00e8d4a4da2e drm/i915/icl: Define TA_TIMING_PARAM registers
9633b65f73df drm/i915/icl: Program TA_TIMING_PARAM registers
330b8eaf31ad drm/i915/icl: Get DSI transcoder for a given port
-:20: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#20: FILE: drivers/gpu/drm/i915/icl_dsi.c:30:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
25067852a150 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
2ba056a34af8 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:47: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#47: FILE: drivers/gpu/drm/i915/i915_reg.h:10396:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

total: 0 errors, 0 warnings, 1 checks, 54 lines checked
74707887f37e drm/i915/icl: Configure DSI transcoders
9bdf8144d433 drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
d41c7f8dd938 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
-:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#21: FILE: drivers/gpu/drm/i915/icl_dsi.c:344:
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/icl_dsi.c:476:
+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

total: 0 errors, 0 warnings, 2 checks, 88 lines checked
605fd9be0d02 drm/i915/icl: Define DSI transcoder timing registers
f3f7796930bb drm/i915/icl: Configure DSI transcoder timings
-:24: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#24: FILE: drivers/gpu/drm/i915/icl_dsi.c:476:
+static void gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
+				const struct intel_crtc_state *pipe_config)

-:52: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#52: FILE: drivers/gpu/drm/i915/icl_dsi.c:504:
+	vsync_shift = hsync_start - htotal/2;
 	                                  ^

-:66: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666'
#66: FILE: drivers/gpu/drm/i915/icl_dsi.c:518:
+	if ((intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666) &&
+	    ((hactive % 4) != 0))

total: 0 errors, 0 warnings, 3 checks, 138 lines checked
574f03ac11ac drm/i915/icl: Define TRANS_CONF register for DSI
21de99317a80 drm/i915/icl: Enable DSI transcoders
2cbb64e9d49c drm/i915/icl: Define DSI panel programming registers
78802bf69fe2 drm/i915/icl: Set max return packet size for DSI panel

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✗ Fi.CI.SPARSE: warning for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Configure lane sequencing of combo phy transmitter
Okay!

Commit: drm/i915/icl: DSI vswing programming sequence
Okay!

Commit: drm/i915/icl: Enable DDI Buffer
Okay!

Commit: drm/i915/icl: Program T_INIT_MASTER registers
Okay!

Commit: drm/i915/icl: Define data/clock lanes dphy timing registers
Okay!

Commit: drm/i915/icl: Program DSI clock and data lane timing params
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void)

Commit: drm/i915/icl: Define TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Program TA_TIMING_PARAM registers
Okay!

Commit: drm/i915/icl: Get DSI transcoder for a given port
Okay!

Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers
Okay!

Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
Okay!

Commit: drm/i915/icl: Configure DSI transcoders
Okay!

Commit: drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
Okay!

Commit: drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
Okay!

Commit: drm/i915/icl: Define DSI transcoder timing registers
Okay!

Commit: drm/i915/icl: Configure DSI transcoder timings
Okay!

Commit: drm/i915/icl: Define TRANS_CONF register for DSI
Okay!

Commit: drm/i915/icl: Enable DSI transcoders
Okay!

Commit: drm/i915/icl: Define DSI panel programming registers
Okay!

Commit: drm/i915/icl: Set max return packet size for DSI panel
Okay!

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✗ Fi.CI.BAT: failure for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4833 -> Patchwork_10199 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10199 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10199, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10199:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       PASS -> WARN

    
== Known issues ==

  Here are the changes found in Patchwork_10199 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_psr@primary_page_flip:
      fi-kbl-7560u:       PASS -> FAIL (fdo#107336)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-glk-j4005:       INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-icl-u:           INCOMPLETE (fdo#107713) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       DMESG-FAIL (fdo#103713) -> PASS

    igt@kms_setmode@basic-clone-single-crtc:
      fi-snb-2520m:       DMESG-WARN (fdo#103713) -> PASS

    
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (46 -> 42) ==

  Missing    (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4833 -> Patchwork_10199

  CI_DRM_4833: 75bb460b367a614d10b0fba220143bee42657d7e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4644: 0b59bb3231ab481959528c5c7b3a98762772e1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10199: 78802bf69fe2392586fa70123ec27ad2ffbd8f35 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

78802bf69fe2 drm/i915/icl: Set max return packet size for DSI panel
2cbb64e9d49c drm/i915/icl: Define DSI panel programming registers
21de99317a80 drm/i915/icl: Enable DSI transcoders
574f03ac11ac drm/i915/icl: Define TRANS_CONF register for DSI
f3f7796930bb drm/i915/icl: Configure DSI transcoder timings
605fd9be0d02 drm/i915/icl: Define DSI transcoder timing registers
d41c7f8dd938 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
9bdf8144d433 drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
74707887f37e drm/i915/icl: Configure DSI transcoders
2ba056a34af8 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
25067852a150 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
330b8eaf31ad drm/i915/icl: Get DSI transcoder for a given port
9633b65f73df drm/i915/icl: Program TA_TIMING_PARAM registers
00e8d4a4da2e drm/i915/icl: Define TA_TIMING_PARAM registers
4f586b27f1d8 drm/i915/icl: Program DSI clock and data lane timing params
c6b328ee922e drm/i915/icl: Define data/clock lanes dphy timing registers
70390672d720 drm/i915/icl: Program T_INIT_MASTER registers
95defd9d09d2 drm/i915/icl: Enable DDI Buffer
ef7b1857842d drm/i915/icl: DSI vswing programming sequence
33aac050cb0a drm/i915/icl: Configure lane sequencing of combo phy transmitter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10199/issues.html
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✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4833 -> Patchwork_10202 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/6/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10202 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_psr@primary_mmap_gtt:
      {fi-cnl-u}:         NOTRUN -> FAIL (fdo#107383) +3

    igt@kms_psr@primary_page_flip:
      fi-kbl-7560u:       PASS -> FAIL (fdo#107336)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-glk-j4005:       INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-icl-u:           INCOMPLETE (fdo#107713) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-kbl-r:           FAIL (fdo#107336) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (46 -> 42) ==

  Additional (1): fi-cnl-u 
  Missing    (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4833 -> Patchwork_10202

  CI_DRM_4833: 75bb460b367a614d10b0fba220143bee42657d7e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4644: 0b59bb3231ab481959528c5c7b3a98762772e1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10202: 15b08802bda983cab8eb17011ec5223b58d2b2f6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

15b08802bda9 drm/i915/icl: Set max return packet size for DSI panel
f2dc51c599ca drm/i915/icl: Define DSI panel programming registers
53c7f89bc2c8 drm/i915/icl: Enable DSI transcoders
d60941c04633 drm/i915/icl: Define TRANS_CONF register for DSI
84150913bbec drm/i915/icl: Configure DSI transcoder timings
931e0ac850e1 drm/i915/icl: Define DSI transcoder timing registers
4ce170f7cb63 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
dd8121a8cd3e drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
26b610a7e8ec drm/i915/icl: Configure DSI transcoders
f93429566bcb drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
3ebb9338c995 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
a849c1a4275d drm/i915/icl: Get DSI transcoder for a given port
8fbbc4ee3420 drm/i915/icl: Program TA_TIMING_PARAM registers
7bd867a46062 drm/i915/icl: Define TA_TIMING_PARAM registers
fc458cdc926d drm/i915/icl: Program DSI clock and data lane timing params
ca0b99a5f68a drm/i915/icl: Define data/clock lanes dphy timing registers
dcc54b5bf339 drm/i915/icl: Program T_INIT_MASTER registers
6800122a52f4 drm/i915/icl: Enable DDI Buffer
a23c4fb75969 drm/i915/icl: DSI vswing programming sequence
e73ace1c09ae drm/i915/icl: Configure lane sequencing of combo phy transmitter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10202/issues.html
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✓ Fi.CI.IGT: success for ICELAKE DSI DRIVER (rev6)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev6)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4833_full -> Patchwork_10202_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10202_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-apl:          PASS -> INCOMPLETE (fdo#106886, fdo#103927)

    igt@gem_pipe_control_store_loop@reused-buffer:
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359)

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          PASS -> INCOMPLETE (fdo#106023, fdo#103665)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
      shard-apl:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#105363)

    
    ==== Possible fixes ====

    igt@kms_busy@extended-pageflip-hang-newfb-render-a:
      shard-glk:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_frontbuffer_tracking@fbc-stridechange:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4833 -> Patchwork_10202

  CI_DRM_4833: 75bb460b367a614d10b0fba220143bee42657d7e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4644: 0b59bb3231ab481959528c5c7b3a98762772e1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10202: 15b08802bda983cab8eb17011ec5223b58d2b2f6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10202/shards.html
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