Re: [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Sep 17, 2018 at 12:49:35PM -0400, Jyoti Yadav wrote:
> DC5 and DC6 counter register tells about residency of DC5 and DC6.
> These registers are same for SKL and ICL.
> 
> Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a5265c2..328e39c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2898,7 +2898,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  		   CSR_VERSION_MINOR(csr->version));
>  
>  	if (IS_KABYLAKE(dev_priv) ||
> -	    (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> +	    (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))
> +		(IS_ICELAKE(dev_priv) && csr->version >= CSR_VERSION(1, 7))) {

Why on ICELAKE we need to be greater than version 1.7?
Specially because our only version starts on 1.7 I don't believe we should
be checking version here.

Also SKL check is useless nowadays and should be removed. It came from
the times we didn't have tied version of kernel and firmware...

Also I'm missing CFL, BXT, GLK and CNL on this range here...

Probably good to replace everything

if gen >= 9 && gen <= 11

?

>  		seq_printf(m, "DC3 -> DC5 count: %d\n",
>  			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
>  		seq_printf(m, "DC5 -> DC6 count: %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88..573d5f3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6985,6 +6985,7 @@ enum {
>  /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
>  #define CSR_MMIO_START_RANGE	0x80000
>  #define CSR_MMIO_END_RANGE	0x8FFFF
> +/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL */
>  #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
>  #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
>  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> -- 
> 1.9.1
> 
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