Re: [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, chris.p.wilson@intel.com
Subject: Re: [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
Date: Fri, 5 Oct 2018 13:45:55 -0700	[thread overview]
Message-ID: <20181005204555.GB16191@intel.com> (raw)
In-Reply-To: <20181005200435.GZ9144@intel.com>

On Fri, Oct 05, 2018 at 11:04:35PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 02:08:46PM -0400, Jyoti Yadav wrote:
> > DC5 and DC6 counter register tells about residency of DC5 and DC6.
> > Added the same in debugfs file.
> > 
> > v2 : Remove csr_version check.
> >      Added generic check regarding DC counters for  Gen9 onwards. (Rodrigo)
> > v3 : Simplified gen checks. (Chris)
> > v4 : Simplified "if" ladder for multiple gens.
> > v5 : Removed unnecessary comment.
> > 
> > Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
> >  1 file changed, 4 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index a5265c2..738f8c7 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2897,15 +2897,14 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> >  		   CSR_VERSION_MINOR(csr->version));
> >  
> > -	if (IS_KABYLAKE(dev_priv) ||
> > -	    (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
> > +	if (IS_BROXTON(dev_priv)) {
> > +		seq_printf(m, "DC3 -> DC5 count: %d\n",
> > +			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > +	} else if (IS_GEN(dev_priv, 9, 11)) {
> 
> What about CFL/GLK/CNL? They didn't take either branch previously.

In the past we didn't have the confirmation from DMC teams
the registers were there. But we got confirmation that they
are there and other drivers use those for validation.

So this adds for all platforms. Maybe commit message could address
that better? But the patch result is right imh so I believe we
could just go ahead.

Also I understand that Jyoti is working on IGT test cases for
this in a generic way too...

> 
> >  		seq_printf(m, "DC3 -> DC5 count: %d\n",
> >  			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
> >  		seq_printf(m, "DC5 -> DC6 count: %d\n",
> >  			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
> > -	} else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
> > -		seq_printf(m, "DC3 -> DC5 count: %d\n",
> > -			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
> >  	}
> >  
> >  out:
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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