From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manasi Navare Subject: [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Date: Fri, 5 Oct 2018 16:23:02 -0700 Message-ID: <20181005232306.31133-25-manasi.d.navare@intel.com> References: <20181005232306.31133-1-manasi.d.navare@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181005232306.31133-1-manasi.d.navare@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org RGlzcGxheSBTdHJlYW0gU3BsaXR0ZXIgcmVnaXN0ZXJzIG5lZWQgdG8gYmUgcHJvZ3JhbW1lZCB0 byBlbmFibGUKdGhlIGpvaW5lciBpZiB0d28gRFNDIGVuZ2luZXMgYXJlIHVzZWQgYW5kIGFsc28g dG8gZW5hYmxlCnRoZSBsZWZ0IGFuZCB0aGUgcmlnaHQgRFNDIGVuZ2luZXMuIFRoaXMgaGFwcGVu cyBhcyBwYXJ0IG9mCnRoZSBEU0MgZW5hYmxpbmcgcm91dGluZSBpbiB0aGUgc291cmNlIGluIGF0 b21pYyBjb21taXQuCgp2MjoKKiBSZWJhc2UgKE1hbmFzaSkKCkNjOiBKYW5pIE5pa3VsYSA8amFu aS5uaWt1bGFAbGludXguaW50ZWwuY29tPgpDYzogVmlsbGUgU3lyamFsYSA8dmlsbGUuc3lyamFs YUBsaW51eC5pbnRlbC5jb20+CkNjOiBBbnVzaGEgU3JpdmF0c2EgPGFudXNoYS5zcml2YXRzYUBp bnRlbC5jb20+ClNpZ25lZC1vZmYtYnk6IE1hbmFzaSBOYXZhcmUgPG1hbmFzaS5kLm5hdmFyZUBp bnRlbC5jb20+ClJldmlld2VkLWJ5OiBBbnVzaGEgU3JpdmF0c2EgPGFudXNoYS5zcml2YXRzYUBp bnRlbGNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF92ZHNjLmMgfCAyMiArKysr KysrKysrKysrKysrKysrKysrCiAxIGZpbGUgY2hhbmdlZCwgMjIgaW5zZXJ0aW9ucygrKQoKZGlm ZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3Zkc2MuYyBiL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2ludGVsX3Zkc2MuYwppbmRleCBmMmIzYjMwYjZmNWUuLmQzMDAxNjQ3YTg4NyAx MDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfdmRzYy5jCisrKyBiL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3Zkc2MuYwpAQCAtMTAwOSw2ICsxMDA5LDEyIEBAIHN0YXRp YyB2b2lkIGludGVsX2RwX3NlbmRfZHNjX3Bwc19zZHAoc3RydWN0IGludGVsX2VuY29kZXIgKmVu Y29kZXIsCiB2b2lkIGludGVsX2RzY19lbmFibGUoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29k ZXIsCiAJCSAgICAgIHN0cnVjdCBpbnRlbF9jcnRjX3N0YXRlICpjcnRjX3N0YXRlKQogeworCXN0 cnVjdCBpbnRlbF9jcnRjICpjcnRjID0gdG9faW50ZWxfY3J0YyhjcnRjX3N0YXRlLT5iYXNlLmNy dGMpOworCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUoZW5jb2Rl ci0+YmFzZS5kZXYpOworCWVudW0gcGlwZSBwaXBlID0gY3J0Yy0+cGlwZTsKKwlpOTE1X3JlZ190 IGRzc19jdGwxX3JlZywgZHNzX2N0bDJfcmVnOworCXUzMiBkc3NfY3RsMV92YWwgPSAwOworCXUz MiBkc3NfY3RsMl92YWwgPSAwOwogCiAJaWYgKCFjcnRjX3N0YXRlLT5kc2NfcGFyYW1zLmNvbXBy ZXNzaW9uX2VuYWJsZSkKIAkJcmV0dXJuOwpAQCAtMTAxNyw1ICsxMDIzLDIxIEBAIHZvaWQgaW50 ZWxfZHNjX2VuYWJsZShzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwKIAogCWludGVsX2Rw X3NlbmRfZHNjX3Bwc19zZHAoZW5jb2RlciwgY3J0Y19zdGF0ZSk7CiAKKwkvKiBDb25maWd1cmUg RFNTX0NUTCByZWdpc3RlcnMgZm9yIERTQyAqLworCWlmIChlbmNvZGVyLT50eXBlID09IElOVEVM X09VVFBVVF9FRFApIHsKKwkJZHNzX2N0bDFfcmVnID0gRFNTX0NUTDE7CisJCWRzc19jdGwyX3Jl ZyA9IERTU19DVEwyOworCX0gZWxzZSB7CisJCWRzc19jdGwxX3JlZyA9IElDTF9QSVBFX0RTU19D VEwxKHBpcGUpOworCQlkc3NfY3RsMl9yZWcgPSBJQ0xfUElQRV9EU1NfQ1RMMihwaXBlKTsKKwl9 CisJZHNzX2N0bDJfdmFsIHw9IExFRlRfQlJBTkNIX1ZEU0NfRU5BQkxFOworCWlmIChjcnRjX3N0 YXRlLT5kc2NfcGFyYW1zLmRzY19zcGxpdCkgeworCQlkc3NfY3RsMl92YWwgfD0gUklHSFRfQlJB TkNIX1ZEU0NfRU5BQkxFOworCQlkc3NfY3RsMV92YWwgfD0gSk9JTkVSX0VOQUJMRTsKKwl9CisJ STkxNV9XUklURShkc3NfY3RsMV9yZWcsIGRzc19jdGwxX3ZhbCk7CisJSTkxNV9XUklURShkc3Nf Y3RsMl9yZWcsIGRzc19jdGwyX3ZhbCk7CisKIAlyZXR1cm47CiB9Ci0tIAoyLjE4LjAKCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWls aW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=