[PATCH 0/8] Refactor and Add helper function for combophy/tc ports

[PATCH 0/8] Refactor and Add helper function for combophy/tc ports

[Mahesh Kumar]

This series refactor code and register definitions for combophy
port registers. And also creates helper functions to identify
combophy/tc ports.

Lucas De Marchi (1):
  drm/i915/icl: Introduce new macros to get combophy registers

Mahesh Kumar (4):
  drm/i915/icl: create function to identify combophy port
  drm/i915/icl: use combophy/TC helper functions during display
    detection
  drm/i915/icl: Combine all port/combophy macros at one place
  drm/i915/icl: Fix DDI/TC port clk_off bits

Vandita Kulkarni (3):
  drm/i915/icl: Refactor get_ddi_pll using helper func
  drm/i915/icl: Use helper functions to classify the ports
  drm/i915/icl: Refactor icl pll functions

 drivers/gpu/drm/i915/i915_reg.h       | 245 +++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_ddi.c      |  36 +++--
 drivers/gpu/drm/i915/intel_display.c  |  36 +++--
 drivers/gpu/drm/i915/intel_dp.c       |  15 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  70 +++-------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   2 +
 drivers/gpu/drm/i915/intel_drv.h      |   1 +
 7 files changed, 178 insertions(+), 227 deletions(-)

-- 
2.16.2

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[PATCH 1/8] drm/i915/icl: create function to identify combophy port

[Mahesh Kumar]

This patch creates a function/wrapper to check if port is combophy port
instead of explicitly comparing ports.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7f34d3955ca1..b5b8dae06cde 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port,
 						INTEL_OUTPUT_HDMI, &n_entries);
 		else
@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	uint32_t pll_id;
 
 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
-	if (port == PORT_A || port == PORT_B) {
+	if (intel_port_is_combophy(dev_priv, port)) {
 		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
 			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
 		else
@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	int n_entries;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
 						&n_entries);
 		else
@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    u32 level,
 				    enum intel_output_type type)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	if (port == PORT_A || port == PORT_B)
+	if (intel_port_is_combophy(dev_priv, port))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 		val = I915_READ(DPCLKA_CFGCR0_ICL);
 		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
 
-		if (port == PORT_A || port == PORT_B) {
+		if (intel_port_is_combophy(dev_priv, port)) {
 			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
@@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_pll_sel(encoder, pll));
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	enum port port = encoder->port;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4c5c2b39e65c..916eb71e78ed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 	return port - PORT_C;
 }
 
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+{
+	if (port == PORT_NONE)
+		return false;
+
+	if (IS_ICELAKE(dev_priv))
+		return (port <= PORT_B);
+
+	return false;
+}
+
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
 {
 	switch (port) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cbcae246d742..86567f26138b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
 			     struct intel_crtc_state *crtc_state,
 			     struct drm_atomic_state *old_state);
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
 
 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 				   int color_plane, unsigned int height);
-- 
2.16.2

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Re: [PATCH 1/8] drm/i915/icl: create function to identify combophy port

[Rodrigo Vivi]

On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);
> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
> 
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH 1/8] drm/i915/icl: create function to identify combophy port

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);

please remove parenthesis

> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);

this should be together with the other helper with the same namespace, i.e. on top
of intel_port_is_tc()

Lucas De Marchi

>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
> 
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[PATCH v2 1/8] drm/i915/icl: create function to identify combophy port

[Mahesh Kumar]

This patch creates a function/wrapper to check if port is combophy port
instead of explicitly comparing ports.

Changes since V1:
 - keep all intel_port_is_* helper together (Lucas)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b6594948b617..69b7355845ac 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port,
 						INTEL_OUTPUT_HDMI, &n_entries);
 		else
@@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	uint32_t pll_id;
 
 	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
-	if (port == PORT_A || port == PORT_B) {
+	if (intel_port_is_combophy(dev_priv, port)) {
 		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
 			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
 		else
@@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	int n_entries;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port == PORT_A || port == PORT_B)
+		if (intel_port_is_combophy(dev_priv, port))
 			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
 						&n_entries);
 		else
@@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    u32 level,
 				    enum intel_output_type type)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	if (port == PORT_A || port == PORT_B)
+	if (intel_port_is_combophy(dev_priv, port))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 		val = I915_READ(DPCLKA_CFGCR0_ICL);
 		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
 
-		if (port == PORT_A || port == PORT_B) {
+		if (intel_port_is_combophy(dev_priv, port)) {
 			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
@@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_pll_sel(encoder, pll));
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	enum port port = encoder->port;
 
 	if (IS_ICELAKE(dev_priv)) {
-		if (port >= PORT_C)
+		if (!intel_port_is_combophy(dev_priv, port))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 36434c5359b1..60aa033405bd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5944,6 +5944,17 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
 	I915_WRITE(BCLRPAT(crtc->pipe), 0);
 }
 
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+{
+	if (port == PORT_NONE)
+		return false;
+
+	if (IS_ICELAKE(dev_priv))
+		return port <= PORT_B;
+
+	return false;
+}
+
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
 {
 	if (IS_ICELAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 43190c6e9ef2..0661a3115f76 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1515,6 +1515,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
 				    struct intel_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
+bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 			      enum port port);
-- 
2.16.2

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Re: [PATCH v2 1/8] drm/i915/icl: create function to identify combophy port

[Lucas De Marchi]

On Thu, Oct 04, 2018 at 02:20:43PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Changes since V1:
>  - keep all intel_port_is_* helper together (Lucas)
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b6594948b617..69b7355845ac 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 36434c5359b1..60aa033405bd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5944,6 +5944,17 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
>  	I915_WRITE(BCLRPAT(crtc->pipe), 0);
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return port <= PORT_B;
> +
> +	return false;
> +}
> +
>  bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	if (IS_ICELAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 43190c6e9ef2..0661a3115f76 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1515,6 +1515,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
>  				    struct intel_encoder *encoder);
>  struct drm_display_mode *
>  intel_encoder_current_mode(struct intel_encoder *encoder);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>  bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>  enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>  			      enum port port);
> -- 
> 2.16.2
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/8] drm/i915/icl: create function to identify combophy port

[Manasi Navare]

On Wed, Oct 03, 2018 at 12:51:56PM +0530, Mahesh Kumar wrote:
> This patch creates a function/wrapper to check if port is combophy port
> instead of explicitly comparing ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>

Looks good to me.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 15 ++++++++-------
>  drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7f34d3955ca1..b5b8dae06cde 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -916,7 +916,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port,
>  						INTEL_OUTPUT_HDMI, &n_entries);
>  		else
> @@ -1535,7 +1535,7 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
>  	uint32_t pll_id;
>  
>  	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
> -	if (port == PORT_A || port == PORT_B) {
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
>  			link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
>  		else
> @@ -2235,7 +2235,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  	int n_entries;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port == PORT_A || port == PORT_B)
> +		if (intel_port_is_combophy(dev_priv, port))
>  			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>  						&n_entries);
>  		else
> @@ -2669,9 +2669,10 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
>  				    u32 level,
>  				    enum intel_output_type type)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A || port == PORT_B)
> +	if (intel_port_is_combophy(dev_priv, port))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2757,7 +2758,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
>  		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
>  
> -		if (port == PORT_A || port == PORT_B) {
> +		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> @@ -2810,7 +2811,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
>  				   icl_pll_to_ddi_pll_sel(encoder, pll));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2852,7 +2853,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	enum port port = encoder->port;
>  
>  	if (IS_ICELAKE(dev_priv)) {
> -		if (port >= PORT_C)
> +		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4c5c2b39e65c..916eb71e78ed 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5947,6 +5947,17 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>  	return port - PORT_C;
>  }
>  
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> +{
> +	if (port == PORT_NONE)
> +		return false;
> +
> +	if (IS_ICELAKE(dev_priv))
> +		return (port <= PORT_B);
> +
> +	return false;
> +}
> +
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>  {
>  	switch (port) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index cbcae246d742..86567f26138b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1443,6 +1443,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  			     struct intel_crtc_state *crtc_state,
>  			     struct drm_atomic_state *old_state);
> +bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>  
>  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
>  				   int color_plane, unsigned int height);
> -- 
> 2.16.2
> 
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[PATCH 2/8] drm/i915/icl: use combophy/TC helper functions during display detection

[Mahesh Kumar]

Instead of directly comparing HPD pins use intel_port_is_combophy/tc
helper functions to distinguish between combophy/TC ports.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 15a981ef5966..f6b9be81ea18 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4965,19 +4965,14 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 
-	switch (encoder->hpd_pin) {
-	case HPD_PORT_A:
-	case HPD_PORT_B:
+	if (intel_port_is_combophy(dev_priv, encoder->port))
 		return icl_combo_port_connected(dev_priv, dig_port);
-	case HPD_PORT_C:
-	case HPD_PORT_D:
-	case HPD_PORT_E:
-	case HPD_PORT_F:
+	else if (intel_port_is_tc(dev_priv, encoder->port))
 		return icl_tc_port_connected(dev_priv, dig_port);
-	default:
+	else
 		MISSING_CASE(encoder->hpd_pin);
-		return false;
-	}
+
+	return false;
 }
 
 /*
-- 
2.16.2

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Re: [PATCH 2/8] drm/i915/icl: use combophy/TC helper functions during display detection

[Rodrigo Vivi]

On Wed, Oct 03, 2018 at 12:51:57PM +0530, Mahesh Kumar wrote:
> Instead of directly comparing HPD pins use intel_port_is_combophy/tc
> helper functions to distinguish between combophy/TC ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 15a981ef5966..f6b9be81ea18 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4965,19 +4965,14 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>  
> -	switch (encoder->hpd_pin) {
> -	case HPD_PORT_A:
> -	case HPD_PORT_B:
> +	if (intel_port_is_combophy(dev_priv, encoder->port))
>  		return icl_combo_port_connected(dev_priv, dig_port);
> -	case HPD_PORT_C:
> -	case HPD_PORT_D:
> -	case HPD_PORT_E:
> -	case HPD_PORT_F:
> +	else if (intel_port_is_tc(dev_priv, encoder->port))
>  		return icl_tc_port_connected(dev_priv, dig_port);
> -	default:
> +	else
>  		MISSING_CASE(encoder->hpd_pin);
> -		return false;
> -	}
> +
> +	return false;
>  }
>  
>  /*
> -- 
> 2.16.2
> 
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Re: [PATCH 2/8] drm/i915/icl: use combophy/TC helper functions during display detection

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:51:57PM +0530, Mahesh Kumar wrote:
> Instead of directly comparing HPD pins use intel_port_is_combophy/tc
> helper functions to distinguish between combophy/TC ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> ---

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

>  drivers/gpu/drm/i915/intel_dp.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 15a981ef5966..f6b9be81ea18 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4965,19 +4965,14 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>  
> -	switch (encoder->hpd_pin) {
> -	case HPD_PORT_A:
> -	case HPD_PORT_B:
> +	if (intel_port_is_combophy(dev_priv, encoder->port))
>  		return icl_combo_port_connected(dev_priv, dig_port);
> -	case HPD_PORT_C:
> -	case HPD_PORT_D:
> -	case HPD_PORT_E:
> -	case HPD_PORT_F:
> +	else if (intel_port_is_tc(dev_priv, encoder->port))
>  		return icl_tc_port_connected(dev_priv, dig_port);
> -	default:
> +	else
>  		MISSING_CASE(encoder->hpd_pin);
> -		return false;
> -	}
> +
> +	return false;
>  }
>  
>  /*
> -- 
> 2.16.2
> 
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[PATCH 3/8] drm/i915/icl: Refactor get_ddi_pll using helper func

[Mahesh Kumar]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Use the existing port-to-id helper function, to refactor
hence making it scalable.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 8 +-------
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 1 +
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 916eb71e78ed..16d9a20a420a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9307,16 +9307,10 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 			return;
 		break;
 	case PORT_C:
-		id = DPLL_ID_ICL_MGPLL1;
-		break;
 	case PORT_D:
-		id = DPLL_ID_ICL_MGPLL2;
-		break;
 	case PORT_E:
-		id = DPLL_ID_ICL_MGPLL3;
-		break;
 	case PORT_F:
-		id = DPLL_ID_ICL_MGPLL4;
+		id = icl_port_to_mg_pll_id(port);
 		break;
 	default:
 		MISSING_CASE(port);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e6cac9225536..510ea90f6f5b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2628,7 +2628,7 @@ static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
 	return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
 }
 
-static enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
+enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
 {
 	return port - PORT_C + DPLL_ID_ICL_MGPLL1;
 }
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index bf0de8a4dc63..5305ce1c2175 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -345,5 +345,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
 			       uint32_t pll_id);
 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
+enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
 
 #endif /* _INTEL_DPLL_MGR_H_ */
-- 
2.16.2

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Re: [PATCH 3/8] drm/i915/icl: Refactor get_ddi_pll using helper func

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:51:58PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Use the existing port-to-id helper function, to refactor
> hence making it scalable.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_display.c  | 8 +-------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h | 1 +
>  3 files changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 916eb71e78ed..16d9a20a420a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9307,16 +9307,10 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  			return;
>  		break;
>  	case PORT_C:
> -		id = DPLL_ID_ICL_MGPLL1;
> -		break;
>  	case PORT_D:
> -		id = DPLL_ID_ICL_MGPLL2;
> -		break;
>  	case PORT_E:
> -		id = DPLL_ID_ICL_MGPLL3;
> -		break;
>  	case PORT_F:
> -		id = DPLL_ID_ICL_MGPLL4;
> +		id = icl_port_to_mg_pll_id(port);
>  		break;
>  	default:
>  		MISSING_CASE(port);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e6cac9225536..510ea90f6f5b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2628,7 +2628,7 @@ static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
>  	return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
>  }
>  
> -static enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
> +enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
>  {
>  	return port - PORT_C + DPLL_ID_ICL_MGPLL1;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index bf0de8a4dc63..5305ce1c2175 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -345,5 +345,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
>  int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>  			       uint32_t pll_id);
>  int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> +enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
>  
>  #endif /* _INTEL_DPLL_MGR_H_ */
> -- 
> 2.16.2
> 
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[PATCH 4/8] drm/i915/icl: Use helper functions to classify the ports

[Mahesh Kumar]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Use intel_port_is_tc and intel_port_is_combophy
functions to replace the individual port checks
from port C to F and port A to B respectively.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 15 ++++-----------
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++----------
 2 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 16d9a20a420a..e31d71526afd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 	u32 temp;
 
 	/* TODO: TBT pll not implemented. */
-	switch (port) {
-	case PORT_A:
-	case PORT_B:
+	if (intel_port_is_combophy(dev_priv, port)) {
 		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
 		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
 
 		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
 			return;
-		break;
-	case PORT_C:
-	case PORT_D:
-	case PORT_E:
-	case PORT_F:
+	} else if (intel_port_is_tc(dev_priv, port)) {
 		id = icl_port_to_mg_pll_id(port);
-		break;
-	default:
-		MISSING_CASE(port);
+	} else {
+		WARN(1, "Invalid port %x\n", port);
 		return;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 510ea90f6f5b..5b2ee49aee14 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2874,6 +2874,7 @@ static struct intel_shared_dpll *
 icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 	     struct intel_encoder *encoder)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *intel_dig_port =
 			enc_to_dig_port(&encoder->base);
 	struct intel_shared_dpll *pll;
@@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 	int clock = crtc_state->port_clock;
 	bool ret;
 
-	switch (port) {
-	case PORT_A:
-	case PORT_B:
+	if (intel_port_is_combophy(dev_priv, port)) {
 		min = DPLL_ID_ICL_DPLL0;
 		max = DPLL_ID_ICL_DPLL1;
 		ret = icl_calc_dpll_state(crtc_state, encoder, clock,
 					  &pll_state);
-		break;
-	case PORT_C:
-	case PORT_D:
-	case PORT_E:
-	case PORT_F:
+	} else if (intel_port_is_tc(dev_priv, port)) {
 		if (intel_dig_port->tc_type == TC_PORT_TBT) {
 			min = DPLL_ID_ICL_TBTPLL;
 			max = min;
@@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 			ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
 						    &pll_state);
 		}
-		break;
-	default:
+	} else {
 		MISSING_CASE(port);
 		return NULL;
 	}
-- 
2.16.2

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Re: [PATCH 4/8] drm/i915/icl: Use helper functions to classify the ports

[Rodrigo Vivi]

On Wed, Oct 03, 2018 at 12:51:59PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Use intel_port_is_tc and intel_port_is_combophy
> functions to replace the individual port checks
> from port C to F and port A to B respectively.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c  | 15 ++++-----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++----------
>  2 files changed, 8 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 16d9a20a420a..e31d71526afd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  	u32 temp;
>  
>  	/* TODO: TBT pll not implemented. */
> -	switch (port) {
> -	case PORT_A:
> -	case PORT_B:
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
>  		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>  
>  		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
>  			return;
> -		break;
> -	case PORT_C:
> -	case PORT_D:
> -	case PORT_E:
> -	case PORT_F:
> +	} else if (intel_port_is_tc(dev_priv, port)) {
>  		id = icl_port_to_mg_pll_id(port);
> -		break;
> -	default:
> -		MISSING_CASE(port);
> +	} else {
> +		WARN(1, "Invalid port %x\n", port);
>  		return;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 510ea90f6f5b..5b2ee49aee14 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll *
>  icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	     struct intel_encoder *encoder)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *intel_dig_port =
>  			enc_to_dig_port(&encoder->base);
>  	struct intel_shared_dpll *pll;
> @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	int clock = crtc_state->port_clock;
>  	bool ret;
>  
> -	switch (port) {
> -	case PORT_A:
> -	case PORT_B:
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		min = DPLL_ID_ICL_DPLL0;
>  		max = DPLL_ID_ICL_DPLL1;
>  		ret = icl_calc_dpll_state(crtc_state, encoder, clock,
>  					  &pll_state);
> -		break;
> -	case PORT_C:
> -	case PORT_D:
> -	case PORT_E:
> -	case PORT_F:
> +	} else if (intel_port_is_tc(dev_priv, port)) {
>  		if (intel_dig_port->tc_type == TC_PORT_TBT) {
>  			min = DPLL_ID_ICL_TBTPLL;
>  			max = min;
> @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  			ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
>  						    &pll_state);
>  		}
> -		break;
> -	default:
> +	} else {
>  		MISSING_CASE(port);
>  		return NULL;
>  	}
> -- 
> 2.16.2
> 
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Re: [PATCH 4/8] drm/i915/icl: Use helper functions to classify the ports

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:51:59PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Use intel_port_is_tc and intel_port_is_combophy
> functions to replace the individual port checks
> from port C to F and port A to B respectively.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_display.c  | 15 ++++-----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 14 ++++----------
>  2 files changed, 8 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 16d9a20a420a..e31d71526afd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9296,24 +9296,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  	u32 temp;
>  
>  	/* TODO: TBT pll not implemented. */
> -	switch (port) {
> -	case PORT_A:
> -	case PORT_B:
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
>  		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>  
>  		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
>  			return;
> -		break;
> -	case PORT_C:
> -	case PORT_D:
> -	case PORT_E:
> -	case PORT_F:
> +	} else if (intel_port_is_tc(dev_priv, port)) {
>  		id = icl_port_to_mg_pll_id(port);
> -		break;
> -	default:
> -		MISSING_CASE(port);
> +	} else {
> +		WARN(1, "Invalid port %x\n", port);
>  		return;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 510ea90f6f5b..5b2ee49aee14 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2874,6 +2874,7 @@ static struct intel_shared_dpll *
>  icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	     struct intel_encoder *encoder)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *intel_dig_port =
>  			enc_to_dig_port(&encoder->base);
>  	struct intel_shared_dpll *pll;
> @@ -2883,18 +2884,12 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	int clock = crtc_state->port_clock;
>  	bool ret;
>  
> -	switch (port) {
> -	case PORT_A:
> -	case PORT_B:
> +	if (intel_port_is_combophy(dev_priv, port)) {
>  		min = DPLL_ID_ICL_DPLL0;
>  		max = DPLL_ID_ICL_DPLL1;
>  		ret = icl_calc_dpll_state(crtc_state, encoder, clock,
>  					  &pll_state);
> -		break;
> -	case PORT_C:
> -	case PORT_D:
> -	case PORT_E:
> -	case PORT_F:
> +	} else if (intel_port_is_tc(dev_priv, port)) {
>  		if (intel_dig_port->tc_type == TC_PORT_TBT) {
>  			min = DPLL_ID_ICL_TBTPLL;
>  			max = min;
> @@ -2906,8 +2901,7 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  			ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
>  						    &pll_state);
>  		}
> -		break;
> -	default:
> +	} else {
>  		MISSING_CASE(port);
>  		return NULL;
>  	}
> -- 
> 2.16.2
> 
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[PATCH 5/8] drm/i915/icl: Refactor icl pll functions

[Mahesh Kumar]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

This patch adds helper function for identifying
whether the given PLL is combo PHY PLL or not.
This helper function is used inside various ICL
functions to make them scalable.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 54 +++++++++++------------------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
 3 files changed, 19 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e31d71526afd..a1c6891cf14b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9301,7 +9301,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
 
-		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
+		if (WARN_ON(!intel_dpll_is_combophy(id)))
 			return;
 	} else if (intel_port_is_tc(dev_priv, port)) {
 		id = icl_port_to_mg_pll_id(port);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5b2ee49aee14..93e8e2307989 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2633,6 +2633,11 @@ enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
 	return port - PORT_C + DPLL_ID_ICL_MGPLL1;
 }
 
+bool intel_dpll_is_combophy(enum intel_dpll_id id)
+{
+	return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
+}
+
 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 				     uint32_t *target_dco_khz,
 				     struct intel_dpll_hw_state *state)
@@ -2926,21 +2931,16 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 
 static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
 {
-	switch (id) {
-	default:
-		MISSING_CASE(id);
-		/* fall through */
-	case DPLL_ID_ICL_DPLL0:
-	case DPLL_ID_ICL_DPLL1:
+	if (intel_dpll_is_combophy(id))
 		return CNL_DPLL_ENABLE(id);
-	case DPLL_ID_ICL_TBTPLL:
+	else if (id == DPLL_ID_ICL_TBTPLL)
 		return TBT_PLL_ENABLE;
-	case DPLL_ID_ICL_MGPLL1:
-	case DPLL_ID_ICL_MGPLL2:
-	case DPLL_ID_ICL_MGPLL3:
-	case DPLL_ID_ICL_MGPLL4:
+	else
+		/*
+		 * TODO: Make MG_PLL macros use
+		 * tc port id instead of port id
+		 */
 		return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
-	}
 }
 
 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -2959,17 +2959,11 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	switch (id) {
-	case DPLL_ID_ICL_DPLL0:
-	case DPLL_ID_ICL_DPLL1:
-	case DPLL_ID_ICL_TBTPLL:
+	if (intel_dpll_is_combophy(id) ||
+	    id == DPLL_ID_ICL_TBTPLL) {
 		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
 		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
-		break;
-	case DPLL_ID_ICL_MGPLL1:
-	case DPLL_ID_ICL_MGPLL2:
-	case DPLL_ID_ICL_MGPLL3:
-	case DPLL_ID_ICL_MGPLL4:
+	} else {
 		port = icl_mg_pll_id_to_port(id);
 		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
 		hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
@@ -3007,9 +3001,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 		hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
 		hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
-		break;
-	default:
-		MISSING_CASE(id);
 	}
 
 	ret = true;
@@ -3098,21 +3089,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
 				    PLL_POWER_STATE, 1))
 		DRM_ERROR("PLL %d Power not enabled\n", id);
 
-	switch (id) {
-	case DPLL_ID_ICL_DPLL0:
-	case DPLL_ID_ICL_DPLL1:
-	case DPLL_ID_ICL_TBTPLL:
+	if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
 		icl_dpll_write(dev_priv, pll);
-		break;
-	case DPLL_ID_ICL_MGPLL1:
-	case DPLL_ID_ICL_MGPLL2:
-	case DPLL_ID_ICL_MGPLL3:
-	case DPLL_ID_ICL_MGPLL4:
+	else
 		icl_mg_pll_write(dev_priv, pll);
-		break;
-	default:
-		MISSING_CASE(id);
-	}
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 5305ce1c2175..6a79ced923e9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -346,5 +346,6 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
 			       uint32_t pll_id);
 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
 enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
+bool intel_dpll_is_combophy(enum intel_dpll_id id);
 
 #endif /* _INTEL_DPLL_MGR_H_ */
-- 
2.16.2

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Re: [PATCH 5/8] drm/i915/icl: Refactor icl pll functions

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:52:00PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> This patch adds helper function for identifying
> whether the given PLL is combo PHY PLL or not.
> This helper function is used inside various ICL
> functions to make them scalable.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_display.c  |  2 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 54 +++++++++++------------------------
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
>  3 files changed, 19 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e31d71526afd..a1c6891cf14b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9301,7 +9301,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>  
> -		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
> +		if (WARN_ON(!intel_dpll_is_combophy(id)))
>  			return;
>  	} else if (intel_port_is_tc(dev_priv, port)) {
>  		id = icl_port_to_mg_pll_id(port);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 5b2ee49aee14..93e8e2307989 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2633,6 +2633,11 @@ enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
>  	return port - PORT_C + DPLL_ID_ICL_MGPLL1;
>  }
>  
> +bool intel_dpll_is_combophy(enum intel_dpll_id id)
> +{
> +	return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
> +}
> +
>  static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  				     uint32_t *target_dco_khz,
>  				     struct intel_dpll_hw_state *state)
> @@ -2926,21 +2931,16 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  
>  static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
>  {
> -	switch (id) {
> -	default:
> -		MISSING_CASE(id);
> -		/* fall through */
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> +	if (intel_dpll_is_combophy(id))
>  		return CNL_DPLL_ENABLE(id);
> -	case DPLL_ID_ICL_TBTPLL:
> +	else if (id == DPLL_ID_ICL_TBTPLL)
>  		return TBT_PLL_ENABLE;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	else
> +		/*
> +		 * TODO: Make MG_PLL macros use
> +		 * tc port id instead of port id
> +		 */
>  		return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
> -	}
>  }
>  
>  static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -2959,17 +2959,11 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PLL_ENABLE))
>  		goto out;
>  
> -	switch (id) {
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> -	case DPLL_ID_ICL_TBTPLL:
> +	if (intel_dpll_is_combophy(id) ||
> +	    id == DPLL_ID_ICL_TBTPLL) {
>  		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>  		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> -		break;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	} else {
>  		port = icl_mg_pll_id_to_port(id);
>  		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
>  		hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
> @@ -3007,9 +3001,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  
>  		hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
>  		hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
> -		break;
> -	default:
> -		MISSING_CASE(id);
>  	}
>  
>  	ret = true;
> @@ -3098,21 +3089,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
>  				    PLL_POWER_STATE, 1))
>  		DRM_ERROR("PLL %d Power not enabled\n", id);
>  
> -	switch (id) {
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> -	case DPLL_ID_ICL_TBTPLL:
> +	if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
>  		icl_dpll_write(dev_priv, pll);
> -		break;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	else
>  		icl_mg_pll_write(dev_priv, pll);
> -		break;
> -	default:
> -		MISSING_CASE(id);
> -	}
>  
>  	/*
>  	 * DVFS pre sequence would be here, but in our driver the cdclk code
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 5305ce1c2175..6a79ced923e9 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -346,5 +346,6 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>  			       uint32_t pll_id);
>  int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
>  enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
> +bool intel_dpll_is_combophy(enum intel_dpll_id id);
>  
>  #endif /* _INTEL_DPLL_MGR_H_ */
> -- 
> 2.16.2
> 
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[PATCH 6/8] drm/i915/icl: Combine all port/combophy macros at one place

[Mahesh Kumar]

This patch combines CNL/ICL specific port/combophy macros together
at one location. This is prework for patches later in series where
new macros to find port/combophy register will be introduced.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++-------------------
 1 file changed, 73 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27e650fe591b..e3ac65f5aa81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1631,14 +1631,42 @@ enum i915_power_well_id {
 #define   PHY_RESERVED			(1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
 
-#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
-#define   CL_POWER_DOWN_ENABLE		(1 << 4)
-#define   SUS_CLOCK_CONFIG		(3 << 0)
+#define _PORT_CL1CM_DW9_A		0x162024
+#define _PORT_CL1CM_DW9_BC		0x6C024
+#define   IREF0RC_OFFSET_SHIFT		8
+#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
+
+#define _PORT_CL1CM_DW10_A		0x162028
+#define _PORT_CL1CM_DW10_BC		0x6C028
+#define   IREF1RC_OFFSET_SHIFT		8
+#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
+
+#define _PORT_CL1CM_DW28_A		0x162070
+#define _PORT_CL1CM_DW28_BC		0x6C070
+#define   OCL1_POWER_DOWN_EN		(1 << 23)
+#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
+#define   SUS_CLK_CONFIG		0x3
+#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
+
+#define _PORT_CL1CM_DW30_A		0x162078
+#define _PORT_CL1CM_DW30_BC		0x6C078
+#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
+
+/*
+ * CNL/ICL Port/COMBO-PHY Registers
+ */
+/* CNL/ICL Port CL_DW registers */
+#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
 
 #define _ICL_PORT_CL_DW5_A	0x162014
 #define _ICL_PORT_CL_DW5_B	0x6C014
 #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
 						 _ICL_PORT_CL_DW5_B)
+#define   CL_POWER_DOWN_ENABLE		(1 << 4)
+#define   SUS_CLOCK_CONFIG		(3 << 0)
 
 #define _CNL_PORT_CL_DW10_A		0x162028
 #define _ICL_PORT_CL_DW10_B		0x6c028
@@ -1660,18 +1688,6 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
 
-#define _PORT_CL1CM_DW9_A		0x162024
-#define _PORT_CL1CM_DW9_BC		0x6C024
-#define   IREF0RC_OFFSET_SHIFT		8
-#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
-
-#define _PORT_CL1CM_DW10_A		0x162028
-#define _PORT_CL1CM_DW10_BC		0x6C028
-#define   IREF1RC_OFFSET_SHIFT		8
-#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
-
 #define _ICL_PORT_CL_DW12_A		0x162030
 #define _ICL_PORT_CL_DW12_B		0x6C030
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
@@ -1679,18 +1695,49 @@ enum i915_power_well_id {
 						   _ICL_PORT_CL_DW12_A, \
 						   _ICL_PORT_CL_DW12_B)
 
-#define _PORT_CL1CM_DW28_A		0x162070
-#define _PORT_CL1CM_DW28_BC		0x6C070
-#define   OCL1_POWER_DOWN_EN		(1 << 23)
-#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
-#define   SUS_CLK_CONFIG		0x3
-#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
+/* CNL/ICL Port COMP_DW registers */
+#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
+#define _ICL_PORT_COMP_DW0_A		0x162100
+#define _ICL_PORT_COMP_DW0_B		0x6C100
+#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
+							 _ICL_PORT_COMP_DW0_B)
+#define   COMP_INIT			(1 << 31)
 
-#define _PORT_CL1CM_DW30_A		0x162078
-#define _PORT_CL1CM_DW30_BC		0x6C078
-#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
-#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
+#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
+#define _ICL_PORT_COMP_DW1_A		0x162104
+#define _ICL_PORT_COMP_DW1_B		0x6C104
+#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
+							 _ICL_PORT_COMP_DW1_B)
+#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
+#define _ICL_PORT_COMP_DW3_A		0x16210C
+#define _ICL_PORT_COMP_DW3_B		0x6C10C
+#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
+							 _ICL_PORT_COMP_DW3_B)
+#define   PROCESS_INFO_DOT_0		(0 << 26)
+#define   PROCESS_INFO_DOT_1		(1 << 26)
+#define   PROCESS_INFO_DOT_4		(2 << 26)
+#define   PROCESS_INFO_MASK		(7 << 26)
+#define   PROCESS_INFO_SHIFT		26
+#define   VOLTAGE_INFO_0_85V		(0 << 24)
+#define   VOLTAGE_INFO_0_95V		(1 << 24)
+#define   VOLTAGE_INFO_1_05V		(2 << 24)
+#define   VOLTAGE_INFO_MASK		(3 << 24)
+#define   VOLTAGE_INFO_SHIFT		24
 
+#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
+#define _ICL_PORT_COMP_DW9_A		0x162124
+#define _ICL_PORT_COMP_DW9_B		0x6C124
+#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
+							 _ICL_PORT_COMP_DW9_B)
+
+#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
+#define _ICL_PORT_COMP_DW10_A		0x162128
+#define _ICL_PORT_COMP_DW10_B		0x6C128
+#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_COMP_DW10_A, \
+						   _ICL_PORT_COMP_DW10_B)
+
+/* CNL/ICL Port PCS registers */
 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
 #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
 #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
@@ -1734,7 +1781,7 @@ enum i915_power_well_id {
 						   _ICL_PORT_PCS_DW1_AUX_B)
 #define   COMMON_KEEPER_EN		(1 << 26)
 
-/* CNL Port TX registers */
+/* CNL/ICL Port TX registers */
 #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
 #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
 #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
@@ -2054,45 +2101,6 @@ enum i915_power_well_id {
 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
-#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
-#define   COMP_INIT			(1 << 31)
-#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
-#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
-#define   PROCESS_INFO_DOT_0		(0 << 26)
-#define   PROCESS_INFO_DOT_1		(1 << 26)
-#define   PROCESS_INFO_DOT_4		(2 << 26)
-#define   PROCESS_INFO_MASK		(7 << 26)
-#define   PROCESS_INFO_SHIFT		26
-#define   VOLTAGE_INFO_0_85V		(0 << 24)
-#define   VOLTAGE_INFO_0_95V		(1 << 24)
-#define   VOLTAGE_INFO_1_05V		(2 << 24)
-#define   VOLTAGE_INFO_MASK		(3 << 24)
-#define   VOLTAGE_INFO_SHIFT		24
-#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
-#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
-
-#define _ICL_PORT_COMP_DW0_A		0x162100
-#define _ICL_PORT_COMP_DW0_B		0x6C100
-#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
-							 _ICL_PORT_COMP_DW0_B)
-#define _ICL_PORT_COMP_DW1_A		0x162104
-#define _ICL_PORT_COMP_DW1_B		0x6C104
-#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
-							 _ICL_PORT_COMP_DW1_B)
-#define _ICL_PORT_COMP_DW3_A		0x16210C
-#define _ICL_PORT_COMP_DW3_B		0x6C10C
-#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
-							 _ICL_PORT_COMP_DW3_B)
-#define _ICL_PORT_COMP_DW9_A		0x162124
-#define _ICL_PORT_COMP_DW9_B		0x6C124
-#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
-							 _ICL_PORT_COMP_DW9_B)
-#define _ICL_PORT_COMP_DW10_A		0x162128
-#define _ICL_PORT_COMP_DW10_B		0x6C128
-#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_COMP_DW10_A, \
-						   _ICL_PORT_COMP_DW10_B)
-
 /* ICL PHY DFLEX registers */
 #define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
 #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
-- 
2.16.2

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Re: [PATCH 6/8] drm/i915/icl: Combine all port/combophy macros at one place

[Rodrigo Vivi]

On Wed, Oct 03, 2018 at 12:52:01PM +0530, Mahesh Kumar wrote:
> This patch combines CNL/ICL specific port/combophy macros together
> at one location. This is prework for patches later in series where
> new macros to find port/combophy register will be introduced.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++-------------------
>  1 file changed, 73 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 27e650fe591b..e3ac65f5aa81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1631,14 +1631,42 @@ enum i915_power_well_id {
>  #define   PHY_RESERVED			(1 << 7)
>  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
>  
> -#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> -#define   CL_POWER_DOWN_ENABLE		(1 << 4)
> -#define   SUS_CLOCK_CONFIG		(3 << 0)
> +#define _PORT_CL1CM_DW9_A		0x162024
> +#define _PORT_CL1CM_DW9_BC		0x6C024
> +#define   IREF0RC_OFFSET_SHIFT		8
> +#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
> +
> +#define _PORT_CL1CM_DW10_A		0x162028
> +#define _PORT_CL1CM_DW10_BC		0x6C028
> +#define   IREF1RC_OFFSET_SHIFT		8
> +#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> +#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
> +
> +#define _PORT_CL1CM_DW28_A		0x162070
> +#define _PORT_CL1CM_DW28_BC		0x6C070
> +#define   OCL1_POWER_DOWN_EN		(1 << 23)
> +#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
> +#define   SUS_CLK_CONFIG		0x3
> +#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
> +
> +#define _PORT_CL1CM_DW30_A		0x162078
> +#define _PORT_CL1CM_DW30_BC		0x6C078
> +#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> +#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> +
> +/*
> + * CNL/ICL Port/COMBO-PHY Registers
> + */
> +/* CNL/ICL Port CL_DW registers */
> +#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
>  

We need to remove this empty line here or it seems the bits for this reg is not
defined.

The rest looks good to me,

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



>  #define _ICL_PORT_CL_DW5_A	0x162014
>  #define _ICL_PORT_CL_DW5_B	0x6C014
>  #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
>  						 _ICL_PORT_CL_DW5_B)
> +#define   CL_POWER_DOWN_ENABLE		(1 << 4)
> +#define   SUS_CLOCK_CONFIG		(3 << 0)
>  
>  #define _CNL_PORT_CL_DW10_A		0x162028
>  #define _ICL_PORT_CL_DW10_B		0x6c028
> @@ -1660,18 +1688,6 @@ enum i915_power_well_id {
>  #define  PWR_DOWN_LN_MASK		(0xf << 4)
>  #define  PWR_DOWN_LN_SHIFT		4
>  
> -#define _PORT_CL1CM_DW9_A		0x162024
> -#define _PORT_CL1CM_DW9_BC		0x6C024
> -#define   IREF0RC_OFFSET_SHIFT		8
> -#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
> -
> -#define _PORT_CL1CM_DW10_A		0x162028
> -#define _PORT_CL1CM_DW10_BC		0x6C028
> -#define   IREF1RC_OFFSET_SHIFT		8
> -#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
> -
>  #define _ICL_PORT_CL_DW12_A		0x162030
>  #define _ICL_PORT_CL_DW12_B		0x6C030
>  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> @@ -1679,18 +1695,49 @@ enum i915_power_well_id {
>  						   _ICL_PORT_CL_DW12_A, \
>  						   _ICL_PORT_CL_DW12_B)
>  
> -#define _PORT_CL1CM_DW28_A		0x162070
> -#define _PORT_CL1CM_DW28_BC		0x6C070
> -#define   OCL1_POWER_DOWN_EN		(1 << 23)
> -#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
> -#define   SUS_CLK_CONFIG		0x3
> -#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
> +/* CNL/ICL Port COMP_DW registers */
> +#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> +#define _ICL_PORT_COMP_DW0_A		0x162100
> +#define _ICL_PORT_COMP_DW0_B		0x6C100
> +#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> +							 _ICL_PORT_COMP_DW0_B)
> +#define   COMP_INIT			(1 << 31)
>  
> -#define _PORT_CL1CM_DW30_A		0x162078
> -#define _PORT_CL1CM_DW30_BC		0x6C078
> -#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> -#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> +#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> +#define _ICL_PORT_COMP_DW1_A		0x162104
> +#define _ICL_PORT_COMP_DW1_B		0x6C104
> +#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> +							 _ICL_PORT_COMP_DW1_B)
> +#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> +#define _ICL_PORT_COMP_DW3_A		0x16210C
> +#define _ICL_PORT_COMP_DW3_B		0x6C10C
> +#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> +							 _ICL_PORT_COMP_DW3_B)
> +#define   PROCESS_INFO_DOT_0		(0 << 26)
> +#define   PROCESS_INFO_DOT_1		(1 << 26)
> +#define   PROCESS_INFO_DOT_4		(2 << 26)
> +#define   PROCESS_INFO_MASK		(7 << 26)
> +#define   PROCESS_INFO_SHIFT		26
> +#define   VOLTAGE_INFO_0_85V		(0 << 24)
> +#define   VOLTAGE_INFO_0_95V		(1 << 24)
> +#define   VOLTAGE_INFO_1_05V		(2 << 24)
> +#define   VOLTAGE_INFO_MASK		(3 << 24)
> +#define   VOLTAGE_INFO_SHIFT		24
>  
> +#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> +#define _ICL_PORT_COMP_DW9_A		0x162124
> +#define _ICL_PORT_COMP_DW9_B		0x6C124
> +#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> +							 _ICL_PORT_COMP_DW9_B)
> +
> +#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> +#define _ICL_PORT_COMP_DW10_A		0x162128
> +#define _ICL_PORT_COMP_DW10_B		0x6C128
> +#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> +						   _ICL_PORT_COMP_DW10_A, \
> +						   _ICL_PORT_COMP_DW10_B)
> +
> +/* CNL/ICL Port PCS registers */
>  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
>  #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
>  #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> @@ -1734,7 +1781,7 @@ enum i915_power_well_id {
>  						   _ICL_PORT_PCS_DW1_AUX_B)
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
> -/* CNL Port TX registers */
> +/* CNL/ICL Port TX registers */
>  #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
>  #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
>  #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
> @@ -2054,45 +2101,6 @@ enum i915_power_well_id {
>  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
> -#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> -#define   COMP_INIT			(1 << 31)
> -#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> -#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> -#define   PROCESS_INFO_DOT_0		(0 << 26)
> -#define   PROCESS_INFO_DOT_1		(1 << 26)
> -#define   PROCESS_INFO_DOT_4		(2 << 26)
> -#define   PROCESS_INFO_MASK		(7 << 26)
> -#define   PROCESS_INFO_SHIFT		26
> -#define   VOLTAGE_INFO_0_85V		(0 << 24)
> -#define   VOLTAGE_INFO_0_95V		(1 << 24)
> -#define   VOLTAGE_INFO_1_05V		(2 << 24)
> -#define   VOLTAGE_INFO_MASK		(3 << 24)
> -#define   VOLTAGE_INFO_SHIFT		24
> -#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> -#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> -
> -#define _ICL_PORT_COMP_DW0_A		0x162100
> -#define _ICL_PORT_COMP_DW0_B		0x6C100
> -#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> -							 _ICL_PORT_COMP_DW0_B)
> -#define _ICL_PORT_COMP_DW1_A		0x162104
> -#define _ICL_PORT_COMP_DW1_B		0x6C104
> -#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> -							 _ICL_PORT_COMP_DW1_B)
> -#define _ICL_PORT_COMP_DW3_A		0x16210C
> -#define _ICL_PORT_COMP_DW3_B		0x6C10C
> -#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> -							 _ICL_PORT_COMP_DW3_B)
> -#define _ICL_PORT_COMP_DW9_A		0x162124
> -#define _ICL_PORT_COMP_DW9_B		0x6C124
> -#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> -							 _ICL_PORT_COMP_DW9_B)
> -#define _ICL_PORT_COMP_DW10_A		0x162128
> -#define _ICL_PORT_COMP_DW10_B		0x6C128
> -#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_COMP_DW10_A, \
> -						   _ICL_PORT_COMP_DW10_B)
> -
>  /* ICL PHY DFLEX registers */
>  #define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
>  #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
> -- 
> 2.16.2
> 
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[PATCH v2] drm/i915/icl: Combine all port/combophy macros at one place

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch combines CNL/ICL specific port/combophy macros together
at one location. This is prework for patches later in series where
new macros to find port/combophy register will be introduced.

v2: remove wrong empty line

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 137 +++++++++++++++++---------------
 1 file changed, 72 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 20785417953d..9055539a241b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1631,14 +1631,41 @@ enum i915_power_well_id {
 #define   PHY_RESERVED			(1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
 
-#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
-#define   CL_POWER_DOWN_ENABLE		(1 << 4)
-#define   SUS_CLOCK_CONFIG		(3 << 0)
+#define _PORT_CL1CM_DW9_A		0x162024
+#define _PORT_CL1CM_DW9_BC		0x6C024
+#define   IREF0RC_OFFSET_SHIFT		8
+#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
 
+#define _PORT_CL1CM_DW10_A		0x162028
+#define _PORT_CL1CM_DW10_BC		0x6C028
+#define   IREF1RC_OFFSET_SHIFT		8
+#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
+#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
+
+#define _PORT_CL1CM_DW28_A		0x162070
+#define _PORT_CL1CM_DW28_BC		0x6C070
+#define   OCL1_POWER_DOWN_EN		(1 << 23)
+#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
+#define   SUS_CLK_CONFIG		0x3
+#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
+
+#define _PORT_CL1CM_DW30_A		0x162078
+#define _PORT_CL1CM_DW30_BC		0x6C078
+#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
+#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
+
+/*
+ * CNL/ICL Port/COMBO-PHY Registers
+ */
+/* CNL/ICL Port CL_DW registers */
+#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
 #define _ICL_PORT_CL_DW5_A	0x162014
 #define _ICL_PORT_CL_DW5_B	0x6C014
 #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
 						 _ICL_PORT_CL_DW5_B)
+#define   CL_POWER_DOWN_ENABLE		(1 << 4)
+#define   SUS_CLOCK_CONFIG		(3 << 0)
 
 #define _CNL_PORT_CL_DW10_A		0x162028
 #define _ICL_PORT_CL_DW10_B		0x6c028
@@ -1660,18 +1687,6 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
 
-#define _PORT_CL1CM_DW9_A		0x162024
-#define _PORT_CL1CM_DW9_BC		0x6C024
-#define   IREF0RC_OFFSET_SHIFT		8
-#define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
-
-#define _PORT_CL1CM_DW10_A		0x162028
-#define _PORT_CL1CM_DW10_BC		0x6C028
-#define   IREF1RC_OFFSET_SHIFT		8
-#define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
-
 #define _ICL_PORT_CL_DW12_A		0x162030
 #define _ICL_PORT_CL_DW12_B		0x6C030
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
@@ -1679,18 +1694,49 @@ enum i915_power_well_id {
 						   _ICL_PORT_CL_DW12_A, \
 						   _ICL_PORT_CL_DW12_B)
 
-#define _PORT_CL1CM_DW28_A		0x162070
-#define _PORT_CL1CM_DW28_BC		0x6C070
-#define   OCL1_POWER_DOWN_EN		(1 << 23)
-#define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
-#define   SUS_CLK_CONFIG		0x3
-#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
+/* CNL/ICL Port COMP_DW registers */
+#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
+#define _ICL_PORT_COMP_DW0_A		0x162100
+#define _ICL_PORT_COMP_DW0_B		0x6C100
+#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
+							 _ICL_PORT_COMP_DW0_B)
+#define   COMP_INIT			(1 << 31)
 
-#define _PORT_CL1CM_DW30_A		0x162078
-#define _PORT_CL1CM_DW30_BC		0x6C078
-#define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
-#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
+#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
+#define _ICL_PORT_COMP_DW1_A		0x162104
+#define _ICL_PORT_COMP_DW1_B		0x6C104
+#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
+							 _ICL_PORT_COMP_DW1_B)
+#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
+#define _ICL_PORT_COMP_DW3_A		0x16210C
+#define _ICL_PORT_COMP_DW3_B		0x6C10C
+#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
+							 _ICL_PORT_COMP_DW3_B)
+#define   PROCESS_INFO_DOT_0		(0 << 26)
+#define   PROCESS_INFO_DOT_1		(1 << 26)
+#define   PROCESS_INFO_DOT_4		(2 << 26)
+#define   PROCESS_INFO_MASK		(7 << 26)
+#define   PROCESS_INFO_SHIFT		26
+#define   VOLTAGE_INFO_0_85V		(0 << 24)
+#define   VOLTAGE_INFO_0_95V		(1 << 24)
+#define   VOLTAGE_INFO_1_05V		(2 << 24)
+#define   VOLTAGE_INFO_MASK		(3 << 24)
+#define   VOLTAGE_INFO_SHIFT		24
+
+#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
+#define _ICL_PORT_COMP_DW9_A		0x162124
+#define _ICL_PORT_COMP_DW9_B		0x6C124
+#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
+							 _ICL_PORT_COMP_DW9_B)
+
+#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
+#define _ICL_PORT_COMP_DW10_A		0x162128
+#define _ICL_PORT_COMP_DW10_B		0x6C128
+#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
+						   _ICL_PORT_COMP_DW10_A, \
+						   _ICL_PORT_COMP_DW10_B)
 
+/* CNL/ICL Port PCS registers */
 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
 #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
 #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
@@ -1734,7 +1780,7 @@ enum i915_power_well_id {
 						   _ICL_PORT_PCS_DW1_AUX_B)
 #define   COMMON_KEEPER_EN		(1 << 26)
 
-/* CNL Port TX registers */
+/* CNL/ICL Port TX registers */
 #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
 #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
 #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
@@ -2054,45 +2100,6 @@ enum i915_power_well_id {
 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
-#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
-#define   COMP_INIT			(1 << 31)
-#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
-#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
-#define   PROCESS_INFO_DOT_0		(0 << 26)
-#define   PROCESS_INFO_DOT_1		(1 << 26)
-#define   PROCESS_INFO_DOT_4		(2 << 26)
-#define   PROCESS_INFO_MASK		(7 << 26)
-#define   PROCESS_INFO_SHIFT		26
-#define   VOLTAGE_INFO_0_85V		(0 << 24)
-#define   VOLTAGE_INFO_0_95V		(1 << 24)
-#define   VOLTAGE_INFO_1_05V		(2 << 24)
-#define   VOLTAGE_INFO_MASK		(3 << 24)
-#define   VOLTAGE_INFO_SHIFT		24
-#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
-#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
-
-#define _ICL_PORT_COMP_DW0_A		0x162100
-#define _ICL_PORT_COMP_DW0_B		0x6C100
-#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
-							 _ICL_PORT_COMP_DW0_B)
-#define _ICL_PORT_COMP_DW1_A		0x162104
-#define _ICL_PORT_COMP_DW1_B		0x6C104
-#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
-							 _ICL_PORT_COMP_DW1_B)
-#define _ICL_PORT_COMP_DW3_A		0x16210C
-#define _ICL_PORT_COMP_DW3_B		0x6C10C
-#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
-							 _ICL_PORT_COMP_DW3_B)
-#define _ICL_PORT_COMP_DW9_A		0x162124
-#define _ICL_PORT_COMP_DW9_B		0x6C124
-#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
-							 _ICL_PORT_COMP_DW9_B)
-#define _ICL_PORT_COMP_DW10_A		0x162128
-#define _ICL_PORT_COMP_DW10_B		0x6C128
-#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_COMP_DW10_A, \
-						   _ICL_PORT_COMP_DW10_B)
-
 /* ICL PHY DFLEX registers */
 #define PORT_TX_DFLEXDPMLE1		_MMIO(0x1638C0)
 #define   DFLEXDPMLE1_DPMLETC_MASK(n)	(0xf << (4 * (n)))
-- 
2.19.1.1.g8c3cf03f71

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers

[Mahesh Kumar]

From: Lucas De Marchi <lucas.demarchi@intel.com>

combo-phy register instances are at same offset from base for each
combo-phy port, i.e.

Port A base offset: 0x16200
Port B base offset: 0x6C000

All the other addresses for both ports can be derived by calculating
offset to these base addresses.

PORT_CL_DW_OFFSET	0x0
PORT_CL_DW<x>		0 + x * 4

PORT_COMP_OFFSET	0x100
PORT_COMP_DW<x>		0x100 + x * 4

PORT_PCS_AUX_OFFSET     0x300
PORT_PCS_GRP_OFFSET     0x600
PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100

PORT_TX_AUX_OFFSET      0x380
PORT_TX_GRP_OFFSET      0x680
PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100

And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.

Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 154 ++++++++++++++--------------------------
 1 file changed, 54 insertions(+), 100 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e3ac65f5aa81..eaf3e0d529d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,21 +1658,21 @@ enum i915_power_well_id {
 /*
  * CNL/ICL Port/COMBO-PHY Registers
  */
+#define _ICL_COMBOPHY_A			0x162000
+#define _ICL_COMBOPHY_B			0x6C000
+#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
+					      _ICL_COMBOPHY_B)
+
 /* CNL/ICL Port CL_DW registers */
-#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
+#define _ICL_PORT_CL_DW(port, dw)	(_ICL_COMBOPHY(port) + \
+					 4 * (dw))
 
-#define _ICL_PORT_CL_DW5_A	0x162014
-#define _ICL_PORT_CL_DW5_B	0x6C014
-#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
-						 _ICL_PORT_CL_DW5_B)
+#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
+#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(port, 5))
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
 #define   SUS_CLOCK_CONFIG		(3 << 0)
 
-#define _CNL_PORT_CL_DW10_A		0x162028
-#define _ICL_PORT_CL_DW10_B		0x6c028
-#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
-						   _CNL_PORT_CL_DW10_A, \
-						   _ICL_PORT_CL_DW10_B)
+#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(port, 10))
 #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
@@ -1688,31 +1688,23 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
 
-#define _ICL_PORT_CL_DW12_A		0x162030
-#define _ICL_PORT_CL_DW12_B		0x6C030
+#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(port, 12))
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
-#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
-						   _ICL_PORT_CL_DW12_A, \
-						   _ICL_PORT_CL_DW12_B)
 
 /* CNL/ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP			0x100
+#define _ICL_PORT_COMP_DW(port, dw)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_COMP + 4 * (dw))
+
 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
-#define _ICL_PORT_COMP_DW0_A		0x162100
-#define _ICL_PORT_COMP_DW0_B		0x6C100
-#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
-							 _ICL_PORT_COMP_DW0_B)
+#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(port, 0))
 #define   COMP_INIT			(1 << 31)
 
 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
-#define _ICL_PORT_COMP_DW1_A		0x162104
-#define _ICL_PORT_COMP_DW1_B		0x6C104
-#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
-							 _ICL_PORT_COMP_DW1_B)
+#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(port, 1))
+
 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
-#define _ICL_PORT_COMP_DW3_A		0x16210C
-#define _ICL_PORT_COMP_DW3_B		0x6C10C
-#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
-							 _ICL_PORT_COMP_DW3_B)
+#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(port, 3))
 #define   PROCESS_INFO_DOT_0		(0 << 26)
 #define   PROCESS_INFO_DOT_1		(1 << 26)
 #define   PROCESS_INFO_DOT_4		(2 << 26)
@@ -1725,17 +1717,10 @@ enum i915_power_well_id {
 #define   VOLTAGE_INFO_SHIFT		24
 
 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
-#define _ICL_PORT_COMP_DW9_A		0x162124
-#define _ICL_PORT_COMP_DW9_B		0x6C124
-#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
-							 _ICL_PORT_COMP_DW9_B)
+#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW((port), 9))
 
 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
-#define _ICL_PORT_COMP_DW10_A		0x162128
-#define _ICL_PORT_COMP_DW10_B		0x6C128
-#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_COMP_DW10_A, \
-						   _ICL_PORT_COMP_DW10_B)
+#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW((port), 10))
 
 /* CNL/ICL Port PCS registers */
 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
@@ -1755,7 +1740,6 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_GRP_D, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
 						    _CNL_PORT_PCS_DW1_GRP_F))
-
 #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_B, \
@@ -1764,21 +1748,18 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_F))
 
-#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
-#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
-#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
-#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
-#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
-#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
-#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
-						   _ICL_PORT_PCS_DW1_GRP_A, \
-						   _ICL_PORT_PCS_DW1_GRP_B)
-#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_PCS_DW1_LN0_A, \
-						   _ICL_PORT_PCS_DW1_LN0_B)
-#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_PCS_DW1_AUX_A, \
-						   _ICL_PORT_PCS_DW1_AUX_B)
+#define _ICL_PORT_PCS_AUX		0x300
+#define _ICL_PORT_PCS_GRP		0x600
+#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
+#define _ICL_PORT_PCS_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_PCS_AUX + 4 * (dw))
+#define _ICL_PORT_PCS_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_PCS_GRP + 4 * (dw))
+#define _ICL_PORT_PCS_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
+					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
+#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(port, 1))
+#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(port, 1))
+#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(port, 1, 0))
 #define   COMMON_KEEPER_EN		(1 << 26)
 
 /* CNL/ICL Port TX registers */
@@ -1809,23 +1790,22 @@ enum i915_power_well_id {
 					       _CNL_PORT_TX_F_LN0_OFFSET) + \
 					       4 * (dw))
 
+#define _ICL_PORT_TX_AUX		0x380
+#define _ICL_PORT_TX_GRP		0x680
+#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
+
+#define _ICL_PORT_TX_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_TX_AUX + 4 * (dw))
+#define _ICL_PORT_TX_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_TX_GRP + 4 * (dw))
+#define _ICL_PORT_TX_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
+					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
+
 #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
 #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
-#define _ICL_PORT_TX_DW2_GRP_A		0x162688
-#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
-#define _ICL_PORT_TX_DW2_LN0_A		0x162888
-#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
-#define _ICL_PORT_TX_DW2_AUX_A		0x162388
-#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
-#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_GRP_A, \
-						   _ICL_PORT_TX_DW2_GRP_B)
-#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_LN0_A, \
-						   _ICL_PORT_TX_DW2_LN0_B)
-#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_AUX_A, \
-						   _ICL_PORT_TX_DW2_AUX_B)
+#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 2))
+#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 2))
+#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 2, 0))
 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK		(1 << 15)
 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
@@ -1842,24 +1822,10 @@ enum i915_power_well_id {
 #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
 					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
 						    _CNL_PORT_TX_DW4_LN0_AE)))
-#define _ICL_PORT_TX_DW4_GRP_A		0x162690
-#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
-#define _ICL_PORT_TX_DW4_LN0_A		0x162890
-#define _ICL_PORT_TX_DW4_LN1_A		0x162990
-#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
-#define _ICL_PORT_TX_DW4_AUX_A		0x162390
-#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
-#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW4_GRP_A, \
-						   _ICL_PORT_TX_DW4_GRP_B)
-#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
-						   _ICL_PORT_TX_DW4_LN0_A, \
-						   _ICL_PORT_TX_DW4_LN0_B) + \
-					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
-						      _ICL_PORT_TX_DW4_LN0_A)))
-#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW4_AUX_A, \
-						   _ICL_PORT_TX_DW4_AUX_B)
+#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 4))
+#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 4))
+#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, 0))
+#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, ln))
 #define   LOADGEN_SELECT		(1 << 31)
 #define   POST_CURSOR_1(x)		((x) << 12)
 #define   POST_CURSOR_1_MASK		(0x3F << 12)
@@ -1870,21 +1836,9 @@ enum i915_power_well_id {
 
 #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
 #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
-#define _ICL_PORT_TX_DW5_GRP_A		0x162694
-#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
-#define _ICL_PORT_TX_DW5_LN0_A		0x162894
-#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
-#define _ICL_PORT_TX_DW5_AUX_A		0x162394
-#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
-#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_GRP_A, \
-						   _ICL_PORT_TX_DW5_GRP_B)
-#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_LN0_A, \
-						   _ICL_PORT_TX_DW5_LN0_B)
-#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_AUX_A, \
-						   _ICL_PORT_TX_DW5_AUX_B)
+#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 5))
+#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 5))
+#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 5, 0))
 #define   TX_TRAINING_EN		(1 << 31)
 #define   TAP2_DISABLE			(1 << 30)
 #define   TAP3_DISABLE			(1 << 29)
-- 
2.16.2

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Re: [PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers

[Rodrigo Vivi]

On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> combo-phy register instances are at same offset from base for each
> combo-phy port, i.e.
> 
> Port A base offset: 0x16200
> Port B base offset: 0x6C000
> 
> All the other addresses for both ports can be derived by calculating
> offset to these base addresses.
> 
> PORT_CL_DW_OFFSET	0x0
> PORT_CL_DW<x>		0 + x * 4
> 
> PORT_COMP_OFFSET	0x100
> PORT_COMP_DW<x>		0x100 + x * 4
> 
> PORT_PCS_AUX_OFFSET     0x300
> PORT_PCS_GRP_OFFSET     0x600
> PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100
> 
> PORT_TX_AUX_OFFSET      0x380
> PORT_TX_GRP_OFFSET      0x680
> PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100

well, in the past I was in favor of trying to find
logic and simplify as much as possible the register offsets and bits.

However nowadays I'm more inclined to keep them explicit for some
reasons.

1. Another developer when adding some workaround later might
search the code for the reg offset, not finding and adding it again.
In this case the risk is minimal because it is only a risk of
duplicating the offset definition.

2. HW Architects when planing to remove some bits consult us
to see the impact and I always get myself searching for the offsets.
In this case the risk is higher because if we can't find the hidden
offset we might underestimate the impact on a future hw generation.

3. I'm checking to see if there are better ways to get
spec changes to notify us that we have to change something.
It would be harder to parse, but I know it is possible.

Well, maybe a tool for 3 could already answer the item above
in a automated and more reliable way... But while we don't have
such tool maybe it is better to keep explicit.

But I'm not blocking or anything like that. I'm just brainstorming
some points here from my view on this.

another detail below:

> 
> And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
> 
> Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 154 ++++++++++++++--------------------------
>  1 file changed, 54 insertions(+), 100 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e3ac65f5aa81..eaf3e0d529d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1658,21 +1658,21 @@ enum i915_power_well_id {
>  /*
>   * CNL/ICL Port/COMBO-PHY Registers
>   */
> +#define _ICL_COMBOPHY_A			0x162000
> +#define _ICL_COMBOPHY_B			0x6C000
> +#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> +					      _ICL_COMBOPHY_B)
> +
>  /* CNL/ICL Port CL_DW registers */
> -#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
> +#define _ICL_PORT_CL_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 4 * (dw))

probably better if inverted DW(dw, port)
because reg definition is DW#dw_#port and I got
confused when reviewing items below...

>  
> -#define _ICL_PORT_CL_DW5_A	0x162014
> -#define _ICL_PORT_CL_DW5_B	0x6C014
> -#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> -						 _ICL_PORT_CL_DW5_B)
> +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> +#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(port, 5))
>  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
>  #define   SUS_CLOCK_CONFIG		(3 << 0)
>  
> -#define _CNL_PORT_CL_DW10_A		0x162028
> -#define _ICL_PORT_CL_DW10_B		0x6c028
> -#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> -						   _CNL_PORT_CL_DW10_A, \
> -						   _ICL_PORT_CL_DW10_B)
> +#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(port, 10))
>  #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
>  #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
>  #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> @@ -1688,31 +1688,23 @@ enum i915_power_well_id {
>  #define  PWR_DOWN_LN_MASK		(0xf << 4)
>  #define  PWR_DOWN_LN_SHIFT		4
>  
> -#define _ICL_PORT_CL_DW12_A		0x162030
> -#define _ICL_PORT_CL_DW12_B		0x6C030
> +#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(port, 12))
>  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> -#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
> -						   _ICL_PORT_CL_DW12_A, \
> -						   _ICL_PORT_CL_DW12_B)
>  
>  /* CNL/ICL Port COMP_DW registers */
> +#define _ICL_PORT_COMP			0x100
> +#define _ICL_PORT_COMP_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_COMP + 4 * (dw))
> +
>  #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> -#define _ICL_PORT_COMP_DW0_A		0x162100
> -#define _ICL_PORT_COMP_DW0_B		0x6C100
> -#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> -							 _ICL_PORT_COMP_DW0_B)
> +#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(port, 0))
>  #define   COMP_INIT			(1 << 31)
>  
>  #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> -#define _ICL_PORT_COMP_DW1_A		0x162104
> -#define _ICL_PORT_COMP_DW1_B		0x6C104
> -#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> -							 _ICL_PORT_COMP_DW1_B)
> +#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(port, 1))
> +
>  #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> -#define _ICL_PORT_COMP_DW3_A		0x16210C
> -#define _ICL_PORT_COMP_DW3_B		0x6C10C
> -#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> -							 _ICL_PORT_COMP_DW3_B)
> +#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(port, 3))
>  #define   PROCESS_INFO_DOT_0		(0 << 26)
>  #define   PROCESS_INFO_DOT_1		(1 << 26)
>  #define   PROCESS_INFO_DOT_4		(2 << 26)
> @@ -1725,17 +1717,10 @@ enum i915_power_well_id {
>  #define   VOLTAGE_INFO_SHIFT		24
>  
>  #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> -#define _ICL_PORT_COMP_DW9_A		0x162124
> -#define _ICL_PORT_COMP_DW9_B		0x6C124
> -#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> -							 _ICL_PORT_COMP_DW9_B)
> +#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW((port), 9))
>  
>  #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> -#define _ICL_PORT_COMP_DW10_A		0x162128
> -#define _ICL_PORT_COMP_DW10_B		0x6C128
> -#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_COMP_DW10_A, \
> -						   _ICL_PORT_COMP_DW10_B)
> +#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW((port), 10))
>  
>  /* CNL/ICL Port PCS registers */
>  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> @@ -1755,7 +1740,6 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_GRP_D, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
>  						    _CNL_PORT_PCS_DW1_GRP_F))
> -
>  #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_B, \
> @@ -1764,21 +1748,18 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_F))
>  
> -#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
> -#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
> -#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
> -#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> -#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
> -#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
> -#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
> -						   _ICL_PORT_PCS_DW1_GRP_A, \
> -						   _ICL_PORT_PCS_DW1_GRP_B)
> -#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_PCS_DW1_LN0_A, \
> -						   _ICL_PORT_PCS_DW1_LN0_B)
> -#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_PCS_DW1_AUX_A, \
> -						   _ICL_PORT_PCS_DW1_AUX_B)
> +#define _ICL_PORT_PCS_AUX		0x300
> +#define _ICL_PORT_PCS_GRP		0x600
> +#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
> +#define _ICL_PORT_PCS_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_PCS_AUX + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_PCS_GRP + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> +					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(port, 1))
> +#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(port, 1))
> +#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(port, 1, 0))
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
>  /* CNL/ICL Port TX registers */
> @@ -1809,23 +1790,22 @@ enum i915_power_well_id {
>  					       _CNL_PORT_TX_F_LN0_OFFSET) + \
>  					       4 * (dw))
>  
> +#define _ICL_PORT_TX_AUX		0x380
> +#define _ICL_PORT_TX_GRP		0x680
> +#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> +
> +#define _ICL_PORT_TX_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_TX_AUX + 4 * (dw))
> +#define _ICL_PORT_TX_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_TX_GRP + 4 * (dw))
> +#define _ICL_PORT_TX_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> +					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
> +
>  #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
>  #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> -#define _ICL_PORT_TX_DW2_GRP_A		0x162688
> -#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
> -#define _ICL_PORT_TX_DW2_LN0_A		0x162888
> -#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> -#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> -#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
> -#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_GRP_A, \
> -						   _ICL_PORT_TX_DW2_GRP_B)
> -#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_LN0_A, \
> -						   _ICL_PORT_TX_DW2_LN0_B)
> -#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_AUX_A, \
> -						   _ICL_PORT_TX_DW2_AUX_B)
> +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 2))
> +#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 2))
> +#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 2, 0))
>  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
>  #define   SWING_SEL_UPPER_MASK		(1 << 15)
>  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> @@ -1842,24 +1822,10 @@ enum i915_power_well_id {
>  #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
>  					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
>  						    _CNL_PORT_TX_DW4_LN0_AE)))
> -#define _ICL_PORT_TX_DW4_GRP_A		0x162690
> -#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
> -#define _ICL_PORT_TX_DW4_LN0_A		0x162890
> -#define _ICL_PORT_TX_DW4_LN1_A		0x162990
> -#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> -#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> -#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
> -#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW4_GRP_A, \
> -						   _ICL_PORT_TX_DW4_GRP_B)
> -#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
> -						   _ICL_PORT_TX_DW4_LN0_A, \
> -						   _ICL_PORT_TX_DW4_LN0_B) + \
> -					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
> -						      _ICL_PORT_TX_DW4_LN0_A)))
> -#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW4_AUX_A, \
> -						   _ICL_PORT_TX_DW4_AUX_B)
> +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 4))
> +#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 4))
> +#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, 0))
> +#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, ln))
>  #define   LOADGEN_SELECT		(1 << 31)
>  #define   POST_CURSOR_1(x)		((x) << 12)
>  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> @@ -1870,21 +1836,9 @@ enum i915_power_well_id {
>  
>  #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
>  #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
> -#define _ICL_PORT_TX_DW5_GRP_A		0x162694
> -#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
> -#define _ICL_PORT_TX_DW5_LN0_A		0x162894
> -#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> -#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> -#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
> -#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_GRP_A, \
> -						   _ICL_PORT_TX_DW5_GRP_B)
> -#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_LN0_A, \
> -						   _ICL_PORT_TX_DW5_LN0_B)
> -#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_AUX_A, \
> -						   _ICL_PORT_TX_DW5_AUX_B)
> +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 5))
> +#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 5))
> +#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 5, 0))
>  #define   TX_TRAINING_EN		(1 << 31)
>  #define   TAP2_DISABLE			(1 << 30)
>  #define   TAP3_DISABLE			(1 << 29)
> -- 
> 2.16.2
> 
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Re: [PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers

[Lucas De Marchi]

On Fri, Oct 12, 2018 at 03:25:37PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> > From: Lucas De Marchi <lucas.demarchi@intel.com>
> > 
> > combo-phy register instances are at same offset from base for each
> > combo-phy port, i.e.
> > 
> > Port A base offset: 0x16200
> > Port B base offset: 0x6C000
> > 
> > All the other addresses for both ports can be derived by calculating
> > offset to these base addresses.
> > 
> > PORT_CL_DW_OFFSET	0x0
> > PORT_CL_DW<x>		0 + x * 4
> > 
> > PORT_COMP_OFFSET	0x100
> > PORT_COMP_DW<x>		0x100 + x * 4
> > 
> > PORT_PCS_AUX_OFFSET     0x300
> > PORT_PCS_GRP_OFFSET     0x600
> > PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100
> > 
> > PORT_TX_AUX_OFFSET      0x380
> > PORT_TX_GRP_OFFSET      0x680
> > PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100
> 
> well, in the past I was in favor of trying to find
> logic and simplify as much as possible the register offsets and bits.
> 
> However nowadays I'm more inclined to keep them explicit for some
> reasons.
> 
> 1. Another developer when adding some workaround later might
> search the code for the reg offset, not finding and adding it again.
> In this case the risk is minimal because it is only a risk of
> duplicating the offset definition.
> 
> 2. HW Architects when planing to remove some bits consult us
> to see the impact and I always get myself searching for the offsets.
> In this case the risk is higher because if we can't find the hidden
> offset we might underestimate the impact on a future hw generation.
> 
> 3. I'm checking to see if there are better ways to get
> spec changes to notify us that we have to change something.
> It would be harder to parse, but I know it is possible.
> 
> Well, maybe a tool for 3 could already answer the item above
> in a automated and more reliable way... But while we don't have
> such tool maybe it is better to keep explicit.
> 
> But I'm not blocking or anything like that. I'm just brainstorming
> some points here from my view on this.


I agree with the reasonings, but in this particular case I think it's simpler since
the spec itself is now modular wrt combophy instance. See 29482, although it continues
to define the individual values, this is not always the case.


> 
> another detail below:
> 
> > 
> > And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
> > 
> > Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.
> > 
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 154 ++++++++++++++--------------------------
> >  1 file changed, 54 insertions(+), 100 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e3ac65f5aa81..eaf3e0d529d3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1658,21 +1658,21 @@ enum i915_power_well_id {
> >  /*
> >   * CNL/ICL Port/COMBO-PHY Registers
> >   */
> > +#define _ICL_COMBOPHY_A			0x162000
> > +#define _ICL_COMBOPHY_B			0x6C000
> > +#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> > +					      _ICL_COMBOPHY_B)
> > +
> >  /* CNL/ICL Port CL_DW registers */
> > -#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
> > +#define _ICL_PORT_CL_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 4 * (dw))
> 
> probably better if inverted DW(dw, port)
> because reg definition is DW#dw_#port and I got
> confused when reviewing items below...

ok

thanks
Lucas De Marchi

> 
> >  
> > -#define _ICL_PORT_CL_DW5_A	0x162014
> > -#define _ICL_PORT_CL_DW5_B	0x6C014
> > -#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> > -						 _ICL_PORT_CL_DW5_B)
> > +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> > +#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(port, 5))
> >  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> >  #define   SUS_CLOCK_CONFIG		(3 << 0)
> >  
> > -#define _CNL_PORT_CL_DW10_A		0x162028
> > -#define _ICL_PORT_CL_DW10_B		0x6c028
> > -#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> > -						   _CNL_PORT_CL_DW10_A, \
> > -						   _ICL_PORT_CL_DW10_B)
> > +#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(port, 10))
> >  #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> >  #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> >  #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> > @@ -1688,31 +1688,23 @@ enum i915_power_well_id {
> >  #define  PWR_DOWN_LN_MASK		(0xf << 4)
> >  #define  PWR_DOWN_LN_SHIFT		4
> >  
> > -#define _ICL_PORT_CL_DW12_A		0x162030
> > -#define _ICL_PORT_CL_DW12_B		0x6C030
> > +#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(port, 12))
> >  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> > -#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
> > -						   _ICL_PORT_CL_DW12_A, \
> > -						   _ICL_PORT_CL_DW12_B)
> >  
> >  /* CNL/ICL Port COMP_DW registers */
> > +#define _ICL_PORT_COMP			0x100
> > +#define _ICL_PORT_COMP_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 _ICL_PORT_COMP + 4 * (dw))
> > +
> >  #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> > -#define _ICL_PORT_COMP_DW0_A		0x162100
> > -#define _ICL_PORT_COMP_DW0_B		0x6C100
> > -#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> > -							 _ICL_PORT_COMP_DW0_B)
> > +#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(port, 0))
> >  #define   COMP_INIT			(1 << 31)
> >  
> >  #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> > -#define _ICL_PORT_COMP_DW1_A		0x162104
> > -#define _ICL_PORT_COMP_DW1_B		0x6C104
> > -#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> > -							 _ICL_PORT_COMP_DW1_B)
> > +#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(port, 1))
> > +
> >  #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> > -#define _ICL_PORT_COMP_DW3_A		0x16210C
> > -#define _ICL_PORT_COMP_DW3_B		0x6C10C
> > -#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> > -							 _ICL_PORT_COMP_DW3_B)
> > +#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(port, 3))
> >  #define   PROCESS_INFO_DOT_0		(0 << 26)
> >  #define   PROCESS_INFO_DOT_1		(1 << 26)
> >  #define   PROCESS_INFO_DOT_4		(2 << 26)
> > @@ -1725,17 +1717,10 @@ enum i915_power_well_id {
> >  #define   VOLTAGE_INFO_SHIFT		24
> >  
> >  #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> > -#define _ICL_PORT_COMP_DW9_A		0x162124
> > -#define _ICL_PORT_COMP_DW9_B		0x6C124
> > -#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> > -							 _ICL_PORT_COMP_DW9_B)
> > +#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW((port), 9))
> >  
> >  #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> > -#define _ICL_PORT_COMP_DW10_A		0x162128
> > -#define _ICL_PORT_COMP_DW10_B		0x6C128
> > -#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_COMP_DW10_A, \
> > -						   _ICL_PORT_COMP_DW10_B)
> > +#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW((port), 10))
> >  
> >  /* CNL/ICL Port PCS registers */
> >  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> > @@ -1755,7 +1740,6 @@ enum i915_power_well_id {
> >  						    _CNL_PORT_PCS_DW1_GRP_D, \
> >  						    _CNL_PORT_PCS_DW1_GRP_AE, \
> >  						    _CNL_PORT_PCS_DW1_GRP_F))
> > -
> >  #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
> >  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> >  						    _CNL_PORT_PCS_DW1_LN0_B, \
> > @@ -1764,21 +1748,18 @@ enum i915_power_well_id {
> >  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> >  						    _CNL_PORT_PCS_DW1_LN0_F))
> >  
> > -#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
> > -#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
> > -#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
> > -#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> > -#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
> > -#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
> > -#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
> > -						   _ICL_PORT_PCS_DW1_GRP_A, \
> > -						   _ICL_PORT_PCS_DW1_GRP_B)
> > -#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_PCS_DW1_LN0_A, \
> > -						   _ICL_PORT_PCS_DW1_LN0_B)
> > -#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_PCS_DW1_AUX_A, \
> > -						   _ICL_PORT_PCS_DW1_AUX_B)
> > +#define _ICL_PORT_PCS_AUX		0x300
> > +#define _ICL_PORT_PCS_GRP		0x600
> > +#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
> > +#define _ICL_PORT_PCS_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 _ICL_PORT_PCS_AUX + 4 * (dw))
> > +#define _ICL_PORT_PCS_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 _ICL_PORT_PCS_GRP + 4 * (dw))
> > +#define _ICL_PORT_PCS_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> > +					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> > +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(port, 1))
> > +#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(port, 1))
> > +#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(port, 1, 0))
> >  #define   COMMON_KEEPER_EN		(1 << 26)
> >  
> >  /* CNL/ICL Port TX registers */
> > @@ -1809,23 +1790,22 @@ enum i915_power_well_id {
> >  					       _CNL_PORT_TX_F_LN0_OFFSET) + \
> >  					       4 * (dw))
> >  
> > +#define _ICL_PORT_TX_AUX		0x380
> > +#define _ICL_PORT_TX_GRP		0x680
> > +#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> > +
> > +#define _ICL_PORT_TX_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 _ICL_PORT_TX_AUX + 4 * (dw))
> > +#define _ICL_PORT_TX_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> > +					 _ICL_PORT_TX_GRP + 4 * (dw))
> > +#define _ICL_PORT_TX_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> > +					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
> > +
> >  #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
> >  #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> > -#define _ICL_PORT_TX_DW2_GRP_A		0x162688
> > -#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
> > -#define _ICL_PORT_TX_DW2_LN0_A		0x162888
> > -#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> > -#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> > -#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
> > -#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW2_GRP_A, \
> > -						   _ICL_PORT_TX_DW2_GRP_B)
> > -#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW2_LN0_A, \
> > -						   _ICL_PORT_TX_DW2_LN0_B)
> > -#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW2_AUX_A, \
> > -						   _ICL_PORT_TX_DW2_AUX_B)
> > +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 2))
> > +#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 2))
> > +#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 2, 0))
> >  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
> >  #define   SWING_SEL_UPPER_MASK		(1 << 15)
> >  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> > @@ -1842,24 +1822,10 @@ enum i915_power_well_id {
> >  #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
> >  					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> >  						    _CNL_PORT_TX_DW4_LN0_AE)))
> > -#define _ICL_PORT_TX_DW4_GRP_A		0x162690
> > -#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
> > -#define _ICL_PORT_TX_DW4_LN0_A		0x162890
> > -#define _ICL_PORT_TX_DW4_LN1_A		0x162990
> > -#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> > -#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> > -#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
> > -#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW4_GRP_A, \
> > -						   _ICL_PORT_TX_DW4_GRP_B)
> > -#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
> > -						   _ICL_PORT_TX_DW4_LN0_A, \
> > -						   _ICL_PORT_TX_DW4_LN0_B) + \
> > -					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
> > -						      _ICL_PORT_TX_DW4_LN0_A)))
> > -#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW4_AUX_A, \
> > -						   _ICL_PORT_TX_DW4_AUX_B)
> > +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 4))
> > +#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 4))
> > +#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, 0))
> > +#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, ln))
> >  #define   LOADGEN_SELECT		(1 << 31)
> >  #define   POST_CURSOR_1(x)		((x) << 12)
> >  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> > @@ -1870,21 +1836,9 @@ enum i915_power_well_id {
> >  
> >  #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
> >  #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
> > -#define _ICL_PORT_TX_DW5_GRP_A		0x162694
> > -#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
> > -#define _ICL_PORT_TX_DW5_LN0_A		0x162894
> > -#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> > -#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> > -#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
> > -#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW5_GRP_A, \
> > -						   _ICL_PORT_TX_DW5_GRP_B)
> > -#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW5_LN0_A, \
> > -						   _ICL_PORT_TX_DW5_LN0_B)
> > -#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> > -						   _ICL_PORT_TX_DW5_AUX_A, \
> > -						   _ICL_PORT_TX_DW5_AUX_B)
> > +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 5))
> > +#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 5))
> > +#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 5, 0))
> >  #define   TX_TRAINING_EN		(1 << 31)
> >  #define   TAP2_DISABLE			(1 << 30)
> >  #define   TAP3_DISABLE			(1 << 29)
> > -- 
> > 2.16.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 7/8] drm/i915/icl: Introduce new macros to get combophy registers

[Rodrigo Vivi]

On Fri, Oct 12, 2018 at 03:58:52PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 12, 2018 at 03:25:37PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 03, 2018 at 12:52:02PM +0530, Mahesh Kumar wrote:
> > > From: Lucas De Marchi <lucas.demarchi@intel.com>
> > > 
> > > combo-phy register instances are at same offset from base for each
> > > combo-phy port, i.e.
> > > 
> > > Port A base offset: 0x16200
> > > Port B base offset: 0x6C000
> > > 
> > > All the other addresses for both ports can be derived by calculating
> > > offset to these base addresses.
> > > 
> > > PORT_CL_DW_OFFSET	0x0
> > > PORT_CL_DW<x>		0 + x * 4
> > > 
> > > PORT_COMP_OFFSET	0x100
> > > PORT_COMP_DW<x>		0x100 + x * 4
> > > 
> > > PORT_PCS_AUX_OFFSET     0x300
> > > PORT_PCS_GRP_OFFSET     0x600
> > > PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100
> > > 
> > > PORT_TX_AUX_OFFSET      0x380
> > > PORT_TX_GRP_OFFSET      0x680
> > > PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100
> > 
> > well, in the past I was in favor of trying to find
> > logic and simplify as much as possible the register offsets and bits.
> > 
> > However nowadays I'm more inclined to keep them explicit for some
> > reasons.
> > 
> > 1. Another developer when adding some workaround later might
> > search the code for the reg offset, not finding and adding it again.
> > In this case the risk is minimal because it is only a risk of
> > duplicating the offset definition.
> > 
> > 2. HW Architects when planing to remove some bits consult us
> > to see the impact and I always get myself searching for the offsets.
> > In this case the risk is higher because if we can't find the hidden
> > offset we might underestimate the impact on a future hw generation.
> > 
> > 3. I'm checking to see if there are better ways to get
> > spec changes to notify us that we have to change something.
> > It would be harder to parse, but I know it is possible.
> > 
> > Well, maybe a tool for 3 could already answer the item above
> > in a automated and more reliable way... But while we don't have
> > such tool maybe it is better to keep explicit.
> > 
> > But I'm not blocking or anything like that. I'm just brainstorming
> > some points here from my view on this.
> 
> 
> I agree with the reasonings, but in this particular case I think it's simpler since
> the spec itself is now modular wrt combophy instance. See 29482, although it continues
> to define the individual values, this is not always the case.

hmm... makes sense...

> 
> 
> > 
> > another detail below:
> > 
> > > 
> > > And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
> > > 
> > > Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.
> > > 
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 154 ++++++++++++++--------------------------
> > >  1 file changed, 54 insertions(+), 100 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index e3ac65f5aa81..eaf3e0d529d3 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1658,21 +1658,21 @@ enum i915_power_well_id {
> > >  /*
> > >   * CNL/ICL Port/COMBO-PHY Registers
> > >   */
> > > +#define _ICL_COMBOPHY_A			0x162000
> > > +#define _ICL_COMBOPHY_B			0x6C000
> > > +#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> > > +					      _ICL_COMBOPHY_B)
> > > +
> > >  /* CNL/ICL Port CL_DW registers */
> > > -#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
> > > +#define _ICL_PORT_CL_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 4 * (dw))
> > 
> > probably better if inverted DW(dw, port)
> > because reg definition is DW#dw_#port and I got
> > confused when reviewing items below...
> 
> ok

thanks, with this changed feel free to already add
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> thanks
> Lucas De Marchi
> 
> > 
> > >  
> > > -#define _ICL_PORT_CL_DW5_A	0x162014
> > > -#define _ICL_PORT_CL_DW5_B	0x6C014
> > > -#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> > > -						 _ICL_PORT_CL_DW5_B)
> > > +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> > > +#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(port, 5))
> > >  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> > >  #define   SUS_CLOCK_CONFIG		(3 << 0)
> > >  
> > > -#define _CNL_PORT_CL_DW10_A		0x162028
> > > -#define _ICL_PORT_CL_DW10_B		0x6c028
> > > -#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> > > -						   _CNL_PORT_CL_DW10_A, \
> > > -						   _ICL_PORT_CL_DW10_B)
> > > +#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(port, 10))
> > >  #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> > >  #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> > >  #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> > > @@ -1688,31 +1688,23 @@ enum i915_power_well_id {
> > >  #define  PWR_DOWN_LN_MASK		(0xf << 4)
> > >  #define  PWR_DOWN_LN_SHIFT		4
> > >  
> > > -#define _ICL_PORT_CL_DW12_A		0x162030
> > > -#define _ICL_PORT_CL_DW12_B		0x6C030
> > > +#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(port, 12))
> > >  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> > > -#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
> > > -						   _ICL_PORT_CL_DW12_A, \
> > > -						   _ICL_PORT_CL_DW12_B)
> > >  
> > >  /* CNL/ICL Port COMP_DW registers */
> > > +#define _ICL_PORT_COMP			0x100
> > > +#define _ICL_PORT_COMP_DW(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 _ICL_PORT_COMP + 4 * (dw))
> > > +
> > >  #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> > > -#define _ICL_PORT_COMP_DW0_A		0x162100
> > > -#define _ICL_PORT_COMP_DW0_B		0x6C100
> > > -#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> > > -							 _ICL_PORT_COMP_DW0_B)
> > > +#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(port, 0))
> > >  #define   COMP_INIT			(1 << 31)
> > >  
> > >  #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> > > -#define _ICL_PORT_COMP_DW1_A		0x162104
> > > -#define _ICL_PORT_COMP_DW1_B		0x6C104
> > > -#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> > > -							 _ICL_PORT_COMP_DW1_B)
> > > +#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(port, 1))
> > > +
> > >  #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> > > -#define _ICL_PORT_COMP_DW3_A		0x16210C
> > > -#define _ICL_PORT_COMP_DW3_B		0x6C10C
> > > -#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> > > -							 _ICL_PORT_COMP_DW3_B)
> > > +#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(port, 3))
> > >  #define   PROCESS_INFO_DOT_0		(0 << 26)
> > >  #define   PROCESS_INFO_DOT_1		(1 << 26)
> > >  #define   PROCESS_INFO_DOT_4		(2 << 26)
> > > @@ -1725,17 +1717,10 @@ enum i915_power_well_id {
> > >  #define   VOLTAGE_INFO_SHIFT		24
> > >  
> > >  #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> > > -#define _ICL_PORT_COMP_DW9_A		0x162124
> > > -#define _ICL_PORT_COMP_DW9_B		0x6C124
> > > -#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> > > -							 _ICL_PORT_COMP_DW9_B)
> > > +#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW((port), 9))
> > >  
> > >  #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> > > -#define _ICL_PORT_COMP_DW10_A		0x162128
> > > -#define _ICL_PORT_COMP_DW10_B		0x6C128
> > > -#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_COMP_DW10_A, \
> > > -						   _ICL_PORT_COMP_DW10_B)
> > > +#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW((port), 10))
> > >  
> > >  /* CNL/ICL Port PCS registers */
> > >  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> > > @@ -1755,7 +1740,6 @@ enum i915_power_well_id {
> > >  						    _CNL_PORT_PCS_DW1_GRP_D, \
> > >  						    _CNL_PORT_PCS_DW1_GRP_AE, \
> > >  						    _CNL_PORT_PCS_DW1_GRP_F))
> > > -
> > >  #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
> > >  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > >  						    _CNL_PORT_PCS_DW1_LN0_B, \
> > > @@ -1764,21 +1748,18 @@ enum i915_power_well_id {
> > >  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > >  						    _CNL_PORT_PCS_DW1_LN0_F))
> > >  
> > > -#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
> > > -#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
> > > -#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
> > > -#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> > > -#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
> > > -#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
> > > -#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
> > > -						   _ICL_PORT_PCS_DW1_GRP_A, \
> > > -						   _ICL_PORT_PCS_DW1_GRP_B)
> > > -#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_PCS_DW1_LN0_A, \
> > > -						   _ICL_PORT_PCS_DW1_LN0_B)
> > > -#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_PCS_DW1_AUX_A, \
> > > -						   _ICL_PORT_PCS_DW1_AUX_B)
> > > +#define _ICL_PORT_PCS_AUX		0x300
> > > +#define _ICL_PORT_PCS_GRP		0x600
> > > +#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
> > > +#define _ICL_PORT_PCS_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 _ICL_PORT_PCS_AUX + 4 * (dw))
> > > +#define _ICL_PORT_PCS_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 _ICL_PORT_PCS_GRP + 4 * (dw))
> > > +#define _ICL_PORT_PCS_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> > > +					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> > > +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(port, 1))
> > > +#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(port, 1))
> > > +#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(port, 1, 0))
> > >  #define   COMMON_KEEPER_EN		(1 << 26)
> > >  
> > >  /* CNL/ICL Port TX registers */
> > > @@ -1809,23 +1790,22 @@ enum i915_power_well_id {
> > >  					       _CNL_PORT_TX_F_LN0_OFFSET) + \
> > >  					       4 * (dw))
> > >  
> > > +#define _ICL_PORT_TX_AUX		0x380
> > > +#define _ICL_PORT_TX_GRP		0x680
> > > +#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> > > +
> > > +#define _ICL_PORT_TX_DW_AUX(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 _ICL_PORT_TX_AUX + 4 * (dw))
> > > +#define _ICL_PORT_TX_DW_GRP(port, dw)	(_ICL_COMBOPHY(port) + \
> > > +					 _ICL_PORT_TX_GRP + 4 * (dw))
> > > +#define _ICL_PORT_TX_DW_LN(port, dw, ln) (_ICL_COMBOPHY(port) + \
> > > +					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
> > > +
> > >  #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
> > >  #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> > > -#define _ICL_PORT_TX_DW2_GRP_A		0x162688
> > > -#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
> > > -#define _ICL_PORT_TX_DW2_LN0_A		0x162888
> > > -#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> > > -#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> > > -#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
> > > -#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW2_GRP_A, \
> > > -						   _ICL_PORT_TX_DW2_GRP_B)
> > > -#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW2_LN0_A, \
> > > -						   _ICL_PORT_TX_DW2_LN0_B)
> > > -#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW2_AUX_A, \
> > > -						   _ICL_PORT_TX_DW2_AUX_B)
> > > +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 2))
> > > +#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 2))
> > > +#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 2, 0))
> > >  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
> > >  #define   SWING_SEL_UPPER_MASK		(1 << 15)
> > >  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> > > @@ -1842,24 +1822,10 @@ enum i915_power_well_id {
> > >  #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
> > >  					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> > >  						    _CNL_PORT_TX_DW4_LN0_AE)))
> > > -#define _ICL_PORT_TX_DW4_GRP_A		0x162690
> > > -#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
> > > -#define _ICL_PORT_TX_DW4_LN0_A		0x162890
> > > -#define _ICL_PORT_TX_DW4_LN1_A		0x162990
> > > -#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> > > -#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> > > -#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
> > > -#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW4_GRP_A, \
> > > -						   _ICL_PORT_TX_DW4_GRP_B)
> > > -#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
> > > -						   _ICL_PORT_TX_DW4_LN0_A, \
> > > -						   _ICL_PORT_TX_DW4_LN0_B) + \
> > > -					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
> > > -						      _ICL_PORT_TX_DW4_LN0_A)))
> > > -#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW4_AUX_A, \
> > > -						   _ICL_PORT_TX_DW4_AUX_B)
> > > +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 4))
> > > +#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 4))
> > > +#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, 0))
> > > +#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN((port), 4, ln))
> > >  #define   LOADGEN_SELECT		(1 << 31)
> > >  #define   POST_CURSOR_1(x)		((x) << 12)
> > >  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> > > @@ -1870,21 +1836,9 @@ enum i915_power_well_id {
> > >  
> > >  #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
> > >  #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
> > > -#define _ICL_PORT_TX_DW5_GRP_A		0x162694
> > > -#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
> > > -#define _ICL_PORT_TX_DW5_LN0_A		0x162894
> > > -#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> > > -#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> > > -#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
> > > -#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW5_GRP_A, \
> > > -						   _ICL_PORT_TX_DW5_GRP_B)
> > > -#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW5_LN0_A, \
> > > -						   _ICL_PORT_TX_DW5_LN0_B)
> > > -#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> > > -						   _ICL_PORT_TX_DW5_AUX_A, \
> > > -						   _ICL_PORT_TX_DW5_AUX_B)
> > > +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX((port), 5))
> > > +#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP((port), 5))
> > > +#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN((port), 5, 0))
> > >  #define   TX_TRAINING_EN		(1 << 31)
> > >  #define   TAP2_DISABLE			(1 << 30)
> > >  #define   TAP3_DISABLE			(1 << 29)
> > > -- 
> > > 2.16.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2] drm/i915/icl: Introduce new macros to get combophy registers

[Lucas De Marchi]

combo-phy register instances are at same offset from base for each
combo-phy port, i.e.

Port A base offset: 0x16200
Port B base offset: 0x6C000

All the other addresses for both ports can be derived by calculating
offset to these base addresses.

PORT_CL_DW_OFFSET	0x0
PORT_CL_DW<x>		0 + x * 4

PORT_COMP_OFFSET	0x100
PORT_COMP_DW<x>		0x100 + x * 4

PORT_PCS_AUX_OFFSET     0x300
PORT_PCS_GRP_OFFSET     0x600
PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100

PORT_TX_AUX_OFFSET      0x380
PORT_TX_GRP_OFFSET      0x680
PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100

And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.

Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.

v2: make port, dw and ln arguments follow the order in
    register's name

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 163 ++++++++++++--------------------
 1 file changed, 59 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fe81dd76734..590574e1ffa7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,20 +1658,21 @@ enum i915_power_well_id {
 /*
  * CNL/ICL Port/COMBO-PHY Registers
  */
+#define _ICL_COMBOPHY_A			0x162000
+#define _ICL_COMBOPHY_B			0x6C000
+#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
+					      _ICL_COMBOPHY_B)
+
 /* CNL/ICL Port CL_DW registers */
-#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
-#define _ICL_PORT_CL_DW5_A	0x162014
-#define _ICL_PORT_CL_DW5_B	0x6C014
-#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
-						 _ICL_PORT_CL_DW5_B)
+#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
+					 4 * (dw))
+
+#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
+#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(5, port))
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
 #define   SUS_CLOCK_CONFIG		(3 << 0)
 
-#define _CNL_PORT_CL_DW10_A		0x162028
-#define _ICL_PORT_CL_DW10_B		0x6c028
-#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
-						   _CNL_PORT_CL_DW10_A, \
-						   _ICL_PORT_CL_DW10_B)
+#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(10, port))
 #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
@@ -1687,31 +1688,23 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
 
-#define _ICL_PORT_CL_DW12_A		0x162030
-#define _ICL_PORT_CL_DW12_B		0x6C030
+#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
-#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
-						   _ICL_PORT_CL_DW12_A, \
-						   _ICL_PORT_CL_DW12_B)
 
 /* CNL/ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP			0x100
+#define _ICL_PORT_COMP_DW(dw, port)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_COMP + 4 * (dw))
+
 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
-#define _ICL_PORT_COMP_DW0_A		0x162100
-#define _ICL_PORT_COMP_DW0_B		0x6C100
-#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
-							 _ICL_PORT_COMP_DW0_B)
+#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(0, port))
 #define   COMP_INIT			(1 << 31)
 
 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
-#define _ICL_PORT_COMP_DW1_A		0x162104
-#define _ICL_PORT_COMP_DW1_B		0x6C104
-#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
-							 _ICL_PORT_COMP_DW1_B)
+#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(1, port))
+
 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
-#define _ICL_PORT_COMP_DW3_A		0x16210C
-#define _ICL_PORT_COMP_DW3_B		0x6C10C
-#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
-							 _ICL_PORT_COMP_DW3_B)
+#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(3, port))
 #define   PROCESS_INFO_DOT_0		(0 << 26)
 #define   PROCESS_INFO_DOT_1		(1 << 26)
 #define   PROCESS_INFO_DOT_4		(2 << 26)
@@ -1724,17 +1717,10 @@ enum i915_power_well_id {
 #define   VOLTAGE_INFO_SHIFT		24
 
 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
-#define _ICL_PORT_COMP_DW9_A		0x162124
-#define _ICL_PORT_COMP_DW9_B		0x6C124
-#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
-							 _ICL_PORT_COMP_DW9_B)
+#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW(9, port))
 
 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
-#define _ICL_PORT_COMP_DW10_A		0x162128
-#define _ICL_PORT_COMP_DW10_B		0x6C128
-#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_COMP_DW10_A, \
-						   _ICL_PORT_COMP_DW10_B)
+#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW(10, port))
 
 /* CNL/ICL Port PCS registers */
 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
@@ -1754,7 +1740,6 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_GRP_D, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
 						    _CNL_PORT_PCS_DW1_GRP_F))
-
 #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_B, \
@@ -1763,21 +1748,18 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_F))
 
-#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
-#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
-#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
-#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
-#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
-#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
-#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
-						   _ICL_PORT_PCS_DW1_GRP_A, \
-						   _ICL_PORT_PCS_DW1_GRP_B)
-#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_PCS_DW1_LN0_A, \
-						   _ICL_PORT_PCS_DW1_LN0_B)
-#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_PCS_DW1_AUX_A, \
-						   _ICL_PORT_PCS_DW1_AUX_B)
+#define _ICL_PORT_PCS_AUX		0x300
+#define _ICL_PORT_PCS_GRP		0x600
+#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
+#define _ICL_PORT_PCS_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_PCS_AUX + 4 * (dw))
+#define _ICL_PORT_PCS_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_PCS_GRP + 4 * (dw))
+#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
+#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
+#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
+#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
 #define   COMMON_KEEPER_EN		(1 << 26)
 
 /* CNL/ICL Port TX registers */
@@ -1808,23 +1790,22 @@ enum i915_power_well_id {
 					       _CNL_PORT_TX_F_LN0_OFFSET) + \
 					       4 * (dw))
 
-#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
-#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
-#define _ICL_PORT_TX_DW2_GRP_A		0x162688
-#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
-#define _ICL_PORT_TX_DW2_LN0_A		0x162888
-#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
-#define _ICL_PORT_TX_DW2_AUX_A		0x162388
-#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
-#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_GRP_A, \
-						   _ICL_PORT_TX_DW2_GRP_B)
-#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_LN0_A, \
-						   _ICL_PORT_TX_DW2_LN0_B)
-#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW2_AUX_A, \
-						   _ICL_PORT_TX_DW2_AUX_B)
+#define _ICL_PORT_TX_AUX		0x380
+#define _ICL_PORT_TX_GRP		0x680
+#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
+
+#define _ICL_PORT_TX_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_TX_AUX + 4 * (dw))
+#define _ICL_PORT_TX_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
+					 _ICL_PORT_TX_GRP + 4 * (dw))
+#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
+
+#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
+#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
+#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(2, port))
+#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(2, port))
+#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK		(1 << 15)
 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
@@ -1841,24 +1822,10 @@ enum i915_power_well_id {
 #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
 					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
 						    _CNL_PORT_TX_DW4_LN0_AE)))
-#define _ICL_PORT_TX_DW4_GRP_A		0x162690
-#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
-#define _ICL_PORT_TX_DW4_LN0_A		0x162890
-#define _ICL_PORT_TX_DW4_LN1_A		0x162990
-#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
-#define _ICL_PORT_TX_DW4_AUX_A		0x162390
-#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
-#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW4_GRP_A, \
-						   _ICL_PORT_TX_DW4_GRP_B)
-#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
-						   _ICL_PORT_TX_DW4_LN0_A, \
-						   _ICL_PORT_TX_DW4_LN0_B) + \
-					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
-						      _ICL_PORT_TX_DW4_LN0_A)))
-#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW4_AUX_A, \
-						   _ICL_PORT_TX_DW4_AUX_B)
+#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
+#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(4, port))
+#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
+#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
 #define   LOADGEN_SELECT		(1 << 31)
 #define   POST_CURSOR_1(x)		((x) << 12)
 #define   POST_CURSOR_1_MASK		(0x3F << 12)
@@ -1867,23 +1834,11 @@ enum i915_power_well_id {
 #define   CURSOR_COEFF(x)		((x) << 0)
 #define   CURSOR_COEFF_MASK		(0x3F << 0)
 
-#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
-#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
-#define _ICL_PORT_TX_DW5_GRP_A		0x162694
-#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
-#define _ICL_PORT_TX_DW5_LN0_A		0x162894
-#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
-#define _ICL_PORT_TX_DW5_AUX_A		0x162394
-#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
-#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_GRP_A, \
-						   _ICL_PORT_TX_DW5_GRP_B)
-#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_LN0_A, \
-						   _ICL_PORT_TX_DW5_LN0_B)
-#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
-						   _ICL_PORT_TX_DW5_AUX_A, \
-						   _ICL_PORT_TX_DW5_AUX_B)
+#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
+#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
+#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(5, port))
+#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(5, port))
+#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
 #define   TX_TRAINING_EN		(1 << 31)
 #define   TAP2_DISABLE			(1 << 30)
 #define   TAP3_DISABLE			(1 << 29)
-- 
2.19.1.1.g8c3cf03f71

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Re: [PATCH v2] drm/i915/icl: Introduce new macros to get combophy registers

[Rodrigo Vivi]

On Mon, Oct 15, 2018 at 07:35:17PM -0700, Lucas De Marchi wrote:
> combo-phy register instances are at same offset from base for each
> combo-phy port, i.e.
> 
> Port A base offset: 0x16200
> Port B base offset: 0x6C000
> 
> All the other addresses for both ports can be derived by calculating
> offset to these base addresses.
> 
> PORT_CL_DW_OFFSET	0x0
> PORT_CL_DW<x>		0 + x * 4
> 
> PORT_COMP_OFFSET	0x100
> PORT_COMP_DW<x>		0x100 + x * 4
> 
> PORT_PCS_AUX_OFFSET     0x300
> PORT_PCS_GRP_OFFSET     0x600
> PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100
> 
> PORT_TX_AUX_OFFSET      0x380
> PORT_TX_GRP_OFFSET      0x680
> PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100
> 
> And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.
> 
> Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.
> 
> v2: make port, dw and ln arguments follow the order in
>     register's name
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Series pushed to dinq. Thanks

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 163 ++++++++++++--------------------
>  1 file changed, 59 insertions(+), 104 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1fe81dd76734..590574e1ffa7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1658,20 +1658,21 @@ enum i915_power_well_id {
>  /*
>   * CNL/ICL Port/COMBO-PHY Registers
>   */
> +#define _ICL_COMBOPHY_A			0x162000
> +#define _ICL_COMBOPHY_B			0x6C000
> +#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> +					      _ICL_COMBOPHY_B)
> +
>  /* CNL/ICL Port CL_DW registers */
> -#define CNL_PORT_CL1CM_DW5	_MMIO(0x162014)
> -#define _ICL_PORT_CL_DW5_A	0x162014
> -#define _ICL_PORT_CL_DW5_B	0x6C014
> -#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
> -						 _ICL_PORT_CL_DW5_B)
> +#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 4 * (dw))
> +
> +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> +#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(5, port))
>  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
>  #define   SUS_CLOCK_CONFIG		(3 << 0)
>  
> -#define _CNL_PORT_CL_DW10_A		0x162028
> -#define _ICL_PORT_CL_DW10_B		0x6c028
> -#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> -						   _CNL_PORT_CL_DW10_A, \
> -						   _ICL_PORT_CL_DW10_B)
> +#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(10, port))
>  #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
>  #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
>  #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> @@ -1687,31 +1688,23 @@ enum i915_power_well_id {
>  #define  PWR_DOWN_LN_MASK		(0xf << 4)
>  #define  PWR_DOWN_LN_SHIFT		4
>  
> -#define _ICL_PORT_CL_DW12_A		0x162030
> -#define _ICL_PORT_CL_DW12_B		0x6C030
> +#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))
>  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> -#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\
> -						   _ICL_PORT_CL_DW12_A, \
> -						   _ICL_PORT_CL_DW12_B)
>  
>  /* CNL/ICL Port COMP_DW registers */
> +#define _ICL_PORT_COMP			0x100
> +#define _ICL_PORT_COMP_DW(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_COMP + 4 * (dw))
> +
>  #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> -#define _ICL_PORT_COMP_DW0_A		0x162100
> -#define _ICL_PORT_COMP_DW0_B		0x6C100
> -#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
> -							 _ICL_PORT_COMP_DW0_B)
> +#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(0, port))
>  #define   COMP_INIT			(1 << 31)
>  
>  #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> -#define _ICL_PORT_COMP_DW1_A		0x162104
> -#define _ICL_PORT_COMP_DW1_B		0x6C104
> -#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
> -							 _ICL_PORT_COMP_DW1_B)
> +#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(1, port))
> +
>  #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> -#define _ICL_PORT_COMP_DW3_A		0x16210C
> -#define _ICL_PORT_COMP_DW3_B		0x6C10C
> -#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
> -							 _ICL_PORT_COMP_DW3_B)
> +#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(3, port))
>  #define   PROCESS_INFO_DOT_0		(0 << 26)
>  #define   PROCESS_INFO_DOT_1		(1 << 26)
>  #define   PROCESS_INFO_DOT_4		(2 << 26)
> @@ -1724,17 +1717,10 @@ enum i915_power_well_id {
>  #define   VOLTAGE_INFO_SHIFT		24
>  
>  #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> -#define _ICL_PORT_COMP_DW9_A		0x162124
> -#define _ICL_PORT_COMP_DW9_B		0x6C124
> -#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
> -							 _ICL_PORT_COMP_DW9_B)
> +#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW(9, port))
>  
>  #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> -#define _ICL_PORT_COMP_DW10_A		0x162128
> -#define _ICL_PORT_COMP_DW10_B		0x6C128
> -#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_COMP_DW10_A, \
> -						   _ICL_PORT_COMP_DW10_B)
> +#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW(10, port))
>  
>  /* CNL/ICL Port PCS registers */
>  #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> @@ -1754,7 +1740,6 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_GRP_D, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
>  						    _CNL_PORT_PCS_DW1_GRP_F))
> -
>  #define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_B, \
> @@ -1763,21 +1748,18 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_F))
>  
> -#define _ICL_PORT_PCS_DW1_GRP_A		0x162604
> -#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604
> -#define _ICL_PORT_PCS_DW1_LN0_A		0x162804
> -#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804
> -#define _ICL_PORT_PCS_DW1_AUX_A		0x162304
> -#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304
> -#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\
> -						   _ICL_PORT_PCS_DW1_GRP_A, \
> -						   _ICL_PORT_PCS_DW1_GRP_B)
> -#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_PCS_DW1_LN0_A, \
> -						   _ICL_PORT_PCS_DW1_LN0_B)
> -#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_PCS_DW1_AUX_A, \
> -						   _ICL_PORT_PCS_DW1_AUX_B)
> +#define _ICL_PORT_PCS_AUX		0x300
> +#define _ICL_PORT_PCS_GRP		0x600
> +#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
> +#define _ICL_PORT_PCS_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_PCS_AUX + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_PCS_GRP + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> +#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
> +#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
> +#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
>  /* CNL/ICL Port TX registers */
> @@ -1808,23 +1790,22 @@ enum i915_power_well_id {
>  					       _CNL_PORT_TX_F_LN0_OFFSET) + \
>  					       4 * (dw))
>  
> -#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
> -#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
> -#define _ICL_PORT_TX_DW2_GRP_A		0x162688
> -#define _ICL_PORT_TX_DW2_GRP_B		0x6C688
> -#define _ICL_PORT_TX_DW2_LN0_A		0x162888
> -#define _ICL_PORT_TX_DW2_LN0_B		0x6C888
> -#define _ICL_PORT_TX_DW2_AUX_A		0x162388
> -#define _ICL_PORT_TX_DW2_AUX_B		0x6c388
> -#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_GRP_A, \
> -						   _ICL_PORT_TX_DW2_GRP_B)
> -#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_LN0_A, \
> -						   _ICL_PORT_TX_DW2_LN0_B)
> -#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW2_AUX_A, \
> -						   _ICL_PORT_TX_DW2_AUX_B)
> +#define _ICL_PORT_TX_AUX		0x380
> +#define _ICL_PORT_TX_GRP		0x680
> +#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> +
> +#define _ICL_PORT_TX_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_TX_AUX + 4 * (dw))
> +#define _ICL_PORT_TX_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
> +					 _ICL_PORT_TX_GRP + 4 * (dw))
> +#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
> +
> +#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> +#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
> +#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(2, port))
> +#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(2, port))
> +#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
>  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
>  #define   SWING_SEL_UPPER_MASK		(1 << 15)
>  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> @@ -1841,24 +1822,10 @@ enum i915_power_well_id {
>  #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
>  					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
>  						    _CNL_PORT_TX_DW4_LN0_AE)))
> -#define _ICL_PORT_TX_DW4_GRP_A		0x162690
> -#define _ICL_PORT_TX_DW4_GRP_B		0x6C690
> -#define _ICL_PORT_TX_DW4_LN0_A		0x162890
> -#define _ICL_PORT_TX_DW4_LN1_A		0x162990
> -#define _ICL_PORT_TX_DW4_LN0_B		0x6C890
> -#define _ICL_PORT_TX_DW4_AUX_A		0x162390
> -#define _ICL_PORT_TX_DW4_AUX_B		0x6c390
> -#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW4_GRP_A, \
> -						   _ICL_PORT_TX_DW4_GRP_B)
> -#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \
> -						   _ICL_PORT_TX_DW4_LN0_A, \
> -						   _ICL_PORT_TX_DW4_LN0_B) + \
> -					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
> -						      _ICL_PORT_TX_DW4_LN0_A)))
> -#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW4_AUX_A, \
> -						   _ICL_PORT_TX_DW4_AUX_B)
> +#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
> +#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(4, port))
> +#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
> +#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
>  #define   LOADGEN_SELECT		(1 << 31)
>  #define   POST_CURSOR_1(x)		((x) << 12)
>  #define   POST_CURSOR_1_MASK		(0x3F << 12)
> @@ -1867,23 +1834,11 @@ enum i915_power_well_id {
>  #define   CURSOR_COEFF(x)		((x) << 0)
>  #define   CURSOR_COEFF_MASK		(0x3F << 0)
>  
> -#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
> -#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
> -#define _ICL_PORT_TX_DW5_GRP_A		0x162694
> -#define _ICL_PORT_TX_DW5_GRP_B		0x6C694
> -#define _ICL_PORT_TX_DW5_LN0_A		0x162894
> -#define _ICL_PORT_TX_DW5_LN0_B		0x6C894
> -#define _ICL_PORT_TX_DW5_AUX_A		0x162394
> -#define _ICL_PORT_TX_DW5_AUX_B		0x6c394
> -#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_GRP_A, \
> -						   _ICL_PORT_TX_DW5_GRP_B)
> -#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_LN0_A, \
> -						   _ICL_PORT_TX_DW5_LN0_B)
> -#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \
> -						   _ICL_PORT_TX_DW5_AUX_A, \
> -						   _ICL_PORT_TX_DW5_AUX_B)
> +#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> +#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
> +#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(5, port))
> +#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(5, port))
> +#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
>  #define   TX_TRAINING_EN		(1 << 31)
>  #define   TAP2_DISABLE			(1 << 30)
>  #define   TAP3_DISABLE			(1 << 29)
> -- 
> 2.19.1.1.g8c3cf03f71
> 
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[PATCH 8/8] drm/i915/icl: Fix DDI/TC port clk_off bits

[Mahesh Kumar]

DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eaf3e0d529d3..e1a2851a28cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9302,6 +9302,9 @@ enum skl_power_gate {
 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
 						      (port) + 10))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
 						(port) * 2)
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b5b8dae06cde..9883f02756ab 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2733,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 	return DDI_BUF_TRANS_SELECT(level);
 }
 
+static inline
+uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
+				   enum port port)
+{
+	if (intel_port_is_combophy(dev_priv, port)) {
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	} else if (intel_port_is_tc(dev_priv, port)) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
+	}
+
+	return 0;
+}
+
 void icl_map_plls_to_ports(struct drm_crtc *crtc,
 			   struct intel_crtc_state *crtc_state,
 			   struct drm_atomic_state *old_state)
@@ -2756,7 +2771,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 		mutex_lock(&dev_priv->dpll_lock);
 
 		val = I915_READ(DPCLKA_CFGCR0_ICL);
-		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
+		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
 
 		if (intel_port_is_combophy(dev_priv, port)) {
 			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
@@ -2765,7 +2780,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 			POSTING_READ(DPCLKA_CFGCR0_ICL);
 		}
 
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 		mutex_unlock(&dev_priv->dpll_lock);
@@ -2793,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
 		mutex_lock(&dev_priv->dpll_lock);
 		I915_WRITE(DPCLKA_CFGCR0_ICL,
 			   I915_READ(DPCLKA_CFGCR0_ICL) |
-			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));
 		mutex_unlock(&dev_priv->dpll_lock);
 	}
 }
-- 
2.16.2

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Re: [PATCH 8/8] drm/i915/icl: Fix DDI/TC port clk_off bits

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:52:03PM +0530, Mahesh Kumar wrote:
> DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
> from offset 12 & TC4 is at offset 21.
> Create a function to choose correct clk-off bit.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>

Missing Fixes tag.


Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
>  2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eaf3e0d529d3..e1a2851a28cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9302,6 +9302,9 @@ enum skl_power_gate {
>  #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
>  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
>  						      (port) + 10))
> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
> +#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
> +						      21 : (tc_port) + 12))
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
>  						(port) * 2)
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b5b8dae06cde..9883f02756ab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2733,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  	return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> +static inline
> +uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> +				   enum port port)
> +{
> +	if (intel_port_is_combophy(dev_priv, port)) {
> +		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +	} else if (intel_port_is_tc(dev_priv, port)) {
> +		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +
> +		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> +	}
> +
> +	return 0;
> +}
> +
>  void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  			   struct intel_crtc_state *crtc_state,
>  			   struct drm_atomic_state *old_state)
> @@ -2756,7 +2771,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  		mutex_lock(&dev_priv->dpll_lock);
>  
>  		val = I915_READ(DPCLKA_CFGCR0_ICL);
> -		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
> +		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
>  
>  		if (intel_port_is_combophy(dev_priv, port)) {
>  			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> @@ -2765,7 +2780,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
>  			POSTING_READ(DPCLKA_CFGCR0_ICL);
>  		}
>  
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
>  		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  
>  		mutex_unlock(&dev_priv->dpll_lock);
> @@ -2793,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
>  		mutex_lock(&dev_priv->dpll_lock);
>  		I915_WRITE(DPCLKA_CFGCR0_ICL,
>  			   I915_READ(DPCLKA_CFGCR0_ICL) |
> -			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> +			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));
>  		mutex_unlock(&dev_priv->dpll_lock);
>  	}
>  }
> -- 
> 2.16.2
> 
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[PATCH v2] drm/i915/icl: Fix DDI/TC port clk_off bits

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.

v2: Add fixes tag (Lucas)

Fixes: c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks")
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 590574e1ffa7..2366b95f5965 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9310,6 +9310,9 @@ enum skl_power_gate {
 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
 						      (port) + 10))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
 						(port) * 2)
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e0a91b6080d..6b9742baa5f2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2740,6 +2740,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 	return DDI_BUF_TRANS_SELECT(level);
 }
 
+static inline
+uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
+				   enum port port)
+{
+	if (intel_port_is_combophy(dev_priv, port)) {
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	} else if (intel_port_is_tc(dev_priv, port)) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
+	}
+
+	return 0;
+}
+
 void icl_map_plls_to_ports(struct drm_crtc *crtc,
 			   struct intel_crtc_state *crtc_state,
 			   struct drm_atomic_state *old_state)
@@ -2763,7 +2778,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 		mutex_lock(&dev_priv->dpll_lock);
 
 		val = I915_READ(DPCLKA_CFGCR0_ICL);
-		WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
+		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
 
 		if (intel_port_is_combophy(dev_priv, port)) {
 			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
@@ -2772,7 +2787,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
 			POSTING_READ(DPCLKA_CFGCR0_ICL);
 		}
 
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 		mutex_unlock(&dev_priv->dpll_lock);
@@ -2800,7 +2815,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
 		mutex_lock(&dev_priv->dpll_lock);
 		I915_WRITE(DPCLKA_CFGCR0_ICL,
 			   I915_READ(DPCLKA_CFGCR0_ICL) |
-			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));
 		mutex_unlock(&dev_priv->dpll_lock);
 	}
 }
-- 
2.19.1.1.g8c3cf03f71

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✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports
URL   : https://patchwork.freedesktop.org/series/50484/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4591313167c8 drm/i915/icl: create function to identify combophy port
b95d617455a9 drm/i915/icl: use combophy/TC helper functions during display detection
4e37b5e76bdf drm/i915/icl: Refactor get_ddi_pll using helper func
ba3df9087f61 drm/i915/icl: Use helper functions to classify the ports
d0c90e3f03a0 drm/i915/icl: Refactor icl pll functions
be5ebfc35a53 drm/i915/icl: Combine all port/combophy macros at one place
4b77c0de33ec drm/i915/icl: Introduce new macros to get combophy registers
bc98520b291a drm/i915/icl: Fix DDI/TC port clk_off bits
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:9308:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))

total: 0 errors, 0 warnings, 1 checks, 54 lines checked

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✗ Fi.CI.BAT: failure for Refactor and Add helper function for combophy/tc ports

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports
URL   : https://patchwork.freedesktop.org/series/50484/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4917 -> Patchwork_10334 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10334 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10334, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10334:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_hangcheck:
      fi-icl-u:           PASS -> INCOMPLETE

    
    ==== Warnings ====

    igt@drv_selftest@live_guc:
      fi-icl-u:           PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_10334 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@cs-compute:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#108094)

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-cfl-8109u:       NOTRUN -> INCOMPLETE (fdo#108126, fdo#106070)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-cfl-8109u:       INCOMPLETE (fdo#108126, fdo#106070) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
  fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126


== Participating hosts (47 -> 44) ==

  Additional (1): fi-snb-2520m 
  Missing    (4): fi-bsw-cyan fi-byt-squawks fi-icl-u2 fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4917 -> Patchwork_10334

  CI_DRM_4917: 7483d033ff9da99c977541021d91940973c94ead @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4662: ebf6a1dd1795e2f014ff3c47fe2eb4d5255845bd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10334: bc98520b291a477a94a5718fc4c6ef780910cdf8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bc98520b291a drm/i915/icl: Fix DDI/TC port clk_off bits
4b77c0de33ec drm/i915/icl: Introduce new macros to get combophy registers
be5ebfc35a53 drm/i915/icl: Combine all port/combophy macros at one place
d0c90e3f03a0 drm/i915/icl: Refactor icl pll functions
ba3df9087f61 drm/i915/icl: Use helper functions to classify the ports
4e37b5e76bdf drm/i915/icl: Refactor get_ddi_pll using helper func
b95d617455a9 drm/i915/icl: use combophy/TC helper functions during display detection
4591313167c8 drm/i915/icl: create function to identify combophy port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10334/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4919 -> Patchwork_10341 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10341 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10341, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10341:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-hsw-4770r:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10341 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@cs-compute:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#108094)

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       NOTRUN -> DMESG-WARN (fdo#106248, fdo#106725)

    igt@drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#107425, fdo#107924)

    igt@gem_exec_suspend@basic-s3:
      fi-bdw-samus:       PASS -> INCOMPLETE (fdo#107773)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-glk-j4005:       NOTRUN -> DMESG-WARN (fdo#106000)

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-glk-j4005:       NOTRUN -> FAIL (fdo#100368)

    igt@kms_flip@basic-plain-flip:
      fi-glk-j4005:       NOTRUN -> DMESG-WARN (fdo#106097)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     NOTRUN -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     NOTRUN -> FAIL (fdo#103191, fdo#107362)

    igt@pm_rpm@module-reload:
      fi-glk-j4005:       NOTRUN -> DMESG-WARN (fdo#107726)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-byt-clapper:     INCOMPLETE (fdo#102657) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-icl-u:           INCOMPLETE (fdo#107713) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924
  fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094


== Participating hosts (49 -> 45) ==

  Additional (1): fi-glk-j4005 
  Missing    (5): fi-ctg-p8600 fi-bsw-cyan fi-byt-squawks fi-icl-u2 fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4919 -> Patchwork_10341

  CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10341: f57caa7775e7b812ebab31aba3d1608bea229222 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f57caa7775e7 drm/i915/icl: Fix DDI/TC port clk_off bits
4eca1f772c36 drm/i915/icl: Introduce new macros to get combophy registers
7b2d6f208091 drm/i915/icl: Combine all port/combophy macros at one place
c62ea17882cf drm/i915/icl: Refactor icl pll functions
ae94362d7d98 drm/i915/icl: Use helper functions to classify the ports
ff20ff437676 drm/i915/icl: Refactor get_ddi_pll using helper func
576a046de6ca drm/i915/icl: use combophy/TC helper functions during display detection
a9fc7d4482e1 drm/i915/icl: create function to identify combophy port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10341/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4919_full -> Patchwork_10341_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10341_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +5

    igt@kms_cursor_crc@cursor-256x85-onscreen:
      shard-glk:          PASS -> FAIL (fdo#103232) +2

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#103191)

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          PASS -> DMESG-WARN (fdo#105763, fdo#106538)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-snb:          PASS -> FAIL (fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-glk:          PASS -> FAIL (fdo#103167) +2

    {igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145)

    {igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
      shard-glk:          PASS -> FAIL (fdo#108145)

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          PASS -> FAIL (fdo#103166)

    
    ==== Possible fixes ====

    igt@kms_busy@extended-pageflip-hang-newfb-render-c:
      shard-glk:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_cursor_crc@cursor-128x42-random:
      shard-skl:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled:
      shard-skl:          FAIL (fdo#103184) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
      shard-skl:          FAIL (fdo#103167) -> PASS +5

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
      shard-skl:          FAIL (fdo#105682) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +3

    {igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
      shard-skl:          FAIL (fdo#108145) -> PASS

    {igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max}:
      shard-apl:          FAIL (fdo#108145) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS +1

    igt@kms_universal_plane@universal-plane-pipe-b-functional:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    
    ==== Warnings ====

    {igt@kms_plane_alpha_blend@pipe-a-alpha-basic}:
      shard-glk:          FAIL (fdo#108145) -> INCOMPLETE (fdo#103359, k.org#198133)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4919 -> Patchwork_10341

  CI_DRM_4919: e489eb0296673790264b25266ef45aae7d1ab566 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10341: f57caa7775e7b812ebab31aba3d1608bea229222 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10341/shards.html
_______________________________________________
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✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports (rev2)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev2)
URL   : https://patchwork.freedesktop.org/series/50484/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
32f5e0dd8f7e drm/i915/icl: create function to identify combophy port
5d2333571a63 drm/i915/icl: use combophy/TC helper functions during display detection
05b02648ec23 drm/i915/icl: Refactor get_ddi_pll using helper func
b1af249bee9d drm/i915/icl: Use helper functions to classify the ports
34829cbb0f1a drm/i915/icl: Refactor icl pll functions
9ea16758bce8 drm/i915/icl: Combine all port/combophy macros at one place
49a53243c2c8 drm/i915/icl: Introduce new macros to get combophy registers
863f6eea7f50 drm/i915/icl: Fix DDI/TC port clk_off bits
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:9308:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))

total: 0 errors, 0 warnings, 1 checks, 54 lines checked

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports (rev2)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev2)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4930 -> Patchwork_10355 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10355 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10355, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10355:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-glk-j4005:       PASS -> SKIP

    igt@prime_vgem@basic-fence-flip:
      fi-ivb-3520m:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10355 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload-inject:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106238) +1

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    igt@pm_rpm@basic-rte:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    
    ==== Possible fixes ====

    igt@drv_getparams_basic@basic-subslice-total:
      fi-snb-2520m:       DMESG-WARN (fdo#103713) -> PASS +10

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-glk-j4005:       DMESG-WARN (fdo#106238) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    igt@pm_rpm@basic-pci-d3-state:
      fi-glk-dsi:         INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    
    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-glk-j4005:       DMESG-WARN (fdo#107726) -> DMESG-FAIL (fdo#104767)

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104767 https://bugs.freedesktop.org/show_bug.cgi?id=104767
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (45 -> 43) ==

  Additional (1): fi-hsw-4770 
  Missing    (3): fi-bsw-cyan fi-byt-squawks fi-icl-u2 


== Build changes ==

    * Linux: CI_DRM_4930 -> Patchwork_10355

  CI_DRM_4930: bf1bd5e86f267d58ac68c342fcfff70e8ef1fd34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4666: bba38422e7f903094562f1b78cc3579683c0a667 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10355: 863f6eea7f50bad2dd813ad349778ffdaacdf06f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

863f6eea7f50 drm/i915/icl: Fix DDI/TC port clk_off bits
49a53243c2c8 drm/i915/icl: Introduce new macros to get combophy registers
9ea16758bce8 drm/i915/icl: Combine all port/combophy macros at one place
34829cbb0f1a drm/i915/icl: Refactor icl pll functions
b1af249bee9d drm/i915/icl: Use helper functions to classify the ports
05b02648ec23 drm/i915/icl: Refactor get_ddi_pll using helper func
5d2333571a63 drm/i915/icl: use combophy/TC helper functions during display detection
32f5e0dd8f7e drm/i915/icl: create function to identify combophy port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10355/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports (rev2)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev2)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4930 -> Patchwork_10356 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10356 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10356, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10356:

  === IGT changes ===

    ==== Warnings ====

    igt@prime_vgem@basic-fence-flip:
      fi-ivb-3520m:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10356 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106248, fdo#106725)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-bdw-samus:       PASS -> INCOMPLETE (fdo#107773)

    igt@kms_flip@basic-flip-vs-modeset:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106000)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-blb-e6850:       NOTRUN -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@drv_getparams_basic@basic-subslice-total:
      fi-snb-2520m:       DMESG-WARN (fdo#103713) -> PASS +10

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-glk-j4005:       DMESG-WARN (fdo#106238) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    igt@pm_rpm@basic-pci-d3-state:
      fi-glk-dsi:         INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (45 -> 43) ==

  Additional (1): fi-hsw-4770 
  Missing    (3): fi-bsw-cyan fi-byt-squawks fi-icl-u2 


== Build changes ==

    * Linux: CI_DRM_4930 -> Patchwork_10356

  CI_DRM_4930: bf1bd5e86f267d58ac68c342fcfff70e8ef1fd34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4666: bba38422e7f903094562f1b78cc3579683c0a667 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10356: 5bcb472b25d4d5b2269d92392c4a845713fbd3ff @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5bcb472b25d4 drm/i915/icl: Fix DDI/TC port clk_off bits
b8f7bc319f60 drm/i915/icl: Introduce new macros to get combophy registers
e07bdd1ce82d drm/i915/icl: Combine all port/combophy macros at one place
db90bb13e05f drm/i915/icl: Refactor icl pll functions
0f2e64af0597 drm/i915/icl: Use helper functions to classify the ports
6595247dc053 drm/i915/icl: Refactor get_ddi_pll using helper func
c5b949f2a561 drm/i915/icl: use combophy/TC helper functions during display detection
2583a0d7366a drm/i915/icl: create function to identify combophy port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10356/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports (rev2)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev2)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4930_full -> Patchwork_10355_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10355_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_schedule@pi-ringfull-blt:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-glk:          NOTRUN -> FAIL (fdo#103158) +3

    igt@gem_pwrite_pread@uncached-pwrite-blt-gtt_mmap-performance:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-glk:          NOTRUN -> FAIL (fdo#106641)

    igt@kms_busy@extended-modeset-hang-newfb-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956) +3

    igt@kms_busy@extended-modeset-hang-newfb-render-c:
      shard-glk:          NOTRUN -> DMESG-WARN (fdo#107956) +11

    igt@kms_cursor_crc@cursor-128x128-onscreen:
      shard-skl:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +2

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108)
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#103191)

    igt@kms_cursor_crc@cursor-256x85-onscreen:
      shard-glk:          NOTRUN -> FAIL (fdo#103232) +3

    igt@kms_cursor_crc@cursor-256x85-sliding:
      shard-skl:          NOTRUN -> FAIL (fdo#103232) +1

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#103232, fdo#103191)

    igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#106509, fdo#105454)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#105454)

    igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
      shard-skl:          PASS -> FAIL (fdo#103184)

    igt@kms_fbcon_fbt@psr:
      shard-skl:          NOTRUN -> FAIL (fdo#107882)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          NOTRUN -> FAIL (fdo#103167) +10

    igt@kms_frontbuffer_tracking@fbc-tilingchange:
      shard-skl:          PASS -> FAIL (fdo#105682)

    igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
      shard-skl:          PASS -> FAIL (fdo#103167) +4

    igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
      shard-skl:          NOTRUN -> FAIL (fdo#105683)

    igt@kms_plane@pixel-format-pipe-a-planes:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#106885) +1

    {igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
      shard-skl:          PASS -> FAIL (fdo#108145)

    {igt@kms_plane_alpha_blend@pipe-b-alpha-basic}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +3

    {igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
      shard-skl:          NOTRUN -> FAIL (fdo#108146)

    {igt@kms_plane_alpha_blend@pipe-c-alpha-7efc}:
      shard-glk:          NOTRUN -> FAIL (fdo#108146) +1

    {igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb}:
      shard-glk:          NOTRUN -> FAIL (fdo#108145) +12

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          NOTRUN -> FAIL (fdo#103166) +3

    igt@kms_rotation_crc@exhaust-fences:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#105748)

    igt@kms_setmode@basic:
      shard-glk:          NOTRUN -> FAIL (fdo#99912)
      shard-kbl:          PASS -> FAIL (fdo#99912)

    igt@pm_backlight@fade_with_suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107847)

    igt@pm_rpm@gem-evict-pwrite:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          FAIL (fdo#106641) -> PASS

    igt@kms_flip_tiling@flip-yf-tiled:
      shard-apl:          DMESG-FAIL (fdo#103558, fdo#105602) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          FAIL (fdo#103167, fdo#105682) -> PASS

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
      shard-apl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +18

    igt@perf@enable-disable:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@perf_pmu@rc6-runtime-pm:
      shard-skl:          FAIL (fdo#105010) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683
  fdo#105748 https://bugs.freedesktop.org/show_bug.cgi?id=105748
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 6) ==

  Additional (1): shard-glk 


== Build changes ==

    * Linux: CI_DRM_4930 -> Patchwork_10355

  CI_DRM_4930: bf1bd5e86f267d58ac68c342fcfff70e8ef1fd34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4666: bba38422e7f903094562f1b78cc3579683c0a667 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10355: 863f6eea7f50bad2dd813ad349778ffdaacdf06f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10355/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports (rev2)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev2)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4930_full -> Patchwork_10356_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10356_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_schedule@pi-ringfull-blt:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-glk:          NOTRUN -> FAIL (fdo#103158) +3

    igt@gem_render_copy_redux@interruptible:
      shard-kbl:          PASS -> INCOMPLETE (fdo#106650, fdo#103665)

    igt@gem_softpin@noreloc-s3:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108, fdo#107773)

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-glk:          NOTRUN -> FAIL (fdo#106641)

    igt@kms_busy@extended-modeset-hang-newfb-render-c:
      shard-glk:          NOTRUN -> DMESG-WARN (fdo#107956) +11

    igt@kms_cursor_crc@cursor-128x128-onscreen:
      shard-skl:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#104108)

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-glk:          NOTRUN -> FAIL (fdo#103232) +7

    igt@kms_cursor_crc@cursor-256x85-random:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614)

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +1

    igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#107409, fdo#106509)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#105454, fdo#106509)

    igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
      shard-skl:          PASS -> FAIL (fdo#103184)

    igt@kms_fbcon_fbt@psr:
      shard-skl:          NOTRUN -> FAIL (fdo#107882)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          NOTRUN -> FAIL (fdo#105363)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-skl:          PASS -> FAIL (fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
      shard-glk:          NOTRUN -> FAIL (fdo#103167) +9

    igt@kms_frontbuffer_tracking@fbc-tilingchange:
      shard-skl:          PASS -> FAIL (fdo#103167) +2

    igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
      shard-skl:          PASS -> FAIL (fdo#105682) +1

    igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
      shard-skl:          NOTRUN -> FAIL (fdo#105683)

    igt@kms_frontbuffer_tracking@fbcpsr-suspend:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108)

    igt@kms_plane@pixel-format-pipe-a-planes:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#106885)

    {igt@kms_plane_alpha_blend@pipe-a-alpha-basic}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +1

    {igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
      shard-skl:          PASS -> FAIL (fdo#108145)

    {igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
      shard-skl:          NOTRUN -> FAIL (fdo#108146)

    {igt@kms_plane_alpha_blend@pipe-c-alpha-7efc}:
      shard-glk:          NOTRUN -> FAIL (fdo#108146) +1

    {igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb}:
      shard-glk:          NOTRUN -> FAIL (fdo#108145) +13

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          NOTRUN -> FAIL (fdo#103166) +2

    igt@kms_setmode@basic:
      shard-glk:          NOTRUN -> FAIL (fdo#99912)
      shard-kbl:          PASS -> FAIL (fdo#99912)

    igt@pm_backlight@fade_with_suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107847)

    
    ==== Possible fixes ====

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          FAIL (fdo#106641) -> PASS

    igt@kms_flip_tiling@flip-yf-tiled:
      shard-apl:          DMESG-FAIL (fdo#105602, fdo#103558) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          FAIL (fdo#103167, fdo#105682) -> PASS

    igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS

    igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
      shard-apl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +18

    igt@perf@enable-disable:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106650 https://bugs.freedesktop.org/show_bug.cgi?id=106650
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107409 https://bugs.freedesktop.org/show_bug.cgi?id=107409
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 6) ==

  Additional (1): shard-glk 


== Build changes ==

    * Linux: CI_DRM_4930 -> Patchwork_10356

  CI_DRM_4930: bf1bd5e86f267d58ac68c342fcfff70e8ef1fd34 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4666: bba38422e7f903094562f1b78cc3579683c0a667 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10356: 5bcb472b25d4d5b2269d92392c4a845713fbd3ff @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10356/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for Refactor and Add helper function for combophy/tc ports (rev3)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev3)
URL   : https://patchwork.freedesktop.org/series/50484/
State : failure

== Summary ==

Applying: drm/i915/icl: create function to identify combophy port
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/intel_ddi.c
M	drivers/gpu/drm/i915/intel_display.c
M	drivers/gpu/drm/i915/intel_drv.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_drv.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/intel_ddi.c
Applying: drm/i915/icl: use combophy/TC helper functions during display detection
Applying: drm/i915/icl: Refactor get_ddi_pll using helper func
Applying: drm/i915/icl: Use helper functions to classify the ports
Applying: drm/i915/icl: Refactor icl pll functions
Applying: drm/i915/icl: Combine all port/combophy macros at one place
Applying: drm/i915/icl: Introduce new macros to get combophy registers
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_reg.h
error: Failed to merge in the changes.
Patch failed at 0007 drm/i915/icl: Introduce new macros to get combophy registers
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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✗ Fi.CI.CHECKPATCH: warning for Refactor and Add helper function for combophy/tc ports (rev5)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL   : https://patchwork.freedesktop.org/series/50484/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7a0475e44ad4 drm/i915/icl: create function to identify combophy port
99f69dd6d4e8 drm/i915/icl: use combophy/TC helper functions during display detection
1d213780b313 drm/i915/icl: Refactor get_ddi_pll using helper func
7e97618174e4 drm/i915/icl: Use helper functions to classify the ports
d44e98562823 drm/i915/icl: Refactor icl pll functions
fe97027237f6 drm/i915/icl: Combine all port/combophy macros at one place
76fe790f6910 drm/i915/icl: Introduce new macros to get combophy registers
3cc221173ac3 drm/i915/icl: Fix DDI/TC port clk_off bits
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9314:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))

total: 0 errors, 0 warnings, 1 checks, 54 lines checked

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✓ Fi.CI.BAT: success for Refactor and Add helper function for combophy/tc ports (rev5)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4984 -> Patchwork_10467 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50484/revisions/5/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10467 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191)

    
    ==== Possible fixes ====

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (53 -> 46) ==

  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 


== Build changes ==

    * Linux: CI_DRM_4984 -> Patchwork_10467

  CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10467: 3cc221173ac3118a71378cf5e0ad68c12af019f2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3cc221173ac3 drm/i915/icl: Fix DDI/TC port clk_off bits
76fe790f6910 drm/i915/icl: Introduce new macros to get combophy registers
fe97027237f6 drm/i915/icl: Combine all port/combophy macros at one place
d44e98562823 drm/i915/icl: Refactor icl pll functions
7e97618174e4 drm/i915/icl: Use helper functions to classify the ports
1d213780b313 drm/i915/icl: Refactor get_ddi_pll using helper func
99f69dd6d4e8 drm/i915/icl: use combophy/TC helper functions during display detection
7a0475e44ad4 drm/i915/icl: create function to identify combophy port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10467/issues.html
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✓ Fi.CI.IGT: success for Refactor and Add helper function for combophy/tc ports (rev5)

[Patchwork]

== Series Details ==

Series: Refactor and Add helper function for combophy/tc ports (rev5)
URL   : https://patchwork.freedesktop.org/series/50484/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4984_full -> Patchwork_10467_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10467_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10467_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10467_full:

  === IGT changes ===

    ==== Warnings ====

    igt@drm_read@empty-nonblock:
      shard-snb:          PASS -> SKIP +3

    
== Known issues ==

  Here are the changes found in Patchwork_10467_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_cpu_reloc@full:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#108073)

    igt@gem_exec_schedule@pi-ringfull-vebox:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-skl:          NOTRUN -> TIMEOUT (fdo#108039)

    igt@gem_userptr_blits@readonly-unsync:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#108074)

    igt@gem_wait@busy-default:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411)

    igt@kms_busy@extended-modeset-hang-newfb-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956) +2

    igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
      shard-skl:          NOTRUN -> FAIL (fdo#105458)

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +1

    igt@kms_draw_crc@fill-fb:
      shard-skl:          NOTRUN -> FAIL (fdo#103184)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-skl:          PASS -> FAIL (fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
      shard-glk:          PASS -> FAIL (fdo#103167) +3

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
      shard-skl:          NOTRUN -> FAIL (fdo#105682)

    igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
      shard-skl:          NOTRUN -> FAIL (fdo#105683)

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
      shard-apl:          SKIP -> INCOMPLETE (fdo#103927)

    igt@kms_plane@pixel-format-pipe-a-planes:
      shard-skl:          NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885)

    igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
      shard-apl:          PASS -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +2

    igt@kms_plane_lowres@pipe-c-tiling-x:
      shard-kbl:          PASS -> DMESG-WARN (fdo#105345)

    igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_psr@suspend:
      shard-skl:          PASS -> INCOMPLETE (fdo#107773)

    igt@kms_rotation_crc@exhaust-fences:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#105748)

    
    ==== Possible fixes ====

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-apl:          FAIL (fdo#103232, fdo#103191) -> PASS

    igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
      shard-glk:          DMESG-WARN (fdo#106538, fdo#105763) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip_tiling@flip-yf-tiled:
      shard-apl:          DMESG-WARN (fdo#103558, fdo#105602) -> PASS +2

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          DMESG-FAIL (fdo#103167, fdo#103558, fdo#105602) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
      shard-skl:          INCOMPLETE (fdo#104108) -> PASS

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-glk:          FAIL (fdo#103166) -> PASS +1

    igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_plane_lowres@pipe-a-tiling-yf:
      shard-kbl:          DMESG-WARN (fdo#105345) -> PASS

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS +2

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105458 https://bugs.freedesktop.org/show_bug.cgi?id=105458
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683
  fdo#105748 https://bugs.freedesktop.org/show_bug.cgi?id=105748
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
  fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
  fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4984 -> Patchwork_10467

  CI_DRM_4984: 90b59df999a13a6405f8d7ece08a69120a9b361a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4678: 9310a1265ceabeec736bdf0a76e1e0357c76c0b1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10467: 3cc221173ac3118a71378cf5e0ad68c12af019f2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10467/shards.html
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