Re: [v2 3/6] i915/dp/fec: Check for FEC Support

From: Manasi Navare <manasi.d.navare@intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [v2 3/6] i915/dp/fec: Check for FEC Support
Date: Thu, 18 Oct 2018 15:45:27 -0700	[thread overview]
Message-ID: <20181018224527.GJ8224@intel.com> (raw)
In-Reply-To: <20181015215037.13901-4-anusha.srivatsa@intel.com>

On Mon, Oct 15, 2018 at 02:50:34PM -0700, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
> 
> Check if the sink supports FEC using the helper.
> 
> v2: Mention External DP where ever FEC is mentioned
> in the code.Check return status of dpcd reads. (Gaurav)
> - Do regular mode check even if FEC is not supported. (manasi)
> 
> v3: Do not perform any dpcd writes in the atomic
> check phase. (DK, Manasi)
> 
> v4: Use debug level logging for scenario where sink does
> not support a feature. (DK)
> 
> v5: Correct commit message. rebase.
> 
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8a0e0a0b26f6..318494afd14a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -650,7 +650,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  			dsc_slice_count =
>  				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
>  								true);
> -		} else {
> +		} else if (drm_dp_sink_supports_fec(intel_dp->fec_dpcd)) {

Pass just a single field  as suggested in Patch 1.
With that change,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

>  			dsc_max_output_bpp =
>  				intel_dp_dsc_get_output_bpp(max_link_clock,
>  							    max_lanes,
> @@ -660,7 +660,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  				intel_dp_dsc_get_slice_count(intel_dp,
>  							     target_clock,
>  							     mode->hdisplay);
> -		}
> +		} else
> +			DRM_DEBUG_KMS("Sink device does not Support FEC\n");
>  	}
>  
>  	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> @@ -2033,6 +2034,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp))
>  		return false;
>  
> +	/* DSC not supported if external DP sink does not support FEC */
> +	if (!intel_dp_is_edp(intel_dp) &&
> +	    !drm_dp_sink_supports_fec(intel_dp->fec_dpcd)) {
> +		DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
> +		return false;
> +	}
> +
>  	/* DSC not supported for DSC sink BPC < 8 */
>  	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
>  		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
> -- 
> 2.17.1
> 
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