* [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV
2018-11-09 9:39 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
@ 2018-11-09 9:39 ` Stanislav Lisovskiy
2018-11-20 14:27 ` Ville Syrjälä
2018-11-09 9:39 ` [PATCH v12 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Stanislav Lisovskiy @ 2018-11-09 9:39 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, martin.peres, dri-devel
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
v11: Fixed rebase conflict, caused by added new formats to drm-tip
meanwhile.
Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index f523948c82b1..94d358eb0b8d 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -237,6 +237,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_X0L2, .depth = 0, .num_planes = 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e7e48f1f4a74..0b44260a5ee9 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,6 +151,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* packed YCbCr420 2x2 tiled formats
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV
2018-11-09 9:39 ` [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
@ 2018-11-20 14:27 ` Ville Syrjälä
2019-07-26 17:36 ` Matt Roper
0 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2018-11-20 14:27 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, ville.syrjala, martin.peres, dri-devel
On Fri, Nov 09, 2018 at 11:39:15AM +0200, Stanislav Lisovskiy wrote:
> v5: This is YUV444 packed format same as AYUV, but without alpha,
> as supported by i915.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added is_yuv field initialization according to latest
> drm_fourcc format structure initialization changes.
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
>
> v11: Fixed rebase conflict, caused by added new formats to drm-tip
> meanwhile.
>
> Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Pushed this one to drm-misc-next. Thanks for the patch and review.
The i915 part won't apply properly in drm-misc-next, so we'll need
to wait until dinq and drm-misc-next are suitably aligned before
we push that one.
> ---
> drivers/gpu/drm/drm_fourcc.c | 1 +
> include/uapi/drm/drm_fourcc.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index f523948c82b1..94d358eb0b8d 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -237,6 +237,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_X0L2, .depth = 0, .num_planes = 1,
> .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
> .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index e7e48f1f4a74..0b44260a5ee9 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -151,6 +151,7 @@ extern "C" {
> #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>
> #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>
> /*
> * packed YCbCr420 2x2 tiled formats
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV
2018-11-20 14:27 ` Ville Syrjälä
@ 2019-07-26 17:36 ` Matt Roper
0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2019-07-26 17:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, ville.syrjala, martin.peres
On Tue, Nov 20, 2018 at 04:27:21PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 11:39:15AM +0200, Stanislav Lisovskiy wrote:
> > v5: This is YUV444 packed format same as AYUV, but without alpha,
> > as supported by i915.
> >
> > v6: Removed unneeded initializer for new XYUV format.
> >
> > v7: Added is_yuv field initialization according to latest
> > drm_fourcc format structure initialization changes.
> >
> > v8: Edited commit message to be more clear about skl+, renamed
> > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> > doesn't support per-pixel alpha. Fixed minor code issues.
> >
> > v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >
> > v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
> >
> > v11: Fixed rebase conflict, caused by added new formats to drm-tip
> > meanwhile.
> >
> > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> Pushed this one to drm-misc-next. Thanks for the patch and review.
>
> The i915 part won't apply properly in drm-misc-next, so we'll need
> to wait until dinq and drm-misc-next are suitably aligned before
> we push that one.
It looks like we forgot to ever go back and apply the i915 patch here.
Any plans to rebase/report it so we can get it landed?
Matt
>
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index f523948c82b1..94d358eb0b8d 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -237,6 +237,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
> > { .format = DRM_FORMAT_X0L2, .depth = 0, .num_planes = 1,
> > .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
> > .hsub = 2, .vsub = 2, .is_yuv = true },
> > + { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> > };
> >
> > unsigned int i;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index e7e48f1f4a74..0b44260a5ee9 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -151,6 +151,7 @@ extern "C" {
> > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
> >
> > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> > +#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> >
> > /*
> > * packed YCbCr420 2x2 tiled formats
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v12 2/2] drm/i915: Adding YUV444 packed format support for skl+
2018-11-09 9:39 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
2018-11-09 9:39 ` [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
@ 2018-11-09 9:39 ` Stanislav Lisovskiy
2018-11-09 9:50 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev10) Patchwork
2018-11-09 10:15 ` ✗ Fi.CI.BAT: failure " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Stanislav Lisovskiy @ 2018-11-09 9:39 UTC (permalink / raw)
To: intel-gfx; +Cc: stanislav.lisovskiy, ville.syrjala, martin.peres, dri-devel
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
v12: Fixed rebase conflicts
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 158cf4716d03..5d1facecda33 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6502,7 +6502,7 @@ enum {
#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
-#define PLANE_CTL_FORMAT_AYUV (8 << 24)
+#define PLANE_CTL_FORMAT_XYUV (8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 05125c7c2aa1..3af1ef26fdb7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2617,6 +2617,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV8888;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3493,6 +3495,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR2101010:
return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+ case DRM_FORMAT_XYUV8888:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -4964,6 +4968,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -14513,6 +14518,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_XYUV8888:
+ if (INTEL_GEN(dev_priv) < 9) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format, &format_name));
+ goto err;
+ }
+ break;
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1293182dbcb0..69188a8b899b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1725,6 +1725,7 @@ static const uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV8888,
};
static const uint32_t skl_planar_formats[] = {
@@ -1741,6 +1742,7 @@ static const uint32_t skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV8888,
};
static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1882,6 +1884,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV8888:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 8+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev10)
2018-11-09 9:39 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
2018-11-09 9:39 ` [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-11-09 9:39 ` [PATCH v12 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
@ 2018-11-09 9:50 ` Patchwork
2018-11-09 10:15 ` ✗ Fi.CI.BAT: failure " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-11-09 9:50 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev10)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6fceb8451e96 drm: Introduce new DRM_FORMAT_XYUV
-:36: WARNING:LONG_LINE: line over 100 characters
#36: FILE: drivers/gpu/drm/drm_fourcc.c:240:
+ { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
total: 0 errors, 2 warnings, 0 checks, 14 lines checked
314594adeb74 drm/i915: Adding YUV444 packed format support for skl+
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* ✗ Fi.CI.BAT: failure for Add XYUV format support (rev10)
2018-11-09 9:39 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
` (2 preceding siblings ...)
2018-11-09 9:50 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev10) Patchwork
@ 2018-11-09 10:15 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-11-09 10:15 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Add XYUV format support (rev10)
URL : https://patchwork.freedesktop.org/series/48007/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5109 -> Patchwork_10790 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10790 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10790, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/10/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10790:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_hangcheck:
fi-bwr-2160: PASS -> DMESG-FAIL
igt@drv_selftest@live_hugepages:
fi-skl-6700k2: PASS -> INCOMPLETE
==== Warnings ====
igt@kms_chamelium@common-hpd-after-suspend:
fi-skl-6700k2: WARN (fdo#108680) -> TIMEOUT
== Known issues ==
Here are the changes found in Patchwork_10790 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_execlists:
fi-apl-guc: PASS -> INCOMPLETE (fdo#103927, fdo#106693)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@drv_selftest@live_contexts:
fi-bsw-n3050: DMESG-FAIL (fdo#108626) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108626 https://bugs.freedesktop.org/show_bug.cgi?id=108626
fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680
== Participating hosts (53 -> 46) ==
Additional (1): fi-pnv-d510
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-icl-u
== Build changes ==
* Linux: CI_DRM_5109 -> Patchwork_10790
CI_DRM_5109: fd007cc63a9d60ac2a6f966a3c790e710aa8ca94 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10790: 314594adeb74eed6f89957ef942137d89d87bbc4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
314594adeb74 drm/i915: Adding YUV444 packed format support for skl+
6fceb8451e96 drm: Introduce new DRM_FORMAT_XYUV
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10790/issues.html
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* [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV
2018-11-08 11:46 [PATCH v12 0/2] Add XYUV format support Stanislav Lisovskiy
@ 2018-11-08 11:46 ` Stanislav Lisovskiy
0 siblings, 0 replies; 8+ messages in thread
From: Stanislav Lisovskiy @ 2018-11-08 11:46 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, martin.peres, dri-devel
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 3934527e09dc..965464e550e1 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -225,6 +225,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0cd40ebfa1b1..e14aaeb7ad46 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,6 +151,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* 2 plane RGB + A
--
2.17.1
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