Re: [PATCH 6/7] drm/i915/icl: Support co-existence between per-context SSEU and OA

Joonas Lahtinen
2019-01-08T13:59:49Z

To be squashed to patch 3. We don't want a broken tree for bisecting.

When squashed:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas

Quoting Tvrtko Ursulin (2019-01-08 13:22:51)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> When OA is active we want to lock the powergating configuration, but on
> Icelake, users like the media stack will have issues if we lock to the
> full device configuration.
>
> Instead lock to a subset of (sub)slices which are currently a known
> working configuration for all users.
>
> v2:
> * Fix commit message spelling.
>
> v3:
> Lionel:
> * Add bspec reference.
> * Fix spelling in comment.
>
> v4:
> * Rebase for IS_GEN changes.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Bspec: 21140
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++-----
> 1 file changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 2ce55bb64fca..e9c6876a5897 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2341,13 +2341,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
>
> /*
> * If i915/perf is active, we want a stable powergating configuration
> - * on the system. The most natural configuration to take in that case
> - * is the default (i.e maximum the hardware can do).
> + * on the system.
> + *
> + * We could choose full enablement, but on ICL we know there are use
> + * cases which disable slices for functional, apart for performance
> + * reasons. So in this case we select a known stable subset.
> */
> - if (unlikely(i915->perf.oa.exclusive_stream))
> - ctx_sseu = intel_device_default_sseu(i915);
> - else
> + if (!i915->perf.oa.exclusive_stream) {
> ctx_sseu = *req_sseu;
> + } else {
> + ctx_sseu = intel_device_default_sseu(i915);
> +
> + if (IS_GEN(i915, 11)) {
> + /*
> + * We only need subslice count so it doesn't matter
> + * which ones we select - just turn off low bits in the
> + * amount of half of all available subslices per slice.
> + */
> + ctx_sseu.subslice_mask =
> + ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
> + ctx_sseu.slice_mask = 0x1;
> + }
> + }
>
> slices = hweight8(ctx_sseu.slice_mask);
> subslices = hweight8(ctx_sseu.subslice_mask);
> --
> 2.19.1
>
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