[PATCH v2 00/13] Enable/disable gamma/csc dynamically and fix C8

Ville Syrjala
2019-02-05T16:08:52Z

Rebase of the gamma/csc series. The last patch is new to fix Matt's
observation that we need something to configure the DSPCNTR gamma/csc
bits correctly during modeset.

Ville Syrjälä (13):
drm/i915: Split the gamma/csc enable bits from the plane_ctl()
function
drm/i915: Precompute gamma_mode
drm/i915: Constify the state arguments to the color management stuff
drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()
drm/i915: Split color mgmt based on single vs. double buffered
registers
drm/i915: Move LUT programming to happen after vblank waits
drm/i915: Populate gamma_mode for all platforms
drm/i915: Track pipe gamma enable/disable in crtc state
drm/i915: Track pipe csc enable in crtc state
drm/i915: Turn off pipe gamma when it's not needed
drm/i915: Turn off pipe CSC when it's not needed
drm/i915: Disable pipe gamma when C8 pixel format is used
drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()

drivers/gpu/drm/i915/i915_drv.h | 16 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 5 +
drivers/gpu/drm/i915/intel_color.c | 381 ++++++++++++++--------
drivers/gpu/drm/i915/intel_display.c | 283 ++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 14 +-
drivers/gpu/drm/i915/intel_sprite.c | 67 +++-
7 files changed, 568 insertions(+), 212 deletions(-)