From mboxrd@z Thu Jan  1 00:00:00 1970
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Subject: Re: [PULL] gvt-fixes
Date: Thu, 4 Apr 2019 08:32:06 +0800
Message-ID: <20190404003206.GA8327@zhen-hp.sh.intel.com>
References: <20190402094037.GB2322@zhen-hp.sh.intel.com>
 <20190404001237.GA18158@intel.com>
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To: Rodrigo Vivi <rodrigo.vivi@intel.com>
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On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> >=20
> > Hi,
> >=20
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload create and one kerneldoc
> > fix which I missed to include before.
>=20
> dim: 000d38970e98 ("drm/i915/gvt: Correct the calculation of plane size")=
: Fixes: SHA1 needs at least 12 digits:
> dim:     e546e281d33("drm/i915/gvt: Dmabuf support for GVT-g")
> dim: ERROR: issues in commits detected, aborting
>=20
> Is it something you could fix on your side without having
> to by-pass dim this time?
>=20

Sorry about that, looks people still doesn't generate Fixes tag
properly. I'll fix that and resend.

--=20
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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