From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: [PULL] gvt-next Date: Tue, 9 Apr 2019 12:05:00 +0800 Message-ID: <20190409040500.GM17995@zhen-hp.sh.intel.com> Reply-To: Zhenyu Wang Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0556166390==" Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Joonas Lahtinen , "Vivi, Rodrigo" , Jani Nikula Cc: intel-gfx , intel-gvt-dev , "Lv, Zhiyuan" , "Yuan, Hang" List-Id: intel-gfx@lists.freedesktop.org --===============0556166390== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="NqSa+Xr3J/G6Hhls" Content-Disposition: inline --NqSa+Xr3J/G6Hhls Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, This includes various code refinement and cleanups, with proper async/sync display flip handling, and also some changes required for recent drm-intel-next as guest kernel, details below. Thanks -- The following changes since commit a01b2c6f47d86c7d1a9fa822b3b91ec233b61784: drm/i915: Update DRIVER_DATE to 20190328 (2019-03-28 14:41:55 +0200) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-next-2019-04-09 for you to fetch changes up to 201e3e8580bb4924d0cc29fc3841ea5782401b46: drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list (201= 9-04-03 16:37:20 +0800) ---------------------------------------------------------------- gvt-next-2019-04-09 - Refine range of MCHBAR snapshot (Yakui) - Refine out-of-sync page struct (Yakui) - Remove unused vGPU sreg (Yan) - Refind MMIO reg names (Xiaolin) - Proper handling of sync/async flip (Colin) - Proper handling of PIPE_CONTROL/MI_FLUSH_DW index mode (Xiaolin) - EXCC reg mask fix (Colin) ---------------------------------------------------------------- Colin Xu (5): drm/i915/gvt: Use consist max display pipe numbers as i915 definition drm/i915/gvt: Add macro define for mmio 0x50080 and gvt flip event drm/i915/gvt: Enable synchronous flip on handling MI_DISPLAY_FLIP drm/i915/gvt: Enable async flip on plane surface mmio writes drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list Xiaolin Zhang (2): drm/i915/gvt: replaced register address with name drm/i915/gvt: addressed guest GPU hang with HWS index mode Yan Zhao (1): drm/i915/gvt: remove the unused sreg Zhao Yakui (2): drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize g= vt-g boot time drm/i915/gvt: Refine the combined intel_vgpu_oos_page struct to save = memory Zhenyu Wang (1): Merge tag 'drm-intel-next-2019-03-28' into gvt-next drivers/gpu/drm/i915/gvt/cmd_parser.c | 30 +++++- drivers/gpu/drm/i915/gvt/display.c | 1 - drivers/gpu/drm/i915/gvt/gtt.c | 7 ++ drivers/gpu/drm/i915/gvt/gtt.h | 2 +- drivers/gpu/drm/i915/gvt/gvt.h | 9 +- drivers/gpu/drm/i915/gvt/handlers.c | 159 +++++++++++++++++++---------= ---- drivers/gpu/drm/i915/gvt/mmio.c | 8 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 4 +- drivers/gpu/drm/i915/gvt/reg.h | 34 +++++++ 9 files changed, 172 insertions(+), 82 deletions(-) --=20 Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --NqSa+Xr3J/G6Hhls Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQTXuabgHDW6LPt9CICxBBozTXgYJwUCXKwZ6wAKCRCxBBozTXgY J5kYAKCK9l+/xI5yJV9oWRAefrABRMTSiACeNtWE1rT/RCteDwKNR4wRkKopLhw= =GfTU -----END PGP SIGNATURE----- --NqSa+Xr3J/G6Hhls-- --===============0556166390== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============0556166390==--