* [PATCH 1/5] drm/i915: refactor the IRQ init/reset macros
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
@ 2019-04-10 23:53 ` Paulo Zanoni
2019-04-10 23:53 ` [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros Paulo Zanoni
` (7 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-10 23:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The whole point of having macros here is for the token pasting
necessary to automatically have IMR, IIR and IER selected. We don't
really need or want all the inlining that happens as a consequence.
The good thing about the current code is that it works regardless of
the relative offsets between these registers (they change after gen4,
with the usual VLV/CHV exceptions).
One thing which we can do is to split the logic of what we do with
imr/ier/iir to functions separate from the macros that pick them.
That's what we do in this commit. This allows us to get rid of the
gen8 duplicates and also all the inlining:
add/remove: 2/0 grow/shrink: 0/21 up/down: 384/-5949 (-5565)
Function old new delta
gen3_irq_reset - 233 +233
gen3_irq_init - 151 +151
i8xx_irq_postinstall 459 442 -17
gen11_irq_postinstall 804 744 -60
ironlake_irq_postinstall 450 353 -97
vlv_display_irq_postinstall 348 245 -103
i965_irq_postinstall 378 272 -106
i915_irq_postinstall 333 227 -106
gen8_irq_power_well_post_enable 374 240 -134
ironlake_irq_reset 397 218 -179
vlv_display_irq_reset 616 433 -183
i965_irq_reset 374 180 -194
cherryview_irq_reset 379 185 -194
i915_irq_reset 407 209 -198
ibx_irq_reset 332 133 -199
gen5_gt_irq_postinstall 533 332 -201
gen8_irq_power_well_pre_disable 434 204 -230
gen8_gt_irq_postinstall 469 196 -273
gen8_de_irq_postinstall 1200 836 -364
gen5_gt_irq_reset 471 76 -395
gen8_gt_irq_reset 775 99 -676
gen8_irq_reset 1100 333 -767
gen11_irq_reset 1959 686 -1273
Total: Before=2259222, After=2253657, chg -0.25%
v2:
- Make checkpatch happy with a temporary which_ (Checkpatch).
- Reorder the arguments for the INIT macros (Ville).
- Correctly explain when the register offsets change in the commit
message (Ville).
- Use more line breaks in the macro calls to make the arguments look
a little more organized/readable.
- Update the bloat-o-meter output (minor change only).
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 136 ++++++++++++++++++++------------
1 file changed, 86 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8d8935d71180..60a3f4203ac3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,36 +136,48 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
};
-/* IIR can theoretically queue up two events. Be paranoid. */
-#define GEN8_IRQ_RESET_NDX(type, which) do { \
- I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
- POSTING_READ(GEN8_##type##_IMR(which)); \
- I915_WRITE(GEN8_##type##_IER(which), 0); \
- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
- POSTING_READ(GEN8_##type##_IIR(which)); \
- I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
- POSTING_READ(GEN8_##type##_IIR(which)); \
-} while (0)
-
-#define GEN3_IRQ_RESET(type) do { \
- I915_WRITE(type##IMR, 0xffffffff); \
- POSTING_READ(type##IMR); \
- I915_WRITE(type##IER, 0); \
- I915_WRITE(type##IIR, 0xffffffff); \
- POSTING_READ(type##IIR); \
- I915_WRITE(type##IIR, 0xffffffff); \
- POSTING_READ(type##IIR); \
-} while (0)
-
-#define GEN2_IRQ_RESET(type) do { \
- I915_WRITE16(type##IMR, 0xffff); \
- POSTING_READ16(type##IMR); \
- I915_WRITE16(type##IER, 0); \
- I915_WRITE16(type##IIR, 0xffff); \
- POSTING_READ16(type##IIR); \
- I915_WRITE16(type##IIR, 0xffff); \
- POSTING_READ16(type##IIR); \
-} while (0)
+static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
+ i915_reg_t iir, i915_reg_t ier)
+{
+ I915_WRITE(imr, 0xffffffff);
+ POSTING_READ(imr);
+
+ I915_WRITE(ier, 0);
+
+ /* IIR can theoretically queue up two events. Be paranoid. */
+ I915_WRITE(iir, 0xffffffff);
+ POSTING_READ(iir);
+ I915_WRITE(iir, 0xffffffff);
+ POSTING_READ(iir);
+}
+
+static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
+ i915_reg_t iir, i915_reg_t ier)
+{
+ I915_WRITE16(imr, 0xffff);
+ POSTING_READ16(imr);
+
+ I915_WRITE16(ier, 0);
+
+ /* IIR can theoretically queue up two events. Be paranoid. */
+ I915_WRITE16(iir, 0xffff);
+ POSTING_READ16(iir);
+ I915_WRITE16(iir, 0xffff);
+ POSTING_READ16(iir);
+}
+
+#define GEN8_IRQ_RESET_NDX(type, which) \
+({ \
+ unsigned int which_ = which; \
+ gen3_irq_reset(dev_priv, GEN8_##type##_IMR(which_), \
+ GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
+})
+
+#define GEN3_IRQ_RESET(type) \
+ gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
+
+#define GEN2_IRQ_RESET(type) \
+ gen2_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
@@ -202,26 +214,50 @@ static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
POSTING_READ16(reg);
}
-#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
- gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
- I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
- I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
- POSTING_READ(GEN8_##type##_IMR(which)); \
-} while (0)
-
-#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
- gen3_assert_iir_is_zero(dev_priv, type##IIR); \
- I915_WRITE(type##IER, (ier_val)); \
- I915_WRITE(type##IMR, (imr_val)); \
- POSTING_READ(type##IMR); \
-} while (0)
-
-#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
- gen2_assert_iir_is_zero(dev_priv, type##IIR); \
- I915_WRITE16(type##IER, (ier_val)); \
- I915_WRITE16(type##IMR, (imr_val)); \
- POSTING_READ16(type##IMR); \
-} while (0)
+static void gen3_irq_init(struct drm_i915_private *dev_priv,
+ i915_reg_t imr, u32 imr_val,
+ i915_reg_t ier, u32 ier_val,
+ i915_reg_t iir)
+{
+ gen3_assert_iir_is_zero(dev_priv, iir);
+
+ I915_WRITE(ier, ier_val);
+ I915_WRITE(imr, imr_val);
+ POSTING_READ(imr);
+}
+
+static void gen2_irq_init(struct drm_i915_private *dev_priv,
+ i915_reg_t imr, u32 imr_val,
+ i915_reg_t ier, u32 ier_val,
+ i915_reg_t iir)
+{
+ gen2_assert_iir_is_zero(dev_priv, iir);
+
+ I915_WRITE16(ier, ier_val);
+ I915_WRITE16(imr, imr_val);
+ POSTING_READ16(imr);
+}
+
+#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
+({ \
+ unsigned int which_ = which; \
+ gen3_irq_init(dev_priv, \
+ GEN8_##type##_IMR(which_), imr_val, \
+ GEN8_##type##_IER(which_), ier_val, \
+ GEN8_##type##_IIR(which_)); \
+})
+
+#define GEN3_IRQ_INIT(type, imr_val, ier_val) \
+ gen3_irq_init(dev_priv, \
+ type##IMR, imr_val, \
+ type##IER, ier_val, \
+ type##IIR)
+
+#define GEN2_IRQ_INIT(type, imr_val, ier_val) \
+ gen2_irq_init(dev_priv, \
+ type##IMR, imr_val, \
+ type##IER, ier_val, \
+ type##IIR)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
2019-04-10 23:53 ` [PATCH 1/5] drm/i915: refactor the IRQ init/reset macros Paulo Zanoni
@ 2019-04-10 23:53 ` Paulo Zanoni
2019-04-11 23:31 ` Daniele Ceraolo Spurio
2019-04-10 23:53 ` [PATCH 3/5] drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers Paulo Zanoni
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-10 23:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Like the gen3+ macros, the gen2 versions of the IRQ initialization
macros take the register name in the 'type' argument. But gen2 only
has one set of registers, so there's really no need to specify the
type. This commit removes the type argument and uses the registers
directly instead of passing them through variables.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++------------------
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 60a3f4203ac3..b1f1db2bd879 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -151,19 +151,18 @@ static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
POSTING_READ(iir);
}
-static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
- i915_reg_t iir, i915_reg_t ier)
+static void gen2_irq_reset(struct drm_i915_private *dev_priv)
{
- I915_WRITE16(imr, 0xffff);
- POSTING_READ16(imr);
+ I915_WRITE16(IMR, 0xffff);
+ POSTING_READ16(IMR);
- I915_WRITE16(ier, 0);
+ I915_WRITE16(IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- I915_WRITE16(iir, 0xffff);
- POSTING_READ16(iir);
- I915_WRITE16(iir, 0xffff);
- POSTING_READ16(iir);
+ I915_WRITE16(IIR, 0xffff);
+ POSTING_READ16(IIR);
+ I915_WRITE16(IIR, 0xffff);
+ POSTING_READ16(IIR);
}
#define GEN8_IRQ_RESET_NDX(type, which) \
@@ -176,8 +175,8 @@ static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
#define GEN3_IRQ_RESET(type) \
gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET(type) \
- gen2_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
+#define GEN2_IRQ_RESET() \
+ gen2_irq_reset(dev_priv)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
@@ -198,20 +197,19 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
POSTING_READ(reg);
}
-static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
+static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
{
- u16 val = I915_READ16(reg);
+ u16 val = I915_READ16(IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
- i915_mmio_reg_offset(reg), val);
- I915_WRITE16(reg, 0xffff);
- POSTING_READ16(reg);
- I915_WRITE16(reg, 0xffff);
- POSTING_READ16(reg);
+ i915_mmio_reg_offset(IIR), val);
+ I915_WRITE16(IIR, 0xffff);
+ POSTING_READ16(IIR);
+ I915_WRITE16(IIR, 0xffff);
+ POSTING_READ16(IIR);
}
static void gen3_irq_init(struct drm_i915_private *dev_priv,
@@ -227,15 +225,13 @@ static void gen3_irq_init(struct drm_i915_private *dev_priv,
}
static void gen2_irq_init(struct drm_i915_private *dev_priv,
- i915_reg_t imr, u32 imr_val,
- i915_reg_t ier, u32 ier_val,
- i915_reg_t iir)
+ u32 imr_val, u32 ier_val)
{
- gen2_assert_iir_is_zero(dev_priv, iir);
+ gen2_assert_iir_is_zero(dev_priv);
- I915_WRITE16(ier, ier_val);
- I915_WRITE16(imr, imr_val);
- POSTING_READ16(imr);
+ I915_WRITE16(IER, ier_val);
+ I915_WRITE16(IMR, imr_val);
+ POSTING_READ16(IMR);
}
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
@@ -253,11 +249,8 @@ static void gen2_irq_init(struct drm_i915_private *dev_priv,
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(type, imr_val, ier_val) \
- gen2_irq_init(dev_priv, \
- type##IMR, imr_val, \
- type##IER, ier_val, \
- type##IIR)
+#define GEN2_IRQ_INIT(imr_val, ier_val) \
+ gen2_irq_init(dev_priv, imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -4247,7 +4240,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ GEN2_IRQ_INIT(dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros
2019-04-10 23:53 ` [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros Paulo Zanoni
@ 2019-04-11 23:31 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 15+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-04-11 23:31 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx
On 4/10/19 4:53 PM, Paulo Zanoni wrote:
> Like the gen3+ macros, the gen2 versions of the IRQ initialization
> macros take the register name in the 'type' argument. But gen2 only
> has one set of registers, so there's really no need to specify the
> type. This commit removes the type argument and uses the registers
> directly instead of passing them through variables.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++------------------
> 1 file changed, 25 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 60a3f4203ac3..b1f1db2bd879 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -151,19 +151,18 @@ static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
> POSTING_READ(iir);
> }
>
> -static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
> - i915_reg_t iir, i915_reg_t ier)
> +static void gen2_irq_reset(struct drm_i915_private *dev_priv)
> {
> - I915_WRITE16(imr, 0xffff);
> - POSTING_READ16(imr);
> + I915_WRITE16(IMR, 0xffff);
> + POSTING_READ16(IMR);
>
> - I915_WRITE16(ier, 0);
> + I915_WRITE16(IER, 0);
>
> /* IIR can theoretically queue up two events. Be paranoid. */
> - I915_WRITE16(iir, 0xffff);
> - POSTING_READ16(iir);
> - I915_WRITE16(iir, 0xffff);
> - POSTING_READ16(iir);
> + I915_WRITE16(IIR, 0xffff);
> + POSTING_READ16(IIR);
> + I915_WRITE16(IIR, 0xffff);
> + POSTING_READ16(IIR);
> }
>
> #define GEN8_IRQ_RESET_NDX(type, which) \
> @@ -176,8 +175,8 @@ static void gen2_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
> #define GEN3_IRQ_RESET(type) \
> gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
>
> -#define GEN2_IRQ_RESET(type) \
> - gen2_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
> +#define GEN2_IRQ_RESET() \
> + gen2_irq_reset(dev_priv)
We could potentially drop the macro entirely now since it doesn't really
add any functional value. The same applies for GEN2_IRQ_INIT.
However, I see the argument for keeping things consistent and use the
same "look" across gens, so with or without the change:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
>
> /*
> * We should clear IMR at preinstall/uninstall, and just check at postinstall.
> @@ -198,20 +197,19 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
> POSTING_READ(reg);
> }
>
> -static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
> - i915_reg_t reg)
> +static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
> {
> - u16 val = I915_READ16(reg);
> + u16 val = I915_READ16(IIR);
>
> if (val == 0)
> return;
>
> WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
> - i915_mmio_reg_offset(reg), val);
> - I915_WRITE16(reg, 0xffff);
> - POSTING_READ16(reg);
> - I915_WRITE16(reg, 0xffff);
> - POSTING_READ16(reg);
> + i915_mmio_reg_offset(IIR), val);
> + I915_WRITE16(IIR, 0xffff);
> + POSTING_READ16(IIR);
> + I915_WRITE16(IIR, 0xffff);
> + POSTING_READ16(IIR);
> }
>
> static void gen3_irq_init(struct drm_i915_private *dev_priv,
> @@ -227,15 +225,13 @@ static void gen3_irq_init(struct drm_i915_private *dev_priv,
> }
>
> static void gen2_irq_init(struct drm_i915_private *dev_priv,
> - i915_reg_t imr, u32 imr_val,
> - i915_reg_t ier, u32 ier_val,
> - i915_reg_t iir)
> + u32 imr_val, u32 ier_val)
> {
> - gen2_assert_iir_is_zero(dev_priv, iir);
> + gen2_assert_iir_is_zero(dev_priv);
>
> - I915_WRITE16(ier, ier_val);
> - I915_WRITE16(imr, imr_val);
> - POSTING_READ16(imr);
> + I915_WRITE16(IER, ier_val);
> + I915_WRITE16(IMR, imr_val);
> + POSTING_READ16(IMR);
> }
>
> #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
> @@ -253,11 +249,8 @@ static void gen2_irq_init(struct drm_i915_private *dev_priv,
> type##IER, ier_val, \
> type##IIR)
>
> -#define GEN2_IRQ_INIT(type, imr_val, ier_val) \
> - gen2_irq_init(dev_priv, \
> - type##IMR, imr_val, \
> - type##IER, ier_val, \
> - type##IIR)
> +#define GEN2_IRQ_INIT(imr_val, ier_val) \
> + gen2_irq_init(dev_priv, imr_val, ier_val)
>
> static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
> static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
> @@ -4247,7 +4240,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
> I915_MASTER_ERROR_INTERRUPT |
> I915_USER_INTERRUPT;
>
> - GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
> + GEN2_IRQ_INIT(dev_priv->irq_mask, enable_mask);
>
> /* Interrupt setup is already guaranteed to be single-threaded, this is
> * just to make the assert_spin_locked check happy. */
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/5] drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
2019-04-10 23:53 ` [PATCH 1/5] drm/i915: refactor the IRQ init/reset macros Paulo Zanoni
2019-04-10 23:53 ` [PATCH 2/5] drm/i915: don't specify the IRQ register in the gen2 macros Paulo Zanoni
@ 2019-04-10 23:53 ` Paulo Zanoni
2019-04-12 7:33 ` Ville Syrjälä
2019-04-10 23:53 ` [PATCH 4/5] drm/i915: convert the IRQ initialization functions to intel_uncore Paulo Zanoni
` (5 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-10 23:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
This discussion started because we use token pasting in the
GEN{2,3}_IRQ_INIT and GEN{2,3}_IRQ_RESET macros, so gen2-4 passes an
empty argument to those macros, making the code a little weird. The
original proposal was to just add a comment as the empty argument, but
Ville suggested we just add a prefix to the registers, and that indeed
sounds like a more elegant solution.
Now doing this is kinda against our rules for register naming since we
only add gens or platform names as register prefixes when the given
gen/platform changes a register that already existed before. On the
other hand, we have so many instances of IIR/IMR in comments that
adding a prefix would make the users of these register more easily
findable, in addition to make our token pasting macros actually
readable. So IMHO opening an exception here is worth it.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++-------------
drivers/gpu/drm/i915/i915_reg.h | 8 ++--
drivers/gpu/drm/i915/i915_reset.c | 3 +-
drivers/gpu/drm/i915/intel_overlay.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++---
7 files changed, 44 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 77b3252bdb2e..5823ffb17821 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -833,11 +833,11 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
} else if (!HAS_PCH_SPLIT(dev_priv)) {
seq_printf(m, "Interrupt enable: %08x\n",
- I915_READ(IER));
+ I915_READ(GEN2_IER));
seq_printf(m, "Interrupt identity: %08x\n",
- I915_READ(IIR));
+ I915_READ(GEN2_IIR));
seq_printf(m, "Interrupt mask: %08x\n",
- I915_READ(IMR));
+ I915_READ(GEN2_IMR));
for_each_pipe(dev_priv, pipe)
seq_printf(m, "Pipe %c stat: %08x\n",
pipe_name(pipe),
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 43b68fdc8967..f51ff683dd2e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1635,9 +1635,9 @@ static void capture_reg_state(struct i915_gpu_state *error)
error->gtier[0] = I915_READ(GTIER);
error->ngtier = 1;
} else if (IS_GEN(dev_priv, 2)) {
- error->ier = I915_READ16(IER);
+ error->ier = I915_READ16(GEN2_IER);
} else if (!IS_VALLEYVIEW(dev_priv)) {
- error->ier = I915_READ(IER);
+ error->ier = I915_READ(GEN2_IER);
}
error->eir = I915_READ(EIR);
error->pgtbl_er = I915_READ(PGTBL_ER);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1f1db2bd879..2910b06913af 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -153,16 +153,16 @@ static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
static void gen2_irq_reset(struct drm_i915_private *dev_priv)
{
- I915_WRITE16(IMR, 0xffff);
- POSTING_READ16(IMR);
+ I915_WRITE16(GEN2_IMR, 0xffff);
+ POSTING_READ16(GEN2_IMR);
- I915_WRITE16(IER, 0);
+ I915_WRITE16(GEN2_IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- I915_WRITE16(IIR, 0xffff);
- POSTING_READ16(IIR);
- I915_WRITE16(IIR, 0xffff);
- POSTING_READ16(IIR);
+ I915_WRITE16(GEN2_IIR, 0xffff);
+ POSTING_READ16(GEN2_IIR);
+ I915_WRITE16(GEN2_IIR, 0xffff);
+ POSTING_READ16(GEN2_IIR);
}
#define GEN8_IRQ_RESET_NDX(type, which) \
@@ -199,17 +199,17 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
{
- u16 val = I915_READ16(IIR);
+ u16 val = I915_READ16(GEN2_IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
- i915_mmio_reg_offset(IIR), val);
- I915_WRITE16(IIR, 0xffff);
- POSTING_READ16(IIR);
- I915_WRITE16(IIR, 0xffff);
- POSTING_READ16(IIR);
+ i915_mmio_reg_offset(GEN2_IIR), val);
+ I915_WRITE16(GEN2_IIR, 0xffff);
+ POSTING_READ16(GEN2_IIR);
+ I915_WRITE16(GEN2_IIR, 0xffff);
+ POSTING_READ16(GEN2_IIR);
}
static void gen3_irq_init(struct drm_i915_private *dev_priv,
@@ -229,9 +229,9 @@ static void gen2_irq_init(struct drm_i915_private *dev_priv,
{
gen2_assert_iir_is_zero(dev_priv);
- I915_WRITE16(IER, ier_val);
- I915_WRITE16(IMR, imr_val);
- POSTING_READ16(IMR);
+ I915_WRITE16(GEN2_IER, ier_val);
+ I915_WRITE16(GEN2_IMR, imr_val);
+ POSTING_READ16(GEN2_IMR);
}
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
@@ -4344,7 +4344,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
u16 eir = 0, eir_stuck = 0;
u16 iir;
- iir = I915_READ16(IIR);
+ iir = I915_READ16(GEN2_IIR);
if (iir == 0)
break;
@@ -4357,7 +4357,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
if (iir & I915_MASTER_ERROR_INTERRUPT)
i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
- I915_WRITE16(IIR, iir);
+ I915_WRITE16(GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
@@ -4384,7 +4384,7 @@ static void i915_irq_reset(struct drm_device *dev)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET();
+ GEN3_IRQ_RESET(GEN2_);
}
static int i915_irq_postinstall(struct drm_device *dev)
@@ -4416,7 +4416,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4448,7 +4448,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
u32 hotplug_status = 0;
u32 iir;
- iir = I915_READ(IIR);
+ iir = I915_READ(GEN2_IIR);
if (iir == 0)
break;
@@ -4465,7 +4465,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
- I915_WRITE(IIR, iir);
+ I915_WRITE(GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
@@ -4493,7 +4493,7 @@ static void i965_irq_reset(struct drm_device *dev)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET();
+ GEN3_IRQ_RESET(GEN2_);
}
static int i965_irq_postinstall(struct drm_device *dev)
@@ -4536,7 +4536,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
- GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4594,7 +4594,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
u32 hotplug_status = 0;
u32 iir;
- iir = I915_READ(IIR);
+ iir = I915_READ(GEN2_IIR);
if (iir == 0)
break;
@@ -4610,7 +4610,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
- I915_WRITE(IIR, iir);
+ I915_WRITE(GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c206e803ab3..6a150243cabb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2713,10 +2713,10 @@ enum i915_power_well_id {
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
#define SCPD0 _MMIO(0x209c) /* 915+ only */
-#define IER _MMIO(0x20a0)
-#define IIR _MMIO(0x20a4)
-#define IMR _MMIO(0x20a8)
-#define ISR _MMIO(0x20ac)
+#define GEN2_IER _MMIO(0x20a0)
+#define GEN2_IIR _MMIO(0x20a4)
+#define GEN2_IMR _MMIO(0x20a8)
+#define GEN2_ISR _MMIO(0x20ac)
#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
#define GINT_DIS (1 << 22)
#define GCFG_DIS (1 << 8)
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index 68875ba43b8d..b75ac660c3c2 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -1223,7 +1223,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915)
*/
DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
- intel_uncore_write(uncore, IIR, I915_MASTER_ERROR_INTERRUPT);
+ intel_uncore_write(uncore, GEN2_IIR,
+ I915_MASTER_ERROR_INTERRUPT);
}
if (INTEL_GEN(i915) >= 8) {
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index a882b8d42bd9..eb317759b5d3 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -446,7 +446,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
if (!overlay->old_vma)
return 0;
- if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
+ if (I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
/* synchronous slowpath */
struct i915_request *rq;
@@ -1430,7 +1430,7 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
return NULL;
error->dovsta = I915_READ(DOVSTA);
- error->isr = I915_READ(ISR);
+ error->isr = I915_READ(GEN2_ISR);
error->base = overlay->flip_addr;
memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index af35f99c5940..029fd8ec1857 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -977,15 +977,15 @@ static void
i9xx_irq_enable(struct intel_engine_cs *engine)
{
engine->i915->irq_mask &= ~engine->irq_enable_mask;
- intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
- intel_uncore_posting_read_fw(engine->uncore, IMR);
+ intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
+ intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
}
static void
i9xx_irq_disable(struct intel_engine_cs *engine)
{
engine->i915->irq_mask |= engine->irq_enable_mask;
- intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
+ intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
}
static void
@@ -994,7 +994,7 @@ i8xx_irq_enable(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
dev_priv->irq_mask &= ~engine->irq_enable_mask;
- I915_WRITE16(IMR, dev_priv->irq_mask);
+ I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
POSTING_READ16(RING_IMR(engine->mmio_base));
}
@@ -1004,7 +1004,7 @@ i8xx_irq_disable(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
dev_priv->irq_mask |= engine->irq_enable_mask;
- I915_WRITE16(IMR, dev_priv->irq_mask);
+ I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
}
static int
--
2.20.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 3/5] drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
2019-04-10 23:53 ` [PATCH 3/5] drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers Paulo Zanoni
@ 2019-04-12 7:33 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2019-04-12 7:33 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
On Wed, Apr 10, 2019 at 04:53:42PM -0700, Paulo Zanoni wrote:
> This discussion started because we use token pasting in the
> GEN{2,3}_IRQ_INIT and GEN{2,3}_IRQ_RESET macros, so gen2-4 passes an
> empty argument to those macros, making the code a little weird. The
> original proposal was to just add a comment as the empty argument, but
> Ville suggested we just add a prefix to the registers, and that indeed
> sounds like a more elegant solution.
>
> Now doing this is kinda against our rules for register naming since we
> only add gens or platform names as register prefixes when the given
> gen/platform changes a register that already existed before. On the
> other hand, we have so many instances of IIR/IMR in comments that
> adding a prefix would make the users of these register more easily
> findable, in addition to make our token pasting macros actually
> readable. So IMHO opening an exception here is worth it.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++-------------
> drivers/gpu/drm/i915/i915_reg.h | 8 ++--
> drivers/gpu/drm/i915/i915_reset.c | 3 +-
> drivers/gpu/drm/i915/intel_overlay.c | 4 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++---
> 7 files changed, 44 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 77b3252bdb2e..5823ffb17821 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -833,11 +833,11 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>
> } else if (!HAS_PCH_SPLIT(dev_priv)) {
> seq_printf(m, "Interrupt enable: %08x\n",
> - I915_READ(IER));
> + I915_READ(GEN2_IER));
> seq_printf(m, "Interrupt identity: %08x\n",
> - I915_READ(IIR));
> + I915_READ(GEN2_IIR));
> seq_printf(m, "Interrupt mask: %08x\n",
> - I915_READ(IMR));
> + I915_READ(GEN2_IMR));
> for_each_pipe(dev_priv, pipe)
> seq_printf(m, "Pipe %c stat: %08x\n",
> pipe_name(pipe),
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 43b68fdc8967..f51ff683dd2e 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1635,9 +1635,9 @@ static void capture_reg_state(struct i915_gpu_state *error)
> error->gtier[0] = I915_READ(GTIER);
> error->ngtier = 1;
> } else if (IS_GEN(dev_priv, 2)) {
> - error->ier = I915_READ16(IER);
> + error->ier = I915_READ16(GEN2_IER);
> } else if (!IS_VALLEYVIEW(dev_priv)) {
> - error->ier = I915_READ(IER);
> + error->ier = I915_READ(GEN2_IER);
> }
> error->eir = I915_READ(EIR);
> error->pgtbl_er = I915_READ(PGTBL_ER);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b1f1db2bd879..2910b06913af 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -153,16 +153,16 @@ static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
>
> static void gen2_irq_reset(struct drm_i915_private *dev_priv)
> {
> - I915_WRITE16(IMR, 0xffff);
> - POSTING_READ16(IMR);
> + I915_WRITE16(GEN2_IMR, 0xffff);
> + POSTING_READ16(GEN2_IMR);
>
> - I915_WRITE16(IER, 0);
> + I915_WRITE16(GEN2_IER, 0);
>
> /* IIR can theoretically queue up two events. Be paranoid. */
> - I915_WRITE16(IIR, 0xffff);
> - POSTING_READ16(IIR);
> - I915_WRITE16(IIR, 0xffff);
> - POSTING_READ16(IIR);
> + I915_WRITE16(GEN2_IIR, 0xffff);
> + POSTING_READ16(GEN2_IIR);
> + I915_WRITE16(GEN2_IIR, 0xffff);
> + POSTING_READ16(GEN2_IIR);
> }
>
> #define GEN8_IRQ_RESET_NDX(type, which) \
> @@ -199,17 +199,17 @@ static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
>
> static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
> {
> - u16 val = I915_READ16(IIR);
> + u16 val = I915_READ16(GEN2_IIR);
>
> if (val == 0)
> return;
>
> WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
> - i915_mmio_reg_offset(IIR), val);
> - I915_WRITE16(IIR, 0xffff);
> - POSTING_READ16(IIR);
> - I915_WRITE16(IIR, 0xffff);
> - POSTING_READ16(IIR);
> + i915_mmio_reg_offset(GEN2_IIR), val);
> + I915_WRITE16(GEN2_IIR, 0xffff);
> + POSTING_READ16(GEN2_IIR);
> + I915_WRITE16(GEN2_IIR, 0xffff);
> + POSTING_READ16(GEN2_IIR);
> }
>
> static void gen3_irq_init(struct drm_i915_private *dev_priv,
> @@ -229,9 +229,9 @@ static void gen2_irq_init(struct drm_i915_private *dev_priv,
> {
> gen2_assert_iir_is_zero(dev_priv);
>
> - I915_WRITE16(IER, ier_val);
> - I915_WRITE16(IMR, imr_val);
> - POSTING_READ16(IMR);
> + I915_WRITE16(GEN2_IER, ier_val);
> + I915_WRITE16(GEN2_IMR, imr_val);
> + POSTING_READ16(GEN2_IMR);
> }
>
> #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
> @@ -4344,7 +4344,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> u16 eir = 0, eir_stuck = 0;
> u16 iir;
>
> - iir = I915_READ16(IIR);
> + iir = I915_READ16(GEN2_IIR);
> if (iir == 0)
> break;
>
> @@ -4357,7 +4357,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>
> - I915_WRITE16(IIR, iir);
> + I915_WRITE16(GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
> @@ -4384,7 +4384,7 @@ static void i915_irq_reset(struct drm_device *dev)
>
> i9xx_pipestat_irq_reset(dev_priv);
>
> - GEN3_IRQ_RESET();
> + GEN3_IRQ_RESET(GEN2_);
These do look a bit odd with the gen3+gen2 in the same sentence.
Hence not entitely convinced that GEN2_ is the best prefix. But
meh.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> }
>
> static int i915_irq_postinstall(struct drm_device *dev)
> @@ -4416,7 +4416,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
> dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
> }
>
> - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
> + GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
>
> /* Interrupt setup is already guaranteed to be single-threaded, this is
> * just to make the assert_spin_locked check happy. */
> @@ -4448,7 +4448,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> u32 hotplug_status = 0;
> u32 iir;
>
> - iir = I915_READ(IIR);
> + iir = I915_READ(GEN2_IIR);
> if (iir == 0)
> break;
>
> @@ -4465,7 +4465,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>
> - I915_WRITE(IIR, iir);
> + I915_WRITE(GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
> @@ -4493,7 +4493,7 @@ static void i965_irq_reset(struct drm_device *dev)
>
> i9xx_pipestat_irq_reset(dev_priv);
>
> - GEN3_IRQ_RESET();
> + GEN3_IRQ_RESET(GEN2_);
> }
>
> static int i965_irq_postinstall(struct drm_device *dev)
> @@ -4536,7 +4536,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
> if (IS_G4X(dev_priv))
> enable_mask |= I915_BSD_USER_INTERRUPT;
>
> - GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
> + GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
>
> /* Interrupt setup is already guaranteed to be single-threaded, this is
> * just to make the assert_spin_locked check happy. */
> @@ -4594,7 +4594,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> u32 hotplug_status = 0;
> u32 iir;
>
> - iir = I915_READ(IIR);
> + iir = I915_READ(GEN2_IIR);
> if (iir == 0)
> break;
>
> @@ -4610,7 +4610,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
> if (iir & I915_MASTER_ERROR_INTERRUPT)
> i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
>
> - I915_WRITE(IIR, iir);
> + I915_WRITE(GEN2_IIR, iir);
>
> if (iir & I915_USER_INTERRUPT)
> intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c206e803ab3..6a150243cabb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2713,10 +2713,10 @@ enum i915_power_well_id {
> #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
> #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
> #define SCPD0 _MMIO(0x209c) /* 915+ only */
> -#define IER _MMIO(0x20a0)
> -#define IIR _MMIO(0x20a4)
> -#define IMR _MMIO(0x20a8)
> -#define ISR _MMIO(0x20ac)
> +#define GEN2_IER _MMIO(0x20a0)
> +#define GEN2_IIR _MMIO(0x20a4)
> +#define GEN2_IMR _MMIO(0x20a8)
> +#define GEN2_ISR _MMIO(0x20ac)
> #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
> #define GINT_DIS (1 << 22)
> #define GCFG_DIS (1 << 8)
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 68875ba43b8d..b75ac660c3c2 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -1223,7 +1223,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915)
> */
> DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
> rmw_set(uncore, EMR, eir);
> - intel_uncore_write(uncore, IIR, I915_MASTER_ERROR_INTERRUPT);
> + intel_uncore_write(uncore, GEN2_IIR,
> + I915_MASTER_ERROR_INTERRUPT);
> }
>
> if (INTEL_GEN(i915) >= 8) {
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index a882b8d42bd9..eb317759b5d3 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -446,7 +446,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> if (!overlay->old_vma)
> return 0;
>
> - if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
> + if (I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
> /* synchronous slowpath */
> struct i915_request *rq;
>
> @@ -1430,7 +1430,7 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
> return NULL;
>
> error->dovsta = I915_READ(DOVSTA);
> - error->isr = I915_READ(ISR);
> + error->isr = I915_READ(GEN2_ISR);
> error->base = overlay->flip_addr;
>
> memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index af35f99c5940..029fd8ec1857 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -977,15 +977,15 @@ static void
> i9xx_irq_enable(struct intel_engine_cs *engine)
> {
> engine->i915->irq_mask &= ~engine->irq_enable_mask;
> - intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> - intel_uncore_posting_read_fw(engine->uncore, IMR);
> + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
> + intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
> }
>
> static void
> i9xx_irq_disable(struct intel_engine_cs *engine)
> {
> engine->i915->irq_mask |= engine->irq_enable_mask;
> - intel_uncore_write(engine->uncore, IMR, engine->i915->irq_mask);
> + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
> }
>
> static void
> @@ -994,7 +994,7 @@ i8xx_irq_enable(struct intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
>
> dev_priv->irq_mask &= ~engine->irq_enable_mask;
> - I915_WRITE16(IMR, dev_priv->irq_mask);
> + I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
> POSTING_READ16(RING_IMR(engine->mmio_base));
> }
>
> @@ -1004,7 +1004,7 @@ i8xx_irq_disable(struct intel_engine_cs *engine)
> struct drm_i915_private *dev_priv = engine->i915;
>
> dev_priv->irq_mask |= engine->irq_enable_mask;
> - I915_WRITE16(IMR, dev_priv->irq_mask);
> + I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
> }
>
> static int
> --
> 2.20.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/5] drm/i915: convert the IRQ initialization functions to intel_uncore
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (2 preceding siblings ...)
2019-04-10 23:53 ` [PATCH 3/5] drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers Paulo Zanoni
@ 2019-04-10 23:53 ` Paulo Zanoni
2019-04-10 23:53 ` [PATCH 5/5] drm/i915: fully convert the IRQ initialization macros " Paulo Zanoni
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-10 23:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The IRQ initialization helpers are simple and self-contained. Continue
the transition started in the recent uncore rework to get us rid of
I915_READ/WRITE and the implicit dev_priv variables.
While the implicit dev_priv is removed from the IRQ initialization
helpers, we didn't get rid of them in the macro callers. Doing that
should be very simple now.
v2: Rebase on top of the new patches.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 97 ++++++++++++++++-----------------
1 file changed, 48 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2910b06913af..22b89da25289 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,121 +136,120 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
};
-static void gen3_irq_reset(struct drm_i915_private *dev_priv, i915_reg_t imr,
+static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
- I915_WRITE(imr, 0xffffffff);
- POSTING_READ(imr);
+ intel_uncore_write(uncore, imr, 0xffffffff);
+ intel_uncore_posting_read(uncore, imr);
- I915_WRITE(ier, 0);
+ intel_uncore_write(uncore, ier, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- I915_WRITE(iir, 0xffffffff);
- POSTING_READ(iir);
- I915_WRITE(iir, 0xffffffff);
- POSTING_READ(iir);
+ intel_uncore_write(uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(uncore, iir);
+ intel_uncore_write(uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(uncore, iir);
}
-static void gen2_irq_reset(struct drm_i915_private *dev_priv)
+static void gen2_irq_reset(struct intel_uncore *uncore)
{
- I915_WRITE16(GEN2_IMR, 0xffff);
- POSTING_READ16(GEN2_IMR);
+ intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
+ intel_uncore_posting_read16(uncore, GEN2_IMR);
- I915_WRITE16(GEN2_IER, 0);
+ intel_uncore_write16(uncore, GEN2_IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- I915_WRITE16(GEN2_IIR, 0xffff);
- POSTING_READ16(GEN2_IIR);
- I915_WRITE16(GEN2_IIR, 0xffff);
- POSTING_READ16(GEN2_IIR);
+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(uncore, GEN2_IIR);
}
#define GEN8_IRQ_RESET_NDX(type, which) \
({ \
unsigned int which_ = which; \
- gen3_irq_reset(dev_priv, GEN8_##type##_IMR(which_), \
+ gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which_), \
GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
})
#define GEN3_IRQ_RESET(type) \
- gen3_irq_reset(dev_priv, type##IMR, type##IIR, type##IER)
+ gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER)
#define GEN2_IRQ_RESET() \
- gen2_irq_reset(dev_priv)
+ gen2_irq_reset(&dev_priv->uncore)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
-static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
+static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
{
- u32 val = I915_READ(reg);
+ u32 val = intel_uncore_read(uncore, reg);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(reg), val);
- I915_WRITE(reg, 0xffffffff);
- POSTING_READ(reg);
- I915_WRITE(reg, 0xffffffff);
- POSTING_READ(reg);
+ intel_uncore_write(uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(uncore, reg);
+ intel_uncore_write(uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(uncore, reg);
}
-static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv)
+static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
{
- u16 val = I915_READ16(GEN2_IIR);
+ u16 val = intel_uncore_read16(uncore, GEN2_IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(GEN2_IIR), val);
- I915_WRITE16(GEN2_IIR, 0xffff);
- POSTING_READ16(GEN2_IIR);
- I915_WRITE16(GEN2_IIR, 0xffff);
- POSTING_READ16(GEN2_IIR);
+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(uncore, GEN2_IIR);
}
-static void gen3_irq_init(struct drm_i915_private *dev_priv,
+static void gen3_irq_init(struct intel_uncore *uncore,
i915_reg_t imr, u32 imr_val,
i915_reg_t ier, u32 ier_val,
i915_reg_t iir)
{
- gen3_assert_iir_is_zero(dev_priv, iir);
+ gen3_assert_iir_is_zero(uncore, iir);
- I915_WRITE(ier, ier_val);
- I915_WRITE(imr, imr_val);
- POSTING_READ(imr);
+ intel_uncore_write(uncore, ier, ier_val);
+ intel_uncore_write(uncore, imr, imr_val);
+ intel_uncore_posting_read(uncore, imr);
}
-static void gen2_irq_init(struct drm_i915_private *dev_priv,
+static void gen2_irq_init(struct intel_uncore *uncore,
u32 imr_val, u32 ier_val)
{
- gen2_assert_iir_is_zero(dev_priv);
+ gen2_assert_iir_is_zero(uncore);
- I915_WRITE16(GEN2_IER, ier_val);
- I915_WRITE16(GEN2_IMR, imr_val);
- POSTING_READ16(GEN2_IMR);
+ intel_uncore_write16(uncore, GEN2_IER, ier_val);
+ intel_uncore_write16(uncore, GEN2_IMR, imr_val);
+ intel_uncore_posting_read16(uncore, GEN2_IMR);
}
#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
({ \
unsigned int which_ = which; \
- gen3_irq_init(dev_priv, \
+ gen3_irq_init(&dev_priv->uncore, \
GEN8_##type##_IMR(which_), imr_val, \
GEN8_##type##_IER(which_), ier_val, \
GEN8_##type##_IIR(which_)); \
})
#define GEN3_IRQ_INIT(type, imr_val, ier_val) \
- gen3_irq_init(dev_priv, \
+ gen3_irq_init(&dev_priv->uncore, \
type##IMR, imr_val, \
type##IER, ier_val, \
type##IIR)
#define GEN2_IRQ_INIT(imr_val, ier_val) \
- gen2_irq_init(dev_priv, imr_val, ier_val)
+ gen2_irq_init(&dev_priv->uncore, imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3868,7 +3867,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
else
mask = SDE_GMBUS_CPT;
- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
@@ -3937,7 +3936,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -4083,7 +4082,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
@@ -4167,7 +4166,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
I915_WRITE(SDEIER, 0xffffffff);
POSTING_READ(SDEIER);
- gen3_assert_iir_is_zero(dev_priv, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
icp_hpd_detection_setup(dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 5/5] drm/i915: fully convert the IRQ initialization macros to intel_uncore
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (3 preceding siblings ...)
2019-04-10 23:53 ` [PATCH 4/5] drm/i915: convert the IRQ initialization functions to intel_uncore Paulo Zanoni
@ 2019-04-10 23:53 ` Paulo Zanoni
2019-04-11 1:08 ` ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2) Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-10 23:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Make them take the uncore argument from the caller instead of passing
the implicit &dev_priv->uncore directly. This will allow us to finally
pass something that's not dev_priv->uncore in the future, and gets rid
of the implicit variables in register macros.
v2: Rebase on top of the newer patches.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 144 +++++++++++++++++++-------------
1 file changed, 88 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 22b89da25289..f6ab4c4c6388 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -165,18 +165,18 @@ static void gen2_irq_reset(struct intel_uncore *uncore)
intel_uncore_posting_read16(uncore, GEN2_IIR);
}
-#define GEN8_IRQ_RESET_NDX(type, which) \
+#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
({ \
unsigned int which_ = which; \
- gen3_irq_reset(&dev_priv->uncore, GEN8_##type##_IMR(which_), \
+ gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
})
-#define GEN3_IRQ_RESET(type) \
- gen3_irq_reset(&dev_priv->uncore, type##IMR, type##IIR, type##IER)
+#define GEN3_IRQ_RESET(uncore, type) \
+ gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET() \
- gen2_irq_reset(&dev_priv->uncore)
+#define GEN2_IRQ_RESET(uncore) \
+ gen2_irq_reset(uncore)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
@@ -233,23 +233,23 @@ static void gen2_irq_init(struct intel_uncore *uncore,
intel_uncore_posting_read16(uncore, GEN2_IMR);
}
-#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) \
+#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
({ \
unsigned int which_ = which; \
- gen3_irq_init(&dev_priv->uncore, \
+ gen3_irq_init((uncore), \
GEN8_##type##_IMR(which_), imr_val, \
GEN8_##type##_IER(which_), ier_val, \
GEN8_##type##_IIR(which_)); \
})
-#define GEN3_IRQ_INIT(type, imr_val, ier_val) \
- gen3_irq_init(&dev_priv->uncore, \
+#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
+ gen3_irq_init((uncore), \
type##IMR, imr_val, \
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(imr_val, ier_val) \
- gen2_irq_init(&dev_priv->uncore, imr_val, ier_val)
+#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
+ gen2_irq_init((uncore), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3349,10 +3349,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
if (HAS_PCH_NOP(dev_priv))
return;
- GEN3_IRQ_RESET(SDE);
+ GEN3_IRQ_RESET(uncore, SDE);
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
I915_WRITE(SERR_INT, 0xffffffff);
@@ -3380,13 +3382,17 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- GEN3_IRQ_RESET(GT);
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ GEN3_IRQ_RESET(uncore, GT);
if (INTEL_GEN(dev_priv) >= 6)
- GEN3_IRQ_RESET(GEN6_PM);
+ GEN3_IRQ_RESET(uncore, GEN6_PM);
}
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
else
@@ -3397,12 +3403,14 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(VLV_);
+ GEN3_IRQ_RESET(uncore, VLV_);
dev_priv->irq_mask = ~0u;
}
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
u32 pipestat_mask;
u32 enable_mask;
enum pipe pipe;
@@ -3427,7 +3435,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~enable_mask;
- GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
}
/* drm_dma.h hooks
@@ -3435,8 +3443,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
static void ironlake_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
- GEN3_IRQ_RESET(DE);
+ GEN3_IRQ_RESET(uncore, DE);
if (IS_GEN(dev_priv, 7))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3467,15 +3476,18 @@ static void valleyview_irq_reset(struct drm_device *dev)
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- GEN8_IRQ_RESET_NDX(GT, 0);
- GEN8_IRQ_RESET_NDX(GT, 1);
- GEN8_IRQ_RESET_NDX(GT, 2);
- GEN8_IRQ_RESET_NDX(GT, 3);
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ GEN8_IRQ_RESET_NDX(uncore, GT, 0);
+ GEN8_IRQ_RESET_NDX(uncore, GT, 1);
+ GEN8_IRQ_RESET_NDX(uncore, GT, 2);
+ GEN8_IRQ_RESET_NDX(uncore, GT, 3);
}
static void gen8_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
int pipe;
gen8_master_intr_disable(dev_priv->uncore.regs);
@@ -3488,11 +3500,11 @@ static void gen8_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
- GEN3_IRQ_RESET(GEN8_DE_PORT_);
- GEN3_IRQ_RESET(GEN8_DE_MISC_);
- GEN3_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
@@ -3518,6 +3530,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_uncore *uncore = &dev_priv->uncore;
int pipe;
gen11_master_intr_disable(dev_priv->uncore.regs);
@@ -3532,21 +3545,23 @@ static void gen11_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
- GEN3_IRQ_RESET(GEN8_DE_PORT_);
- GEN3_IRQ_RESET(GEN8_DE_MISC_);
- GEN3_IRQ_RESET(GEN11_DE_HPD_);
- GEN3_IRQ_RESET(GEN11_GU_MISC_);
- GEN3_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- GEN3_IRQ_RESET(SDE);
+ GEN3_IRQ_RESET(uncore, SDE);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
@@ -3558,7 +3573,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
dev_priv->de_irq_mask[pipe],
~dev_priv->de_irq_mask[pipe] | extra_ier);
@@ -3568,6 +3583,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
enum pipe pipe;
spin_lock_irq(&dev_priv->irq_lock);
@@ -3578,7 +3594,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
spin_unlock_irq(&dev_priv->irq_lock);
@@ -3589,13 +3605,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void cherryview_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
I915_WRITE(GEN8_MASTER_IRQ, 0);
POSTING_READ(GEN8_MASTER_IRQ);
gen8_gt_irq_reset(dev_priv);
- GEN3_IRQ_RESET(GEN8_PCU_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display_irqs_enabled)
@@ -3880,6 +3897,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 pm_irqs, gt_irqs;
pm_irqs = gt_irqs = 0;
@@ -3898,7 +3916,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
- GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
+ GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs);
if (INTEL_GEN(dev_priv) >= 6) {
/*
@@ -3911,13 +3929,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
}
dev_priv->pm_imr = 0xffffffff;
- GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
+ GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
}
}
static int ironlake_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 display_mask, extra_mask;
if (INTEL_GEN(dev_priv) >= 7) {
@@ -3936,7 +3955,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -3945,7 +3964,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
- GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
+ GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
+ display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
@@ -4015,6 +4035,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
/* These are interrupts we'll toggle with the ring mask register */
u32 gt_interrupts[] = {
(GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -4035,18 +4057,20 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->pm_ier = 0x0;
dev_priv->pm_imr = ~dev_priv->pm_ier;
- GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
- GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled. Same wil be the case for GuC interrupts.
*/
- GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
- GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
u32 de_pipe_enables;
u32 de_port_masked = GEN8_AUX_CHANNEL_A;
@@ -4082,7 +4106,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(&dev_priv->uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
@@ -4090,20 +4114,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
dev_priv->de_irq_mask[pipe],
de_pipe_enables);
}
- GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
- GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
+ GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
+ GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
if (INTEL_GEN(dev_priv) >= 11) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
- GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables);
+ GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
+ de_hpd_enables);
gen11_hpd_detection_setup(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_hpd_detection_setup(dev_priv);
@@ -4175,6 +4200,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -4183,7 +4209,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
- GEN3_IRQ_INIT(GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -4213,15 +4239,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
static void i8xx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
i9xx_pipestat_irq_reset(dev_priv);
- GEN2_IRQ_RESET();
+ GEN2_IRQ_RESET(uncore);
}
static int i8xx_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u16 enable_mask;
I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4239,7 +4267,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(dev_priv->irq_mask, enable_mask);
+ GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4375,6 +4403,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
static void i915_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
if (I915_HAS_HOTPLUG(dev_priv)) {
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4383,12 +4412,13 @@ static void i915_irq_reset(struct drm_device *dev)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(GEN2_);
+ GEN3_IRQ_RESET(uncore, GEN2_);
}
static int i915_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4415,7 +4445,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4486,18 +4516,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
static void i965_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(GEN2_);
+ GEN3_IRQ_RESET(uncore, GEN2_);
}
static int i965_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
u32 error_mask;
@@ -4535,7 +4567,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
- GEN3_IRQ_INIT(GEN2_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2)
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (4 preceding siblings ...)
2019-04-10 23:53 ` [PATCH 5/5] drm/i915: fully convert the IRQ initialization macros " Paulo Zanoni
@ 2019-04-11 1:08 ` Patchwork
2019-04-12 20:57 ` Paulo Zanoni
2019-04-12 23:01 ` ✗ Fi.CI.SPARSE: warning for IRQ initialization debloat and conversion to uncore (rev3) Patchwork
` (2 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Patchwork @ 2019-04-11 1:08 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev2)
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5904 -> Patchwork_12760
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59202/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_12760 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@basic-bsd2:
- fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57
* igt@gem_exec_parse@basic-rejected:
- fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_contexts:
- fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@i915_selftest@live_hangcheck:
- fi-bxt-dsi: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@basic-flip-c:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191]
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> SKIP [fdo#109271] +49
- fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3
* igt@kms_psr@primary_page_flip:
- fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +50
* igt@prime_vgem@basic-fence-flip:
- fi-icl-y: NOTRUN -> SKIP [fdo#109294]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (45 -> 38)
------------------------------
Additional (4): fi-icl-y fi-skl-guc fi-apl-guc fi-snb-2520m
Missing (11): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 fi-bdw-samus fi-kbl-r
Build changes
-------------
* Linux: CI_DRM_5904 -> Patchwork_12760
CI_DRM_5904: f0ba5aa7a6ab956f01dbaf1b16720da3ca859230 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4942: ff8929d4d5b57b544e699fa428930f0fd66dd2dc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12760: 84a9eee43744c59bbfca952ea970891ee1076c77 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
84a9eee43744 drm/i915: fully convert the IRQ initialization macros to intel_uncore
3d688694ded6 drm/i915: convert the IRQ initialization functions to intel_uncore
602a584b8939 drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
238ca5a190e4 drm/i915: don't specify the IRQ register in the gen2 macros
41f6a743fff7 drm/i915: refactor the IRQ init/reset macros
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12760/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2)
2019-04-11 1:08 ` ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2) Patchwork
@ 2019-04-12 20:57 ` Paulo Zanoni
2019-04-15 6:42 ` Tomi Sarvela
0 siblings, 1 reply; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-12 20:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Tomi Sarvela, Martin Peres
Em qui, 2019-04-11 às 01:08 +0000, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore (rev2)
> URL : https://patchwork.freedesktop.org/series/59202/
> State : success
So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
email anywhere: it's not showing on patchwork and it's also not showing
on https://intel-gfx-ci.01.org/queue/ as something to-do. Will CI run
the full IGT run in this series? Why not? I wanted to merge it.
Thanks,
Paulo
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5904 -> Patchwork_12760
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
> External URL: https://patchwork.freedesktop.org/api/1.0/series/59202/revisions/2/mbox/
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_12760 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@amdgpu/amd_cs_nop@fork-compute0:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17
>
> * igt@gem_exec_basic@basic-bsd2:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7
>
> * igt@gem_exec_basic@readonly-bsd1:
> - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57
>
> * igt@gem_exec_parse@basic-rejected:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1
>
> * igt@i915_selftest@live_contexts:
> - fi-icl-y: NOTRUN -> DMESG-FAIL [fdo#108569]
>
> * igt@i915_selftest@live_execlists:
> - fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]
>
> * igt@i915_selftest@live_hangcheck:
> - fi-bxt-dsi: PASS -> INCOMPLETE [fdo#103927]
>
> * igt@kms_busy@basic-flip-c:
> - fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
>
> * igt@kms_chamelium@dp-crc-fast:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8
>
> * igt@kms_force_connector_basic@force-load-detect:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
> - fi-byt-clapper: PASS -> FAIL [fdo#103191]
>
> * igt@kms_psr@primary_mmap_gtt:
> - fi-skl-guc: NOTRUN -> SKIP [fdo#109271] +49
> - fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3
>
> * igt@kms_psr@primary_page_flip:
> - fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +50
>
> * igt@prime_vgem@basic-fence-flip:
> - fi-icl-y: NOTRUN -> SKIP [fdo#109294]
>
> * igt@runner@aborted:
> - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
>
>
> #### Possible fixes ####
>
> * igt@i915_selftest@live_contexts:
> - fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
>
> * igt@i915_selftest@live_evict:
> - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS
>
> * igt@kms_frontbuffer_tracking@basic:
> - fi-byt-clapper: FAIL [fdo#103167] -> PASS
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
> - fi-byt-clapper: FAIL [fdo#103191] -> PASS
>
>
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
> [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
> [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
>
>
> Participating hosts (45 -> 38)
> ------------------------------
>
> Additional (4): fi-icl-y fi-skl-guc fi-apl-guc fi-snb-2520m
> Missing (11): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-glk-dsi fi-byt-squawks fi-bwr-2160 fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 fi-bdw-samus fi-kbl-r
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_5904 -> Patchwork_12760
>
> CI_DRM_5904: f0ba5aa7a6ab956f01dbaf1b16720da3ca859230 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4942: ff8929d4d5b57b544e699fa428930f0fd66dd2dc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_12760: 84a9eee43744c59bbfca952ea970891ee1076c77 @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 84a9eee43744 drm/i915: fully convert the IRQ initialization macros to intel_uncore
> 3d688694ded6 drm/i915: convert the IRQ initialization functions to intel_uncore
> 602a584b8939 drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
> 238ca5a190e4 drm/i915: don't specify the IRQ register in the gen2 macros
> 41f6a743fff7 drm/i915: refactor the IRQ init/reset macros
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12760/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2)
2019-04-12 20:57 ` Paulo Zanoni
@ 2019-04-15 6:42 ` Tomi Sarvela
2019-04-15 23:04 ` Paulo Zanoni
0 siblings, 1 reply; 15+ messages in thread
From: Tomi Sarvela @ 2019-04-15 6:42 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Martin Peres
On 4/12/19 11:57 PM, Paulo Zanoni wrote:
> Em qui, 2019-04-11 às 01:08 +0000, Patchwork escreveu:
>> == Series Details ==
>>
>> Series: IRQ initialization debloat and conversion to uncore (rev2)
>> URL : https://patchwork.freedesktop.org/series/59202/
>> State : success
>
> So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
> email anywhere: it's not showing on patchwork and it's also not showing
> on https://intel-gfx-ci.01.org/queue/ as something to-do. Will CI run
> the full IGT run in this series? Why not? I wanted to merge it.
On Thu and Fri the CI (or rather, our lab network) had serious issues
with DNS connectivity. We're mostly clear now, one issue remains but it
shouldn't affect productivity.
Seems that the re-testing did the trick for you?
Tomi
--
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2)
2019-04-15 6:42 ` Tomi Sarvela
@ 2019-04-15 23:04 ` Paulo Zanoni
0 siblings, 0 replies; 15+ messages in thread
From: Paulo Zanoni @ 2019-04-15 23:04 UTC (permalink / raw)
To: Tomi Sarvela, intel-gfx; +Cc: Martin Peres
Em seg, 2019-04-15 às 09:42 +0300, Tomi Sarvela escreveu:
> On 4/12/19 11:57 PM, Paulo Zanoni wrote:
> > Em qui, 2019-04-11 às 01:08 +0000, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloat and conversion to uncore (rev2)
> > > URL : https://patchwork.freedesktop.org/series/59202/
> > > State : success
> >
> > So, this is the BAT email I got yesterday. I don't see the FI.CI.IGT
> > email anywhere: it's not showing on patchwork and it's also not showing
> > on https://intel-gfx-ci.01.org/queue/ as something to-do. Will CI run
> > the full IGT run in this series? Why not? I wanted to merge it.
>
> On Thu and Fri the CI (or rather, our lab network) had serious issues
> with DNS connectivity. We're mostly clear now, one issue remains but it
> shouldn't affect productivity.
Thanks for letting me know. I was unsure if there was some new CI rule
in place or that maybe I just did something wrong.
>
> Seems that the re-testing did the trick for you?
Yeah, I pushed the retest button a little later I sent the email.
Thanks,
Paulo
>
>
> Tomi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.SPARSE: warning for IRQ initialization debloat and conversion to uncore (rev3)
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (5 preceding siblings ...)
2019-04-11 1:08 ` ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev2) Patchwork
@ 2019-04-12 23:01 ` Patchwork
2019-04-12 23:29 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-13 3:55 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-04-12 23:01 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: refactor the IRQ init/reset macros
+drivers/gpu/drm/i915/i915_irq.c:1004:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_irq.c:1004:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1004:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:1004:20: warning: expression using sizeof(void)
Commit: drm/i915: don't specify the IRQ register in the gen2 macros
-drivers/gpu/drm/i915/i915_irq.c:997:20: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_irq.c:997:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_irq.c:997:20: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_irq.c:997:20: warning: expression using sizeof(void)
Commit: drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
Okay!
Commit: drm/i915: convert the IRQ initialization functions to intel_uncore
Okay!
Commit: drm/i915: fully convert the IRQ initialization macros to intel_uncore
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.BAT: success for IRQ initialization debloat and conversion to uncore (rev3)
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (6 preceding siblings ...)
2019-04-12 23:01 ` ✗ Fi.CI.SPARSE: warning for IRQ initialization debloat and conversion to uncore (rev3) Patchwork
@ 2019-04-12 23:29 ` Patchwork
2019-04-13 3:55 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-04-12 23:29 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926 -> Patchwork_12787
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59202/revisions/3/mbox/
Known issues
------------
Here are the changes found in Patchwork_12787 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
* igt@kms_force_connector_basic@force-edid:
- fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26
* igt@kms_frontbuffer_tracking@basic:
- fi-glk-dsi: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] +1
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] -> PASS +1
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (48 -> 42)
------------------------------
Missing (6): fi-kbl-soraka fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5926 -> Patchwork_12787
CI_DRM_5926: 2ab8e3b23618f04e84a03ecb53685e14cd2a5346 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12787: 7c5df13fc83a57d036475ba770febdb152aeaa11 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7c5df13fc83a drm/i915: fully convert the IRQ initialization macros to intel_uncore
c561cc4f095e drm/i915: convert the IRQ initialization functions to intel_uncore
f6efee35fd2c drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registers
e0425f91d576 drm/i915: don't specify the IRQ register in the gen2 macros
cc555253c2ac drm/i915: refactor the IRQ init/reset macros
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12787/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.IGT: success for IRQ initialization debloat and conversion to uncore (rev3)
2019-04-10 23:53 [PATCH 0/5] IRQ initialization debloat and conversion to uncore, v2 Paulo Zanoni
` (7 preceding siblings ...)
2019-04-12 23:29 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-13 3:55 ` Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-04-13 3:55 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore (rev3)
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5926_full -> Patchwork_12787_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12787_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +16
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-iclb: NOTRUN -> SKIP [fdo#109313]
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> SKIP [fdo#109283]
* igt@gem_mocs_settings@mocs-settings-dirty-render:
- shard-iclb: NOTRUN -> SKIP [fdo#110206] +1
* igt@gem_pread@stolen-normal:
- shard-iclb: NOTRUN -> SKIP [fdo#109277] +1
* igt@i915_pm_lpsp@screens-disabled:
- shard-iclb: NOTRUN -> SKIP [fdo#109301]
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> SKIP [fdo#109308]
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> SKIP [fdo#109506]
* igt@i915_selftest@live_workarounds:
- shard-iclb: PASS -> DMESG-FAIL [fdo#108954]
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +3
* igt@i915_suspend@sysfs-reader:
- shard-kbl: PASS -> DMESG-WARN [fdo#108566]
* igt@kms_atomic_transition@4x-modeset-transitions-nonblocking:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +4
* igt@kms_atomic_transition@5x-modeset-transitions:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-iclb: NOTRUN -> FAIL [fdo#106641]
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +5
* igt@kms_cursor_crc@cursor-512x512-onscreen:
- shard-iclb: NOTRUN -> SKIP [fdo#109279]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +11
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_force_connector_basic@force-connector-state:
- shard-iclb: NOTRUN -> SKIP [fdo#109285]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +30
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#109247] +13
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +98
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] +3
* igt@kms_invalid_dotclock:
- shard-iclb: NOTRUN -> SKIP [fdo#109310]
* igt@kms_lease@cursor_implicit_plane:
- shard-skl: NOTRUN -> FAIL [fdo#110278]
- shard-iclb: NOTRUN -> FAIL [fdo#110278]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#110403]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
- shard-apl: PASS -> INCOMPLETE [fdo#103927] +1
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: NOTRUN -> FAIL [fdo#109052] +1
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: PASS -> SKIP [fdo#109441]
* igt@kms_psr@psr2_suspend:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@perf_pmu@rc6:
- shard-kbl: PASS -> SKIP [fdo#109271]
* igt@prime_nv_api@i915_self_import:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +3
* igt@v3d_get_bo_offset@get-bad-handle:
- shard-iclb: NOTRUN -> SKIP [fdo#109315]
#### Possible fixes ####
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: FAIL [fdo#108686] -> PASS
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-WARN [fdo#109982] -> PASS
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#109247] -> PASS +5
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#110403] -> PASS
* igt@kms_psr@cursor_blt:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +3
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: SKIP [fdo#109441] -> PASS
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
[fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109310]: https://bugs.freedesktop.org/show_bug.cgi?id=109310
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
[fdo#110206]: https://bugs.freedesktop.org/show_bug.cgi?id=110206
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110278]: https://bugs.freedesktop.org/show_bug.cgi?id=110278
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5926 -> Patchwork_12787
CI_DRM_5926: 2ab8e3b23618f04e84a03ecb53685e14cd2a5346 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12787: 7c5df13fc83a57d036475ba770febdb152aeaa11 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12787/
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