Re: [PATCH 3/3] drm/i915/ehl: Add voltage level requirement table

Souza, Jose
2019-06-20T00:36:05Z

On Wed, 2019-06-19 at 14:43 +0300, Ville Syrjälä wrote:
> On Tue, Jun 18, 2019 at 03:50:35PM -0700, José Roberto de Souza
> wrote:
> > EHL has it own voltage level requirement depending on cd clock.
> >
> > BSpec: 21809
> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++
> > ------
> > 1 file changed, 17 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 26c17ecf2083..575ab1a96bbc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1872,8 +1872,17 @@ static void icl_set_cdclk(struct
> > drm_i915_private *dev_priv,
> > dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> > }
> >
> > -static u8 icl_calc_voltage_level(int cdclk)
> > +static u8 icl_calc_voltage_level(struct drm_i915_private
> > *dev_priv, int cdclk)
> > {
> > + if (IS_ELKHARTLAKE(dev_priv)) {
> > + if (cdclk > 312000)
> > + return 2;
> > + else if (cdclk > 180000)
> > + return 1;
> > + else
> > + return 0;
> > + }
> > +
> > if (cdclk > 556800)
> > return 2;
> > else if (cdclk > 312000)
>
> I would move the rest into and else branch to make it clear the
> two are just the two sides of the same coin.

You mean like this?

static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int
cdclk)
{
if (IS_ELKHARTLAKE(dev_priv)) {
if (cdclk > 312000)
return 2;
else if (cdclk > 180000)
return 1;
else
return 0;
} else {
if (cdclk > 556800)
return 2;
else if (cdclk > 312000)
return 1;
else
return 0;
}
}

>
> > @@ -1930,7 +1939,7 @@ static void icl_get_cdclk(struct
> > drm_i915_private *dev_priv,
> > * at least what the CDCLK frequency requires.
> > */
> > cdclk_state->voltage_level =
> > - icl_calc_voltage_level(cdclk_state->cdclk);
> > + icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
> > }
> >
> > static void icl_init_cdclk(struct drm_i915_private *dev_priv)
> > @@ -1966,7 +1975,8 @@ static void icl_init_cdclk(struct
> > drm_i915_private *dev_priv)
> > sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> > sanitized_state.cd
> > clk);
> > sanitized_state.voltage_level =
> > - icl_calc_voltage_level(sanitized_state.
> > cdclk);
> > + icl_calc_voltage_level(dev_priv,
> > + sanitized_state.
> > cdclk);
> >
> > icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
> > }
> > @@ -1977,7 +1987,8 @@ static void icl_uninit_cdclk(struct
> > drm_i915_private *dev_priv)
> >
> > cdclk_state.cdclk = cdclk_state.bypass;
> > cdclk_state.vco = 0;
> > - cdclk_state.voltage_level =
> > icl_calc_voltage_level(cdclk_state.cdclk);
> > + cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
> > + cdclk_state.
> > cdclk);
> >
> > icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> > }
> > @@ -2568,7 +2579,7 @@ static int icl_modeset_calc_cdclk(struct
> > intel_atomic_state *state)
> > state->cdclk.logical.vco = vco;
> > state->cdclk.logical.cdclk = cdclk;
> > state->cdclk.logical.voltage_level =
> > - max(icl_calc_voltage_level(cdclk),
> > + max(icl_calc_voltage_level(dev_priv, cdclk),
> > cnl_compute_min_voltage_level(state));
> >
> > if (!state->active_crtcs) {
> > @@ -2579,7 +2590,7 @@ static int icl_modeset_calc_cdclk(struct
> > intel_atomic_state *state)
> > state->cdclk.actual.vco = vco;
> > state->cdclk.actual.cdclk = cdclk;
> > state->cdclk.actual.voltage_level =
> > - icl_calc_voltage_level(cdclk);
> > + icl_calc_voltage_level(dev_priv, cdclk);
> > } else {
> > state->cdclk.actual = state->cdclk.logical;
> > }
> > --
> > 2.22.0
> >
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> > Intel-gfx@lists.freedesktop.org
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