✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev2)

Patchwork
2019-08-17T10:12:09Z

== Series Details ==

Series: Tiger Lake batch 3 (rev2)
URL : https://patchwork.freedesktop.org/series/65290/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6725 -> Patchwork_14069
====================================================

Summary
-------

**FAILURE**

Serious unknown changes coming with Patchwork_14069 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14069, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_14069:

### IGT changes ###

#### Possible regressions ####

* igt@gem_sync@basic-store-each:
- fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-cfl-8109u/igt@gem_sync@basic-store-each.html

Known issues
------------

Here are the changes found in Patchwork_14069 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html

* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

#### Possible fixes ####

* igt@gem_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u3/igt@gem_linear_blits@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u3/igt@gem_linear_blits@basic.html

* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][11] ([fdo#109271] / [fdo#109278]) -> [PASS][12] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html

* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [FAIL][13] ([fdo#109483] / [fdo#109635 ]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html

[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635

Participating hosts (53 -> 45)
------------------------------

Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus

Build changes
-------------

* CI: CI-20190529 -> None
* Linux: CI_DRM_6725 -> Patchwork_14069

CI-20190529: 20190529
CI_DRM_6725: fdcbe4ab792e64f23631fcb6a9d58c2cf03d74f7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14069: 32fc1d4b22a3b512cfa2d1b5576888f49cad5c93 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

32fc1d4b22a3 drm/i915/tgl: Gen-12 media compression
523159de2114 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
4d432593e93d drm/i915/tgl: Gen-12 render decompression
ed7414e63958 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
722ded5b9285 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
6614f3d1a6f2 drm/i915/tgl: Add perf support on TGL
493819143bc7 drm/i915/perf: add a parameter to control the size of OA buffer
ea7621575fd9 drm/i915/tgl/perf: use the same oa ctx_id format as icl
240a129f0132 drm/i915/tgl: Updated Private PAT programming
623edef0032b rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
230eba25e017 drm/i915/tgl: Report valid VDBoxes with SFC capability
5453b392d597 drm/i915/tgl: Gen12 csb support
bde4c00b75c9 drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
bfbb493106a1 drm/i915/tgl: add Gen12 default indirect ctx offset
86de648919da HACK: drm/i915/tgl: Gen12 render context size
d0ca1f27b4a0 drm/i915/tgl: Implement TGL DisplayPort training sequence
df4c77de5dd1 drm/i915/tgl: move DP_TP_* to transcoder
94baf2b17b36 drm/i915/tgl: Register state context definition for Gen12
6cdda9b265af drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
c77dbff20a84 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
6a6b80f2fb18 drm/i915/tgl: Introduce initial Tiger Lake workarounds
08b6786f83a9 drm/i915/tgl: Select master transcoder in DP MST
e5990121b4b6 drm/i915: Disable pipes in reverse order
c29f6126d5bc drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
8a0acb1f6f18 drm/i915: Add for_each_new_intel_connector_in_state()
b20288b02d29 drm/i915: Fix DP-MST crtc_mask
06803b514364 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
0d7f5c32f219 drm/i915/tgl: Access the right register when handling PSR interruptions
b9911dff9e65 drm/i915/tgl: PSR link standby is not supported anymore
03270e92e574 drm/i915: Do not read PSR2 register in transcoders without PSR2
d2a1e84537f6 drm/i915: Guard and warn if more than one eDP panel is present
1470888c4e04 drm/i915/bdw+: Enable PSR in any eDP port
3647639077cd drm/i915/psr: Only handle interruptions of the transcoder in use
ea93386d65d2 drm/i915: Do not unmask PSR interruption in IRQ postinstall
66b0f8d14a5c drm/i915: Add transcoder restriction to PSR2
c7f6f41671dc drm/i915/psr: Make PSR registers relative to transcoders
6d8b64b06ed0 drm/i915/tgl: update DMC firmware to 2.04
bc67233266e2 drm/i915/tgl: Move transcoders to pipes' powerwells
90d92ce242b9 drm/i915/tgl: add support for reading the timestamp frequency
bfd5dba4649b drm/i915/tgl: disable DDIC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/