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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 05/19] drm/i915: Allow downscale factor of <3.0 on glk+ for all formats
Date: Wed, 11 Sep 2019 13:39:00 +0300	[thread overview]
Message-ID: <20190911103900.GX7482@intel.com> (raw)
In-Reply-To: <f84f813d-02c1-3d60-d320-1f7ed7202395@linux.intel.com>

On Wed, Sep 11, 2019 at 11:53:54AM +0200, Maarten Lankhorst wrote:
> Op 08-07-2019 om 14:53 schreef Ville Syrjala:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Bspec says that glk+ max downscale factor is <3.0 for all pixel formats.
> > Older platforms had a max of <2.0 for NV12. Update the code to deal with
> > this.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index ee93577bdf95..2b8a6a84605c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14472,7 +14472,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	int max_scale, mult;
> > +	int max_scale;
> >  	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
> >  
> >  	if (!crtc_state->base.enable)
> > @@ -14493,8 +14493,11 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
> >  	 *            or
> >  	 *    cdclk/crtc_clock
> >  	 */
> > -	mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3;
> > -	tmpclk1 = (1 << 16) * mult - 1;
> > +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
> > +	    !drm_format_info_is_yuv_semiplanar(format))
> > +		tmpclk1 = 0x30000 - 1;
> > +	else
> > +		tmpclk1 = 0x20000 - 1;
> >  	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> >  	max_scale = min(tmpclk1, tmpclk2);
> >  
> 
> For this patch and 4, 6, 7, 8:
> 
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
> Patch 4 seems to be exactly the same as the patch I wrote for it, so lets upstream this ASAP before someone else does as well. ;)

Almost the same, except the 'if (fourcc && ...)' part in the readout.
IIRC otherwise it would WARN when we try to look up the format info
w/ fourcc==0.

Thanks for the review.

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2019-09-11 10:39 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-08 12:53 [PATCH 00/19] drm/i915: Plane cdclk requirements and fp16 for gen4+ Ville Syrjala
2019-07-08 12:53 ` [PATCH 01/19] drm: Add drm_modeset_lock_assert_held() Ville Syrjala
2019-07-08 12:53 ` [PATCH 02/19] drm/atomic-helper: Make crtc helper funcs optional Ville Syrjala
2019-09-05  6:38   ` Lisovskiy, Stanislav
2019-09-05 11:00     ` Ville Syrjälä
2019-09-18 13:42   ` Lisovskiy, Stanislav
2019-09-19 18:47     ` Ville Syrjälä
2019-07-08 12:53 ` [PATCH 03/19] drm/i915: Remove pointless planes_changed=true assignment Ville Syrjala
2019-09-05  6:40   ` Lisovskiy, Stanislav
2019-07-08 12:53 ` [PATCH 04/19] drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar() Ville Syrjala
2019-07-08 12:53 ` [PATCH 05/19] drm/i915: Allow downscale factor of <3.0 on glk+ for all formats Ville Syrjala
2019-09-11  9:53   ` Maarten Lankhorst
2019-09-11 10:39     ` Ville Syrjälä [this message]
2019-07-08 12:53 ` [PATCH 06/19] drm/i915: Extract intel_modeset_calc_cdclk() Ville Syrjala
2019-07-08 12:53 ` [PATCH 07/19] drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check() Ville Syrjala
2019-07-08 12:53 ` [PATCH 08/19] drm/i915: Stop using drm_atomic_helper_check_planes() Ville Syrjala
2019-09-05  6:44   ` Lisovskiy, Stanislav
2019-09-19 11:15   ` Maarten Lankhorst
2019-07-08 12:53 ` [PATCH 09/19] drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update Ville Syrjala
2019-07-08 12:53 ` [PATCH 10/19] drm/i915: Make .modeset_calc_cdclk() mandatory Ville Syrjala
2019-09-19 11:01   ` [Intel-gfx] " Maarten Lankhorst
2019-07-08 12:53 ` [PATCH 11/19] drm/i915: Rework global state locking Ville Syrjala
2019-07-08 12:53 ` [PATCH 12/19] drm/i915: Move check_digital_port_conflicts() earier Ville Syrjala
2019-07-08 12:53 ` [PATCH 13/19] drm/i915: Allow planes to declare their minimum acceptable cdclk Ville Syrjala
2019-07-08 12:53 ` [PATCH 14/19] drm/i915: Eliminate skl_check_pipe_max_pixel_rate() Ville Syrjala
2019-07-08 12:53 ` [PATCH 15/19] drm/i915: Simplify skl_max_scale() Ville Syrjala
2019-09-16 20:01   ` Juha-Pekka Heikkilä
2019-07-08 12:53 ` [PATCH 16/19] drm/i915: Add support for half float framebuffers for skl+ Ville Syrjala
2019-07-08 12:53 ` [PATCH 17/19] drm/i915: Add support for half float framebuffers for gen4+ primary planes Ville Syrjala
2019-07-08 12:53 ` [PATCH 18/19] drm/i915: Add support for half float framebuffers for ivb+ sprites Ville Syrjala
2019-07-08 12:53 ` [PATCH 19/19] drm/i915: Add support for half float framebuffers on snb sprites Ville Syrjala
2019-07-08 13:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cdclk requirements and fp16 for gen4+ Patchwork
2019-07-08 13:21 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-07-08 13:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-08 19:41 ` ✓ Fi.CI.IGT: " Patchwork

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