* [PATCH 01/24] HAX to make DSC work on the icelake test system
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 11:34 ` [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition Maarten Lankhorst
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
DSC is available on the display emulator, but not set in DPCD.
Override the entries to allow bigjoiner testing.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f373798d82f6..a990073c7adf 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1374,7 +1374,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
} else {
@@ -1398,7 +1398,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ed1a985745ba..065b65350fce 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1222,6 +1222,7 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SI
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
{
+ return dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT];
return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
DP_DSC_DECOMPRESSION_IS_SUPPORTED;
}
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
2019-10-04 11:34 ` [PATCH 01/24] HAX to make DSC work on the icelake test system Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 13:14 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
2019-10-04 11:34 ` [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state Maarten Lankhorst
` (24 subsequent siblings)
26 siblings, 2 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
Using for_each_intel_plane_mask() fails because of an extra bracket,
remove the bracket so we can use it in the next commit.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 2782f23ee887..4ded64fcbc6c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -350,7 +350,7 @@ enum phy_fia {
&(dev)->mode_config.plane_list, \
base.head) \
for_each_if((plane_mask) & \
- drm_plane_mask(&intel_plane->base)))
+ drm_plane_mask(&intel_plane->base))
#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
list_for_each_entry(intel_plane, \
--
2.23.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition
2019-10-04 11:34 ` [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition Maarten Lankhorst
@ 2019-10-04 13:14 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 13:14 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:52PM +0200, Maarten Lankhorst wrote:
> Using for_each_intel_plane_mask() fails because of an extra bracket,
> remove the bracket so we can use it in the next commit.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 2782f23ee887..4ded64fcbc6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -350,7 +350,7 @@ enum phy_fia {
> &(dev)->mode_config.plane_list, \
> base.head) \
> for_each_if((plane_mask) & \
> - drm_plane_mask(&intel_plane->base)))
> + drm_plane_mask(&intel_plane->base))
>
> #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
> list_for_each_entry(intel_plane, \
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition
2019-10-04 11:34 ` [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition Maarten Lankhorst
2019-10-04 13:14 ` Ville Syrjälä
@ 2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Matt Roper @ 2019-10-07 19:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:52PM +0200, Maarten Lankhorst wrote:
> Using for_each_intel_plane_mask() fails because of an extra bracket,
> remove the bracket so we can use it in the next commit.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 2782f23ee887..4ded64fcbc6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -350,7 +350,7 @@ enum phy_fia {
> &(dev)->mode_config.plane_list, \
> base.head) \
> for_each_if((plane_mask) & \
> - drm_plane_mask(&intel_plane->base)))
> + drm_plane_mask(&intel_plane->base))
>
> #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
> list_for_each_entry(intel_plane, \
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
2019-10-04 11:34 ` [PATCH 01/24] HAX to make DSC work on the icelake test system Maarten Lankhorst
2019-10-04 11:34 ` [PATCH 02/24] drm/i915: Fix for_each_intel_plane_mask definition Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 13:18 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
2019-10-04 11:34 ` [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates Maarten Lankhorst
` (23 subsequent siblings)
26 siblings, 2 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
Instead of looking at drm_plane_state, look at intel_plane_state directly.
This will allow us to make the watermarks bigjoiner aware, when we make it
work for bigjoiner slave pipes as well.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 8 +++
drivers/gpu/drm/i915/intel_pm.c | 60 ++++++++------------
2 files changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 4ded64fcbc6c..bc2cf4bec0e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -440,6 +440,14 @@ enum phy_fia {
(__i)--) \
for_each_if(crtc)
+#define intel_atomic_crtc_state_for_each_plane_state( \
+ plane, plane_state, \
+ crtc_state) \
+ for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
+ ((crtc_state)->base.plane_mask)) \
+ for_each_if ((plane_state = \
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..6aeaad587a20 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3089,8 +3089,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
struct intel_pipe_wm *pipe_wm;
struct drm_device *dev = state->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_plane *plane;
- const struct drm_plane_state *plane_state;
+ struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
const struct intel_plane_state *pristate = NULL;
const struct intel_plane_state *sprstate = NULL;
const struct intel_plane_state *curstate = NULL;
@@ -3099,15 +3099,13 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
pipe_wm = &crtc_state->wm.ilk.optimal;
- drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
- const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
-
- if (plane->type == DRM_PLANE_TYPE_PRIMARY)
- pristate = ps;
- else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
- sprstate = ps;
- else if (plane->type == DRM_PLANE_TYPE_CURSOR)
- curstate = ps;
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
+ pristate = plane_state;
+ else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
+ sprstate = plane_state;
+ else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ curstate = plane_state;
}
pipe_wm->pipe_enabled = crtc_state->base.active;
@@ -4124,8 +4122,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
{
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
struct drm_atomic_state *state = crtc_state->base.state;
- struct drm_plane *plane;
- const struct drm_plane_state *drm_plane_state;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
int crtc_clock, dotclk;
u32 pipe_max_pixel_rate;
uint_fixed_16_16_t pipe_downscale;
@@ -4134,12 +4132,10 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
if (!crtc_state->base.enable)
return 0;
- drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
uint_fixed_16_16_t plane_downscale;
uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
int bpp;
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(drm_plane_state);
if (!intel_wm_plane_visible(crtc_state, plane_state))
continue;
@@ -4227,18 +4223,16 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *uv_plane_data_rate)
{
struct drm_atomic_state *state = crtc_state->base.state;
- struct drm_plane *plane;
- const struct drm_plane_state *drm_plane_state;
+ struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
if (WARN_ON(!state))
return 0;
/* Calculate and cache data rate for each plane */
- drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
- enum plane_id plane_id = to_intel_plane(plane)->id;
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(drm_plane_state);
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ enum plane_id plane_id = plane->id;
u64 rate;
/* packed/y */
@@ -4259,18 +4253,16 @@ static u64
icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate)
{
- struct drm_plane *plane;
- const struct drm_plane_state *drm_plane_state;
+ struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
if (WARN_ON(!crtc_state->base.state))
return 0;
/* Calculate and cache data rate for each plane */
- drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(drm_plane_state);
- enum plane_id plane_id = to_intel_plane(plane)->id;
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+ enum plane_id plane_id = plane->id;
u64 rate;
if (!plane_state->planar_linked_plane) {
@@ -4282,7 +4274,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
/*
* The slave plane might not iterate in
- * drm_atomic_crtc_state_for_each_plane_state(),
+ * intel_atomic_crtc_state_for_each_plane_state(),
* and needs the master plane state which may be
* NULL if we try get_new_plane_state(), so we
* always calculate from the master.
@@ -5065,8 +5057,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- struct drm_plane *plane;
- const struct drm_plane_state *drm_plane_state;
+ struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
int ret;
/*
@@ -5075,10 +5067,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
*/
memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
- drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
- &crtc_state->base) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(drm_plane_state);
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
+ crtc_state) {
if (INTEL_GEN(dev_priv) >= 11)
ret = icl_build_plane_wm(crtc_state, plane_state);
--
2.23.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state.
2019-10-04 11:34 ` [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state Maarten Lankhorst
@ 2019-10-04 13:18 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 13:18 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:53PM +0200, Maarten Lankhorst wrote:
> Instead of looking at drm_plane_state, look at intel_plane_state directly.
>
> This will allow us to make the watermarks bigjoiner aware, when we make it
> work for bigjoiner slave pipes as well.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> drivers/gpu/drm/i915/intel_pm.c | 60 ++++++++------------
> 2 files changed, 33 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 4ded64fcbc6c..bc2cf4bec0e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -440,6 +440,14 @@ enum phy_fia {
> (__i)--) \
> for_each_if(crtc)
>
> +#define intel_atomic_crtc_state_for_each_plane_state( \
> + plane, plane_state, \
> + crtc_state) \
> + for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> + ((crtc_state)->base.plane_mask)) \
> + for_each_if ((plane_state = \
> + to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> +
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfcf03ab5245..6aeaad587a20 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3089,8 +3089,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> struct intel_pipe_wm *pipe_wm;
> struct drm_device *dev = state->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_plane *plane;
> - const struct drm_plane_state *plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> const struct intel_plane_state *pristate = NULL;
> const struct intel_plane_state *sprstate = NULL;
> const struct intel_plane_state *curstate = NULL;
> @@ -3099,15 +3099,13 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>
> pipe_wm = &crtc_state->wm.ilk.optimal;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
> - const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
> -
> - if (plane->type == DRM_PLANE_TYPE_PRIMARY)
> - pristate = ps;
> - else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> - sprstate = ps;
> - else if (plane->type == DRM_PLANE_TYPE_CURSOR)
> - curstate = ps;
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> + pristate = plane_state;
> + else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
> + sprstate = plane_state;
> + else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
> + curstate = plane_state;
> }
>
> pipe_wm->pipe_enabled = crtc_state->base.active;
> @@ -4124,8 +4122,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> int crtc_clock, dotclk;
> u32 pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> @@ -4134,12 +4132,10 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> if (!crtc_state->base.enable)
> return 0;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> uint_fixed_16_16_t plane_downscale;
> uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
> int bpp;
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
>
> if (!intel_wm_plane_visible(crtc_state, plane_state))
> continue;
> @@ -4227,18 +4223,16 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *uv_plane_data_rate)
> {
> struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> if (WARN_ON(!state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> - enum plane_id plane_id = to_intel_plane(plane)->id;
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + enum plane_id plane_id = plane->id;
> u64 rate;
>
> /* packed/y */
> @@ -4259,18 +4253,16 @@ static u64
> icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate)
> {
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> if (WARN_ON(!crtc_state->base.state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> - enum plane_id plane_id = to_intel_plane(plane)->id;
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + enum plane_id plane_id = plane->id;
> u64 rate;
>
> if (!plane_state->planar_linked_plane) {
> @@ -4282,7 +4274,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>
> /*
> * The slave plane might not iterate in
> - * drm_atomic_crtc_state_for_each_plane_state(),
> + * intel_atomic_crtc_state_for_each_plane_state(),
> * and needs the master plane state which may be
> * NULL if we try get_new_plane_state(), so we
> * always calculate from the master.
> @@ -5065,8 +5057,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> int ret;
>
> /*
> @@ -5075,10 +5067,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> */
> memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
> - &crtc_state->base) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
> + crtc_state) {
>
> if (INTEL_GEN(dev_priv) >= 11)
> ret = icl_build_plane_wm(crtc_state, plane_state);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state.
2019-10-04 11:34 ` [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state Maarten Lankhorst
2019-10-04 13:18 ` Ville Syrjälä
@ 2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Matt Roper @ 2019-10-07 19:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:53PM +0200, Maarten Lankhorst wrote:
> Instead of looking at drm_plane_state, look at intel_plane_state directly.
>
> This will allow us to make the watermarks bigjoiner aware, when we make it
> work for bigjoiner slave pipes as well.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 8 +++
> drivers/gpu/drm/i915/intel_pm.c | 60 ++++++++------------
> 2 files changed, 33 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 4ded64fcbc6c..bc2cf4bec0e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -440,6 +440,14 @@ enum phy_fia {
> (__i)--) \
> for_each_if(crtc)
>
> +#define intel_atomic_crtc_state_for_each_plane_state( \
> + plane, plane_state, \
> + crtc_state) \
> + for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> + ((crtc_state)->base.plane_mask)) \
> + for_each_if ((plane_state = \
> + to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> +
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfcf03ab5245..6aeaad587a20 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3089,8 +3089,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> struct intel_pipe_wm *pipe_wm;
> struct drm_device *dev = state->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_plane *plane;
> - const struct drm_plane_state *plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> const struct intel_plane_state *pristate = NULL;
> const struct intel_plane_state *sprstate = NULL;
> const struct intel_plane_state *curstate = NULL;
> @@ -3099,15 +3099,13 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>
> pipe_wm = &crtc_state->wm.ilk.optimal;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
> - const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
> -
> - if (plane->type == DRM_PLANE_TYPE_PRIMARY)
> - pristate = ps;
> - else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
> - sprstate = ps;
> - else if (plane->type == DRM_PLANE_TYPE_CURSOR)
> - curstate = ps;
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> + pristate = plane_state;
> + else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
> + sprstate = plane_state;
> + else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
> + curstate = plane_state;
> }
>
> pipe_wm->pipe_enabled = crtc_state->base.active;
> @@ -4124,8 +4122,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> int crtc_clock, dotclk;
> u32 pipe_max_pixel_rate;
> uint_fixed_16_16_t pipe_downscale;
> @@ -4134,12 +4132,10 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> if (!crtc_state->base.enable)
> return 0;
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> uint_fixed_16_16_t plane_downscale;
> uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
> int bpp;
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
>
> if (!intel_wm_plane_visible(crtc_state, plane_state))
> continue;
> @@ -4227,18 +4223,16 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *uv_plane_data_rate)
> {
> struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> if (WARN_ON(!state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> - enum plane_id plane_id = to_intel_plane(plane)->id;
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + enum plane_id plane_id = plane->id;
> u64 rate;
>
> /* packed/y */
> @@ -4259,18 +4253,16 @@ static u64
> icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate)
> {
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> if (WARN_ON(!crtc_state->base.state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> - enum plane_id plane_id = to_intel_plane(plane)->id;
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> + enum plane_id plane_id = plane->id;
> u64 rate;
>
> if (!plane_state->planar_linked_plane) {
> @@ -4282,7 +4274,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>
> /*
> * The slave plane might not iterate in
> - * drm_atomic_crtc_state_for_each_plane_state(),
> + * intel_atomic_crtc_state_for_each_plane_state(),
> * and needs the master plane state which may be
> * NULL if we try get_new_plane_state(), so we
> * always calculate from the master.
> @@ -5065,8 +5057,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> - struct drm_plane *plane;
> - const struct drm_plane_state *drm_plane_state;
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> int ret;
>
> /*
> @@ -5075,10 +5067,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> */
> memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
>
> - drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
> - &crtc_state->base) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(drm_plane_state);
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
> + crtc_state) {
>
> if (INTEL_GEN(dev_priv) >= 11)
> ret = icl_build_plane_wm(crtc_state, plane_state);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (2 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 03/24] drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 13:22 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
2019-10-04 11:34 ` [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Maarten Lankhorst
` (22 subsequent siblings)
26 siblings, 2 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
We have a src and dect rectangle, use it instead of relying on
the core drm properties.
This removes the special case in the watermark code for cursor w/h.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 58 +++++++-------------
2 files changed, 53 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c3ac5a5c5185..9e34be48c770 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10591,16 +10591,16 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
/* ILK+ do this automagically */
if (HAS_GMCH(dev_priv) &&
plane_state->base.rotation & DRM_MODE_ROTATE_180)
- base += (plane_state->base.crtc_h *
- plane_state->base.crtc_w - 1) * fb->format->cpp[0];
+ base += (drm_rect_height(&plane_state->base.dst) *
+ drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
return base;
}
static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
{
- int x = plane_state->base.crtc_x;
- int y = plane_state->base.crtc_y;
+ int x = plane_state->base.dst.x1;
+ int y = plane_state->base.dst.y1;
u32 pos = 0;
if (x < 0) {
@@ -10622,8 +10622,8 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
{
const struct drm_mode_config *config =
&plane_state->base.plane->dev->mode_config;
- int width = plane_state->base.crtc_w;
- int height = plane_state->base.crtc_h;
+ int width = drm_rect_width(&plane_state->base.dst);
+ int height = drm_rect_height(&plane_state->base.dst);
return width > 0 && width <= config->cursor_width &&
height > 0 && height <= config->cursor_height;
@@ -10642,8 +10642,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
if (!plane_state->base.visible)
return 0;
- src_x = plane_state->base.src_x >> 16;
- src_y = plane_state->base.src_y >> 16;
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
@@ -10678,6 +10678,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ /* Use the unclipped src/dst rectangles, which we program to hw */
+ plane_state->base.src = drm_plane_state_src(&plane_state->base);
+ plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
+
ret = intel_cursor_check_surface(plane_state);
if (ret)
return ret;
@@ -10720,7 +10724,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
{
- int width = plane_state->base.crtc_w;
+ int width = drm_rect_width(&plane_state->base.dst);
/*
* 845g/865g are only limited by the width of their cursors,
@@ -10746,8 +10750,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
/* Check for which cursor types we support */
if (!i845_cursor_size_ok(plane_state)) {
DRM_DEBUG("Cursor dimension %dx%d not supported\n",
- plane_state->base.crtc_w,
- plane_state->base.crtc_h);
+ drm_rect_width(&plane_state->base.dst),
+ drm_rect_height(&plane_state->base.dst));
return -EINVAL;
}
@@ -10780,8 +10784,8 @@ static void i845_update_cursor(struct intel_plane *plane,
unsigned long irqflags;
if (plane_state && plane_state->base.visible) {
- unsigned int width = plane_state->base.crtc_w;
- unsigned int height = plane_state->base.crtc_h;
+ unsigned int width = drm_rect_width(&plane_state->base.src);
+ unsigned int height = drm_rect_height(&plane_state->base.dst);
cntl = plane_state->ctl |
i845_cursor_ctl_crtc(crtc_state);
@@ -10883,7 +10887,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
- switch (plane_state->base.crtc_w) {
+ switch (drm_rect_width(&plane_state->base.dst)) {
case 64:
cntl |= MCURSOR_MODE_64_ARGB_AX;
break;
@@ -10894,7 +10898,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
cntl |= MCURSOR_MODE_256_ARGB_AX;
break;
default:
- MISSING_CASE(plane_state->base.crtc_w);
+ MISSING_CASE(drm_rect_width(&plane_state->base.dst));
return 0;
}
@@ -10908,8 +10912,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- int width = plane_state->base.crtc_w;
- int height = plane_state->base.crtc_h;
+ int width = drm_rect_width(&plane_state->base.dst);
+ int height = drm_rect_height(&plane_state->base.dst);
if (!intel_cursor_size_ok(plane_state))
return false;
@@ -10962,17 +10966,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
/* Check for which cursor types we support */
if (!i9xx_cursor_size_ok(plane_state)) {
DRM_DEBUG("Cursor dimension %dx%d not supported\n",
- plane_state->base.crtc_w,
- plane_state->base.crtc_h);
+ drm_rect_width(&plane_state->base.dst),
+ drm_rect_height(&plane_state->base.dst));
return -EINVAL;
}
WARN_ON(plane_state->base.visible &&
plane_state->color_plane[0].stride != fb->pitches[0]);
- if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
+ if (fb->pitches[0] !=
+ drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
- fb->pitches[0], plane_state->base.crtc_w);
+ fb->pitches[0],
+ drm_rect_width(&plane_state->base.dst));
return -EINVAL;
}
@@ -10987,7 +10993,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
* Refuse the put the cursor into that compromised position.
*/
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
- plane_state->base.visible && plane_state->base.crtc_x < 0) {
+ plane_state->base.visible && plane_state->base.dst.x1 < 0) {
DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
return -EINVAL;
}
@@ -11007,11 +11013,14 @@ static void i9xx_update_cursor(struct intel_plane *plane,
unsigned long irqflags;
if (plane_state && plane_state->base.visible) {
+ unsigned width = drm_rect_width(&plane_state->base.dst);
+ unsigned height = drm_rect_height(&plane_state->base.dst);
+
cntl = plane_state->ctl |
i9xx_cursor_ctl_crtc(crtc_state);
- if (plane_state->base.crtc_h != plane_state->base.crtc_w)
- fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
+ if (width != height)
+ fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6aeaad587a20..53358e33df1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1117,10 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
- if (plane->id == PLANE_CURSOR)
- width = plane_state->base.crtc_w;
- else
- width = drm_rect_width(&plane_state->base.dst);
+ width = drm_rect_width(&plane_state->base.dst);
if (plane->id == PLANE_CURSOR) {
wm = intel_wm_method2(clock, htotal, width, cpp, latency);
@@ -2549,7 +2546,8 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
return ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->base.adjusted_mode.crtc_htotal,
- plane_state->base.crtc_w, cpp, mem_value);
+ drm_rect_width(&plane_state->base.dst),
+ cpp, mem_value);
}
/* Only for WM_LP. */
@@ -4046,7 +4044,6 @@ static uint_fixed_16_16_t
skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 src_w, src_h, dst_w, dst_h;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
@@ -4054,27 +4051,17 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
return u32_to_fixed16(0);
- /* n.b., src is 16.16 fixed point, dst is whole integer */
- if (plane->id == PLANE_CURSOR) {
- /*
- * Cursors only support 0/180 degree rotation,
- * hence no need to account for rotation here.
- */
- src_w = plane_state->base.src_w >> 16;
- src_h = plane_state->base.src_h >> 16;
- dst_w = plane_state->base.crtc_w;
- dst_h = plane_state->base.crtc_h;
- } else {
- /*
- * Src coordinates are already rotated by 270 degrees for
- * the 90/270 degree plane rotation cases (to match the
- * GTT mapping), hence no need to account for rotation here.
- */
- src_w = drm_rect_width(&plane_state->base.src) >> 16;
- src_h = drm_rect_height(&plane_state->base.src) >> 16;
- dst_w = drm_rect_width(&plane_state->base.dst);
- dst_h = drm_rect_height(&plane_state->base.dst);
- }
+ /*
+ * Src coordinates are already rotated by 270 degrees for
+ * the 90/270 degree plane rotation cases (to match the
+ * GTT mapping), hence no need to account for rotation here.
+ *
+ * n.b., src is 16.16 fixed point, dst is whole integer.
+ */
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ dst_w = drm_rect_width(&plane_state->base.dst);
+ dst_h = drm_rect_height(&plane_state->base.dst);
fp_w_ratio = div_fixed16(src_w, dst_w);
fp_h_ratio = div_fixed16(src_h, dst_h);
@@ -4698,20 +4685,15 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
struct skl_wm_params *wp, int color_plane)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
const struct drm_framebuffer *fb = plane_state->base.fb;
int width;
- if (plane->id == PLANE_CURSOR) {
- width = plane_state->base.crtc_w;
- } else {
- /*
- * Src coordinates are already rotated by 270 degrees for
- * the 90/270 degree plane rotation cases (to match the
- * GTT mapping), hence no need to account for rotation here.
- */
- width = drm_rect_width(&plane_state->base.src) >> 16;
- }
+ /*
+ * Src coordinates are already rotated by 270 degrees for
+ * the 90/270 degree plane rotation cases (to match the
+ * GTT mapping), hence no need to account for rotation here.
+ */
+ width = drm_rect_width(&plane_state->base.src) >> 16;
return skl_compute_wm_params(crtc_state, width,
fb->format, fb->modifier,
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
2019-10-04 11:34 ` [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates Maarten Lankhorst
@ 2019-10-04 13:22 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 13:22 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
> We have a src and dect rectangle, use it instead of relying on
> the core drm properties.
>
> This removes the special case in the watermark code for cursor w/h.
I like getting rid of special cases. I guess the only concern I once
had is whether we'd need the clipped coordinates for something,
but I don't think we actually do.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++-------------
> 2 files changed, 53 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c3ac5a5c5185..9e34be48c770 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10591,16 +10591,16 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> /* ILK+ do this automagically */
> if (HAS_GMCH(dev_priv) &&
> plane_state->base.rotation & DRM_MODE_ROTATE_180)
> - base += (plane_state->base.crtc_h *
> - plane_state->base.crtc_w - 1) * fb->format->cpp[0];
> + base += (drm_rect_height(&plane_state->base.dst) *
> + drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
>
> return base;
> }
>
> static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
> {
> - int x = plane_state->base.crtc_x;
> - int y = plane_state->base.crtc_y;
> + int x = plane_state->base.dst.x1;
> + int y = plane_state->base.dst.y1;
> u32 pos = 0;
>
> if (x < 0) {
> @@ -10622,8 +10622,8 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> const struct drm_mode_config *config =
> &plane_state->base.plane->dev->mode_config;
> - int width = plane_state->base.crtc_w;
> - int height = plane_state->base.crtc_h;
> + int width = drm_rect_width(&plane_state->base.dst);
> + int height = drm_rect_height(&plane_state->base.dst);
>
> return width > 0 && width <= config->cursor_width &&
> height > 0 && height <= config->cursor_height;
> @@ -10642,8 +10642,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> if (!plane_state->base.visible)
> return 0;
>
> - src_x = plane_state->base.src_x >> 16;
> - src_y = plane_state->base.src_y >> 16;
> + src_x = plane_state->base.src.x1 >> 16;
> + src_y = plane_state->base.src.y1 >> 16;
>
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> @@ -10678,6 +10678,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + /* Use the unclipped src/dst rectangles, which we program to hw */
> + plane_state->base.src = drm_plane_state_src(&plane_state->base);
> + plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
> +
> ret = intel_cursor_check_surface(plane_state);
> if (ret)
> return ret;
> @@ -10720,7 +10724,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>
> static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> - int width = plane_state->base.crtc_w;
> + int width = drm_rect_width(&plane_state->base.dst);
>
> /*
> * 845g/865g are only limited by the width of their cursors,
> @@ -10746,8 +10750,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> /* Check for which cursor types we support */
> if (!i845_cursor_size_ok(plane_state)) {
> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
> - plane_state->base.crtc_w,
> - plane_state->base.crtc_h);
> + drm_rect_width(&plane_state->base.dst),
> + drm_rect_height(&plane_state->base.dst));
> return -EINVAL;
> }
>
> @@ -10780,8 +10784,8 @@ static void i845_update_cursor(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (plane_state && plane_state->base.visible) {
> - unsigned int width = plane_state->base.crtc_w;
> - unsigned int height = plane_state->base.crtc_h;
> + unsigned int width = drm_rect_width(&plane_state->base.src);
> + unsigned int height = drm_rect_height(&plane_state->base.dst);
>
> cntl = plane_state->ctl |
> i845_cursor_ctl_crtc(crtc_state);
> @@ -10883,7 +10887,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>
> - switch (plane_state->base.crtc_w) {
> + switch (drm_rect_width(&plane_state->base.dst)) {
> case 64:
> cntl |= MCURSOR_MODE_64_ARGB_AX;
> break;
> @@ -10894,7 +10898,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> cntl |= MCURSOR_MODE_256_ARGB_AX;
> break;
> default:
> - MISSING_CASE(plane_state->base.crtc_w);
> + MISSING_CASE(drm_rect_width(&plane_state->base.dst));
> return 0;
> }
>
> @@ -10908,8 +10912,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> - int width = plane_state->base.crtc_w;
> - int height = plane_state->base.crtc_h;
> + int width = drm_rect_width(&plane_state->base.dst);
> + int height = drm_rect_height(&plane_state->base.dst);
>
> if (!intel_cursor_size_ok(plane_state))
> return false;
> @@ -10962,17 +10966,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> /* Check for which cursor types we support */
> if (!i9xx_cursor_size_ok(plane_state)) {
> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
> - plane_state->base.crtc_w,
> - plane_state->base.crtc_h);
> + drm_rect_width(&plane_state->base.dst),
> + drm_rect_height(&plane_state->base.dst));
> return -EINVAL;
> }
>
> WARN_ON(plane_state->base.visible &&
> plane_state->color_plane[0].stride != fb->pitches[0]);
>
> - if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
> + if (fb->pitches[0] !=
> + drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
> DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
> - fb->pitches[0], plane_state->base.crtc_w);
> + fb->pitches[0],
> + drm_rect_width(&plane_state->base.dst));
> return -EINVAL;
> }
>
> @@ -10987,7 +10993,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> * Refuse the put the cursor into that compromised position.
> */
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
> - plane_state->base.visible && plane_state->base.crtc_x < 0) {
> + plane_state->base.visible && plane_state->base.dst.x1 < 0) {
> DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
> return -EINVAL;
> }
> @@ -11007,11 +11013,14 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (plane_state && plane_state->base.visible) {
> + unsigned width = drm_rect_width(&plane_state->base.dst);
> + unsigned height = drm_rect_height(&plane_state->base.dst);
> +
> cntl = plane_state->ctl |
> i9xx_cursor_ctl_crtc(crtc_state);
>
> - if (plane_state->base.crtc_h != plane_state->base.crtc_w)
> - fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
> + if (width != height)
> + fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6aeaad587a20..53358e33df1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1117,10 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
>
> - if (plane->id == PLANE_CURSOR)
> - width = plane_state->base.crtc_w;
> - else
> - width = drm_rect_width(&plane_state->base.dst);
> + width = drm_rect_width(&plane_state->base.dst);
>
> if (plane->id == PLANE_CURSOR) {
> wm = intel_wm_method2(clock, htotal, width, cpp, latency);
> @@ -2549,7 +2546,8 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>
> return ilk_wm_method2(crtc_state->pixel_rate,
> crtc_state->base.adjusted_mode.crtc_htotal,
> - plane_state->base.crtc_w, cpp, mem_value);
> + drm_rect_width(&plane_state->base.dst),
> + cpp, mem_value);
> }
>
> /* Only for WM_LP. */
> @@ -4046,7 +4044,6 @@ static uint_fixed_16_16_t
> skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 src_w, src_h, dst_w, dst_h;
> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> uint_fixed_16_16_t downscale_h, downscale_w;
> @@ -4054,27 +4051,17 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> return u32_to_fixed16(0);
>
> - /* n.b., src is 16.16 fixed point, dst is whole integer */
> - if (plane->id == PLANE_CURSOR) {
> - /*
> - * Cursors only support 0/180 degree rotation,
> - * hence no need to account for rotation here.
> - */
> - src_w = plane_state->base.src_w >> 16;
> - src_h = plane_state->base.src_h >> 16;
> - dst_w = plane_state->base.crtc_w;
> - dst_h = plane_state->base.crtc_h;
> - } else {
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - src_w = drm_rect_width(&plane_state->base.src) >> 16;
> - src_h = drm_rect_height(&plane_state->base.src) >> 16;
> - dst_w = drm_rect_width(&plane_state->base.dst);
> - dst_h = drm_rect_height(&plane_state->base.dst);
> - }
> + /*
> + * Src coordinates are already rotated by 270 degrees for
> + * the 90/270 degree plane rotation cases (to match the
> + * GTT mapping), hence no need to account for rotation here.
> + *
> + * n.b., src is 16.16 fixed point, dst is whole integer.
> + */
> + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + dst_w = drm_rect_width(&plane_state->base.dst);
> + dst_h = drm_rect_height(&plane_state->base.dst);
>
> fp_w_ratio = div_fixed16(src_w, dst_w);
> fp_h_ratio = div_fixed16(src_h, dst_h);
> @@ -4698,20 +4685,15 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> struct skl_wm_params *wp, int color_plane)
> {
> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> int width;
>
> - if (plane->id == PLANE_CURSOR) {
> - width = plane_state->base.crtc_w;
> - } else {
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - width = drm_rect_width(&plane_state->base.src) >> 16;
> - }
> + /*
> + * Src coordinates are already rotated by 270 degrees for
> + * the 90/270 degree plane rotation cases (to match the
> + * GTT mapping), hence no need to account for rotation here.
> + */
> + width = drm_rect_width(&plane_state->base.src) >> 16;
>
> return skl_compute_wm_params(crtc_state, width,
> fb->format, fb->modifier,
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
2019-10-04 11:34 ` [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates Maarten Lankhorst
2019-10-04 13:22 ` Ville Syrjälä
@ 2019-10-07 19:37 ` Matt Roper
2019-10-10 12:10 ` Maarten Lankhorst
2019-10-10 14:04 ` Maarten Lankhorst
1 sibling, 2 replies; 60+ messages in thread
From: Matt Roper @ 2019-10-07 19:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
> We have a src and dect rectangle, use it instead of relying on
> the core drm properties.
>
> This removes the special case in the watermark code for cursor w/h.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
I think you should make it more clear in the commit message here that
you're actually overwriting the clipped coordinates in src/dst with the
unclipped coordinates that we program into our hardware. I missed that
the first time reading through the patch; using clipped coordinates
would obviously cause lots of failures.
Actually, even if this is safe at the moment, we're violating the
documented expectations of the DRM core. I'd suggest also adding a drm
core patch that updates the comment on drm_plane_state to indicate that
the contents may or may not be clipped (driver-specific) and that the
core shouldn't assume either way.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++-------------
> 2 files changed, 53 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c3ac5a5c5185..9e34be48c770 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10591,16 +10591,16 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> /* ILK+ do this automagically */
> if (HAS_GMCH(dev_priv) &&
> plane_state->base.rotation & DRM_MODE_ROTATE_180)
> - base += (plane_state->base.crtc_h *
> - plane_state->base.crtc_w - 1) * fb->format->cpp[0];
> + base += (drm_rect_height(&plane_state->base.dst) *
> + drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
>
> return base;
> }
>
> static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
> {
> - int x = plane_state->base.crtc_x;
> - int y = plane_state->base.crtc_y;
> + int x = plane_state->base.dst.x1;
> + int y = plane_state->base.dst.y1;
> u32 pos = 0;
>
> if (x < 0) {
> @@ -10622,8 +10622,8 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> const struct drm_mode_config *config =
> &plane_state->base.plane->dev->mode_config;
> - int width = plane_state->base.crtc_w;
> - int height = plane_state->base.crtc_h;
> + int width = drm_rect_width(&plane_state->base.dst);
> + int height = drm_rect_height(&plane_state->base.dst);
>
> return width > 0 && width <= config->cursor_width &&
> height > 0 && height <= config->cursor_height;
> @@ -10642,8 +10642,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> if (!plane_state->base.visible)
> return 0;
>
> - src_x = plane_state->base.src_x >> 16;
> - src_y = plane_state->base.src_y >> 16;
> + src_x = plane_state->base.src.x1 >> 16;
> + src_y = plane_state->base.src.y1 >> 16;
>
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> @@ -10678,6 +10678,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + /* Use the unclipped src/dst rectangles, which we program to hw */
> + plane_state->base.src = drm_plane_state_src(&plane_state->base);
> + plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
> +
> ret = intel_cursor_check_surface(plane_state);
> if (ret)
> return ret;
> @@ -10720,7 +10724,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>
> static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> - int width = plane_state->base.crtc_w;
> + int width = drm_rect_width(&plane_state->base.dst);
>
> /*
> * 845g/865g are only limited by the width of their cursors,
> @@ -10746,8 +10750,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> /* Check for which cursor types we support */
> if (!i845_cursor_size_ok(plane_state)) {
> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
> - plane_state->base.crtc_w,
> - plane_state->base.crtc_h);
> + drm_rect_width(&plane_state->base.dst),
> + drm_rect_height(&plane_state->base.dst));
> return -EINVAL;
> }
>
> @@ -10780,8 +10784,8 @@ static void i845_update_cursor(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (plane_state && plane_state->base.visible) {
> - unsigned int width = plane_state->base.crtc_w;
> - unsigned int height = plane_state->base.crtc_h;
> + unsigned int width = drm_rect_width(&plane_state->base.src);
> + unsigned int height = drm_rect_height(&plane_state->base.dst);
>
> cntl = plane_state->ctl |
> i845_cursor_ctl_crtc(crtc_state);
> @@ -10883,7 +10887,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
> cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>
> - switch (plane_state->base.crtc_w) {
> + switch (drm_rect_width(&plane_state->base.dst)) {
> case 64:
> cntl |= MCURSOR_MODE_64_ARGB_AX;
> break;
> @@ -10894,7 +10898,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> cntl |= MCURSOR_MODE_256_ARGB_AX;
> break;
> default:
> - MISSING_CASE(plane_state->base.crtc_w);
> + MISSING_CASE(drm_rect_width(&plane_state->base.dst));
> return 0;
> }
>
> @@ -10908,8 +10912,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> - int width = plane_state->base.crtc_w;
> - int height = plane_state->base.crtc_h;
> + int width = drm_rect_width(&plane_state->base.dst);
> + int height = drm_rect_height(&plane_state->base.dst);
>
> if (!intel_cursor_size_ok(plane_state))
> return false;
> @@ -10962,17 +10966,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> /* Check for which cursor types we support */
> if (!i9xx_cursor_size_ok(plane_state)) {
> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
> - plane_state->base.crtc_w,
> - plane_state->base.crtc_h);
> + drm_rect_width(&plane_state->base.dst),
> + drm_rect_height(&plane_state->base.dst));
> return -EINVAL;
> }
>
> WARN_ON(plane_state->base.visible &&
> plane_state->color_plane[0].stride != fb->pitches[0]);
>
> - if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
> + if (fb->pitches[0] !=
> + drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
> DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
> - fb->pitches[0], plane_state->base.crtc_w);
> + fb->pitches[0],
> + drm_rect_width(&plane_state->base.dst));
> return -EINVAL;
> }
>
> @@ -10987,7 +10993,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> * Refuse the put the cursor into that compromised position.
> */
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
> - plane_state->base.visible && plane_state->base.crtc_x < 0) {
> + plane_state->base.visible && plane_state->base.dst.x1 < 0) {
> DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
> return -EINVAL;
> }
> @@ -11007,11 +11013,14 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (plane_state && plane_state->base.visible) {
> + unsigned width = drm_rect_width(&plane_state->base.dst);
> + unsigned height = drm_rect_height(&plane_state->base.dst);
> +
> cntl = plane_state->ctl |
> i9xx_cursor_ctl_crtc(crtc_state);
>
> - if (plane_state->base.crtc_h != plane_state->base.crtc_w)
> - fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
> + if (width != height)
> + fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
>
> base = intel_cursor_base(plane_state);
> pos = intel_cursor_position(plane_state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6aeaad587a20..53358e33df1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1117,10 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
>
> - if (plane->id == PLANE_CURSOR)
> - width = plane_state->base.crtc_w;
> - else
> - width = drm_rect_width(&plane_state->base.dst);
> + width = drm_rect_width(&plane_state->base.dst);
>
> if (plane->id == PLANE_CURSOR) {
> wm = intel_wm_method2(clock, htotal, width, cpp, latency);
> @@ -2549,7 +2546,8 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>
> return ilk_wm_method2(crtc_state->pixel_rate,
> crtc_state->base.adjusted_mode.crtc_htotal,
> - plane_state->base.crtc_w, cpp, mem_value);
> + drm_rect_width(&plane_state->base.dst),
> + cpp, mem_value);
> }
>
> /* Only for WM_LP. */
> @@ -4046,7 +4044,6 @@ static uint_fixed_16_16_t
> skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 src_w, src_h, dst_w, dst_h;
> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> uint_fixed_16_16_t downscale_h, downscale_w;
> @@ -4054,27 +4051,17 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> return u32_to_fixed16(0);
>
> - /* n.b., src is 16.16 fixed point, dst is whole integer */
> - if (plane->id == PLANE_CURSOR) {
> - /*
> - * Cursors only support 0/180 degree rotation,
> - * hence no need to account for rotation here.
> - */
> - src_w = plane_state->base.src_w >> 16;
> - src_h = plane_state->base.src_h >> 16;
> - dst_w = plane_state->base.crtc_w;
> - dst_h = plane_state->base.crtc_h;
> - } else {
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - src_w = drm_rect_width(&plane_state->base.src) >> 16;
> - src_h = drm_rect_height(&plane_state->base.src) >> 16;
> - dst_w = drm_rect_width(&plane_state->base.dst);
> - dst_h = drm_rect_height(&plane_state->base.dst);
> - }
> + /*
> + * Src coordinates are already rotated by 270 degrees for
> + * the 90/270 degree plane rotation cases (to match the
> + * GTT mapping), hence no need to account for rotation here.
> + *
> + * n.b., src is 16.16 fixed point, dst is whole integer.
> + */
> + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> + dst_w = drm_rect_width(&plane_state->base.dst);
> + dst_h = drm_rect_height(&plane_state->base.dst);
>
> fp_w_ratio = div_fixed16(src_w, dst_w);
> fp_h_ratio = div_fixed16(src_h, dst_h);
> @@ -4698,20 +4685,15 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> struct skl_wm_params *wp, int color_plane)
> {
> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> int width;
>
> - if (plane->id == PLANE_CURSOR) {
> - width = plane_state->base.crtc_w;
> - } else {
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - width = drm_rect_width(&plane_state->base.src) >> 16;
> - }
> + /*
> + * Src coordinates are already rotated by 270 degrees for
> + * the 90/270 degree plane rotation cases (to match the
> + * GTT mapping), hence no need to account for rotation here.
> + */
> + width = drm_rect_width(&plane_state->base.src) >> 16;
>
> return skl_compute_wm_params(crtc_state, width,
> fb->format, fb->modifier,
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
2019-10-07 19:37 ` Matt Roper
@ 2019-10-10 12:10 ` Maarten Lankhorst
2019-10-10 14:04 ` Maarten Lankhorst
1 sibling, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 12:10 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> I think you should make it more clear in the commit message here that
> you're actually overwriting the clipped coordinates in src/dst with the
> unclipped coordinates that we program into our hardware. I missed that
> the first time reading through the patch; using clipped coordinates
> would obviously cause lots of failures.
>
> Actually, even if this is safe at the moment, we're violating the
> documented expectations of the DRM core. I'd suggest also adding a drm
> core patch that updates the comment on drm_plane_state to indicate that
> the contents may or may not be clipped (driver-specific) and that the
> core shouldn't assume either way.
https://patchwork.freedesktop.org/patch/335245/?series=67840&rev=1
?
~Maarten
>
> Matt
>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++--------
>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++-------------
>> 2 files changed, 53 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index c3ac5a5c5185..9e34be48c770 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -10591,16 +10591,16 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
>> /* ILK+ do this automagically */
>> if (HAS_GMCH(dev_priv) &&
>> plane_state->base.rotation & DRM_MODE_ROTATE_180)
>> - base += (plane_state->base.crtc_h *
>> - plane_state->base.crtc_w - 1) * fb->format->cpp[0];
>> + base += (drm_rect_height(&plane_state->base.dst) *
>> + drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
>>
>> return base;
>> }
>>
>> static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
>> {
>> - int x = plane_state->base.crtc_x;
>> - int y = plane_state->base.crtc_y;
>> + int x = plane_state->base.dst.x1;
>> + int y = plane_state->base.dst.y1;
>> u32 pos = 0;
>>
>> if (x < 0) {
>> @@ -10622,8 +10622,8 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
>> {
>> const struct drm_mode_config *config =
>> &plane_state->base.plane->dev->mode_config;
>> - int width = plane_state->base.crtc_w;
>> - int height = plane_state->base.crtc_h;
>> + int width = drm_rect_width(&plane_state->base.dst);
>> + int height = drm_rect_height(&plane_state->base.dst);
>>
>> return width > 0 && width <= config->cursor_width &&
>> height > 0 && height <= config->cursor_height;
>> @@ -10642,8 +10642,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
>> if (!plane_state->base.visible)
>> return 0;
>>
>> - src_x = plane_state->base.src_x >> 16;
>> - src_y = plane_state->base.src_y >> 16;
>> + src_x = plane_state->base.src.x1 >> 16;
>> + src_y = plane_state->base.src.y1 >> 16;
>>
>> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>> offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
>> @@ -10678,6 +10678,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
>> if (ret)
>> return ret;
>>
>> + /* Use the unclipped src/dst rectangles, which we program to hw */
>> + plane_state->base.src = drm_plane_state_src(&plane_state->base);
>> + plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
>> +
>> ret = intel_cursor_check_surface(plane_state);
>> if (ret)
>> return ret;
>> @@ -10720,7 +10724,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
>>
>> static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
>> {
>> - int width = plane_state->base.crtc_w;
>> + int width = drm_rect_width(&plane_state->base.dst);
>>
>> /*
>> * 845g/865g are only limited by the width of their cursors,
>> @@ -10746,8 +10750,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
>> /* Check for which cursor types we support */
>> if (!i845_cursor_size_ok(plane_state)) {
>> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
>> - plane_state->base.crtc_w,
>> - plane_state->base.crtc_h);
>> + drm_rect_width(&plane_state->base.dst),
>> + drm_rect_height(&plane_state->base.dst));
>> return -EINVAL;
>> }
>>
>> @@ -10780,8 +10784,8 @@ static void i845_update_cursor(struct intel_plane *plane,
>> unsigned long irqflags;
>>
>> if (plane_state && plane_state->base.visible) {
>> - unsigned int width = plane_state->base.crtc_w;
>> - unsigned int height = plane_state->base.crtc_h;
>> + unsigned int width = drm_rect_width(&plane_state->base.src);
>> + unsigned int height = drm_rect_height(&plane_state->base.dst);
>>
>> cntl = plane_state->ctl |
>> i845_cursor_ctl_crtc(crtc_state);
>> @@ -10883,7 +10887,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
>> cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
>>
>> - switch (plane_state->base.crtc_w) {
>> + switch (drm_rect_width(&plane_state->base.dst)) {
>> case 64:
>> cntl |= MCURSOR_MODE_64_ARGB_AX;
>> break;
>> @@ -10894,7 +10898,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
>> cntl |= MCURSOR_MODE_256_ARGB_AX;
>> break;
>> default:
>> - MISSING_CASE(plane_state->base.crtc_w);
>> + MISSING_CASE(drm_rect_width(&plane_state->base.dst));
>> return 0;
>> }
>>
>> @@ -10908,8 +10912,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
>> {
>> struct drm_i915_private *dev_priv =
>> to_i915(plane_state->base.plane->dev);
>> - int width = plane_state->base.crtc_w;
>> - int height = plane_state->base.crtc_h;
>> + int width = drm_rect_width(&plane_state->base.dst);
>> + int height = drm_rect_height(&plane_state->base.dst);
>>
>> if (!intel_cursor_size_ok(plane_state))
>> return false;
>> @@ -10962,17 +10966,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
>> /* Check for which cursor types we support */
>> if (!i9xx_cursor_size_ok(plane_state)) {
>> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
>> - plane_state->base.crtc_w,
>> - plane_state->base.crtc_h);
>> + drm_rect_width(&plane_state->base.dst),
>> + drm_rect_height(&plane_state->base.dst));
>> return -EINVAL;
>> }
>>
>> WARN_ON(plane_state->base.visible &&
>> plane_state->color_plane[0].stride != fb->pitches[0]);
>>
>> - if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
>> + if (fb->pitches[0] !=
>> + drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
>> DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
>> - fb->pitches[0], plane_state->base.crtc_w);
>> + fb->pitches[0],
>> + drm_rect_width(&plane_state->base.dst));
>> return -EINVAL;
>> }
>>
>> @@ -10987,7 +10993,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
>> * Refuse the put the cursor into that compromised position.
>> */
>> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
>> - plane_state->base.visible && plane_state->base.crtc_x < 0) {
>> + plane_state->base.visible && plane_state->base.dst.x1 < 0) {
>> DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
>> return -EINVAL;
>> }
>> @@ -11007,11 +11013,14 @@ static void i9xx_update_cursor(struct intel_plane *plane,
>> unsigned long irqflags;
>>
>> if (plane_state && plane_state->base.visible) {
>> + unsigned width = drm_rect_width(&plane_state->base.dst);
>> + unsigned height = drm_rect_height(&plane_state->base.dst);
>> +
>> cntl = plane_state->ctl |
>> i9xx_cursor_ctl_crtc(crtc_state);
>>
>> - if (plane_state->base.crtc_h != plane_state->base.crtc_w)
>> - fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
>> + if (width != height)
>> + fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
>>
>> base = intel_cursor_base(plane_state);
>> pos = intel_cursor_position(plane_state);
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 6aeaad587a20..53358e33df1b 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -1117,10 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
>> clock = adjusted_mode->crtc_clock;
>> htotal = adjusted_mode->crtc_htotal;
>>
>> - if (plane->id == PLANE_CURSOR)
>> - width = plane_state->base.crtc_w;
>> - else
>> - width = drm_rect_width(&plane_state->base.dst);
>> + width = drm_rect_width(&plane_state->base.dst);
>>
>> if (plane->id == PLANE_CURSOR) {
>> wm = intel_wm_method2(clock, htotal, width, cpp, latency);
>> @@ -2549,7 +2546,8 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>>
>> return ilk_wm_method2(crtc_state->pixel_rate,
>> crtc_state->base.adjusted_mode.crtc_htotal,
>> - plane_state->base.crtc_w, cpp, mem_value);
>> + drm_rect_width(&plane_state->base.dst),
>> + cpp, mem_value);
>> }
>>
>> /* Only for WM_LP. */
>> @@ -4046,7 +4044,6 @@ static uint_fixed_16_16_t
>> skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state)
>> {
>> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> u32 src_w, src_h, dst_w, dst_h;
>> uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
>> uint_fixed_16_16_t downscale_h, downscale_w;
>> @@ -4054,27 +4051,17 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
>> if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
>> return u32_to_fixed16(0);
>>
>> - /* n.b., src is 16.16 fixed point, dst is whole integer */
>> - if (plane->id == PLANE_CURSOR) {
>> - /*
>> - * Cursors only support 0/180 degree rotation,
>> - * hence no need to account for rotation here.
>> - */
>> - src_w = plane_state->base.src_w >> 16;
>> - src_h = plane_state->base.src_h >> 16;
>> - dst_w = plane_state->base.crtc_w;
>> - dst_h = plane_state->base.crtc_h;
>> - } else {
>> - /*
>> - * Src coordinates are already rotated by 270 degrees for
>> - * the 90/270 degree plane rotation cases (to match the
>> - * GTT mapping), hence no need to account for rotation here.
>> - */
>> - src_w = drm_rect_width(&plane_state->base.src) >> 16;
>> - src_h = drm_rect_height(&plane_state->base.src) >> 16;
>> - dst_w = drm_rect_width(&plane_state->base.dst);
>> - dst_h = drm_rect_height(&plane_state->base.dst);
>> - }
>> + /*
>> + * Src coordinates are already rotated by 270 degrees for
>> + * the 90/270 degree plane rotation cases (to match the
>> + * GTT mapping), hence no need to account for rotation here.
>> + *
>> + * n.b., src is 16.16 fixed point, dst is whole integer.
>> + */
>> + src_w = drm_rect_width(&plane_state->base.src) >> 16;
>> + src_h = drm_rect_height(&plane_state->base.src) >> 16;
>> + dst_w = drm_rect_width(&plane_state->base.dst);
>> + dst_h = drm_rect_height(&plane_state->base.dst);
>>
>> fp_w_ratio = div_fixed16(src_w, dst_w);
>> fp_h_ratio = div_fixed16(src_h, dst_h);
>> @@ -4698,20 +4685,15 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state,
>> struct skl_wm_params *wp, int color_plane)
>> {
>> - struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> const struct drm_framebuffer *fb = plane_state->base.fb;
>> int width;
>>
>> - if (plane->id == PLANE_CURSOR) {
>> - width = plane_state->base.crtc_w;
>> - } else {
>> - /*
>> - * Src coordinates are already rotated by 270 degrees for
>> - * the 90/270 degree plane rotation cases (to match the
>> - * GTT mapping), hence no need to account for rotation here.
>> - */
>> - width = drm_rect_width(&plane_state->base.src) >> 16;
>> - }
>> + /*
>> + * Src coordinates are already rotated by 270 degrees for
>> + * the 90/270 degree plane rotation cases (to match the
>> + * GTT mapping), hence no need to account for rotation here.
>> + */
>> + width = drm_rect_width(&plane_state->base.src) >> 16;
>>
>> return skl_compute_wm_params(crtc_state, width,
>> fb->format, fb->modifier,
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
2019-10-07 19:37 ` Matt Roper
2019-10-10 12:10 ` Maarten Lankhorst
@ 2019-10-10 14:04 ` Maarten Lankhorst
1 sibling, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 14:04 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> I think you should make it more clear in the commit message here that
> you're actually overwriting the clipped coordinates in src/dst with the
> unclipped coordinates that we program into our hardware. I missed that
> the first time reading through the patch; using clipped coordinates
> would obviously cause lots of failures.
>
> Actually, even if this is safe at the moment, we're violating the
> documented expectations of the DRM core. I'd suggest also adding a drm
> core patch that updates the comment on drm_plane_state to indicate that
> the contents may or may not be clipped (driver-specific) and that the
> core shouldn't assume either way.
Updated the core's expectations, to explicitly allow the unclipped coordinates,
and pushed patch 2-6 with the feedback.
Thanks for reviews all. :)
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (3 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 13:23 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
2019-10-04 11:34 ` [PATCH 06/24] drm/i915: Remove begin/finish_crtc_commit, v4 Maarten Lankhorst
` (21 subsequent siblings)
26 siblings, 2 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
We need to look at the hw fb in the plane split, so replace all the places
that use drm_plane_state with intel_plane_state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++---------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e34be48c770..b5ed097d6a59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14380,12 +14380,14 @@ static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
*/
int
intel_prepare_plane_fb(struct drm_plane *plane,
- struct drm_plane_state *new_state)
+ struct drm_plane_state *_new_plane_state)
{
+ struct intel_plane_state *new_plane_state =
+ to_intel_plane_state(_new_plane_state);
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(new_state->state);
+ to_intel_atomic_state(new_plane_state->base.state);
struct drm_i915_private *dev_priv = to_i915(plane->dev);
- struct drm_framebuffer *fb = new_state->fb;
+ struct drm_framebuffer *fb = new_plane_state->base.fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
int ret;
@@ -14416,9 +14418,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
}
- if (new_state->fence) { /* explicit fencing */
+ if (new_plane_state->base.fence) { /* explicit fencing */
ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
- new_state->fence,
+ new_plane_state->base.fence,
I915_FENCE_TIMEOUT,
GFP_KERNEL);
if (ret < 0)
@@ -14438,7 +14440,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
return ret;
}
- ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
+ ret = intel_plane_pin_fb(new_plane_state);
mutex_unlock(&dev_priv->drm.struct_mutex);
i915_gem_object_unpin_pages(obj);
@@ -14448,7 +14450,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
fb_obj_bump_render_priority(obj);
intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
- if (!new_state->fence) { /* implicit fencing */
+ if (!new_plane_state->base.fence) { /* implicit fencing */
struct dma_fence *fence;
ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
@@ -14460,11 +14462,11 @@ intel_prepare_plane_fb(struct drm_plane *plane,
fence = dma_resv_get_excl_rcu(obj->base.resv);
if (fence) {
- add_rps_boost_after_vblank(new_state->crtc, fence);
+ add_rps_boost_after_vblank(new_plane_state->base.crtc, fence);
dma_fence_put(fence);
}
} else {
- add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
+ add_rps_boost_after_vblank(new_plane_state->base.crtc, new_plane_state->base.fence);
}
/*
@@ -14494,10 +14496,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
*/
void
intel_cleanup_plane_fb(struct drm_plane *plane,
- struct drm_plane_state *old_state)
+ struct drm_plane_state *_old_plane_state)
{
+ struct intel_plane_state *old_plane_state =
+ to_intel_plane_state(_old_plane_state);
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(old_state->state);
+ to_intel_atomic_state(old_plane_state->base.state);
struct drm_i915_private *dev_priv = to_i915(plane->dev);
if (intel_state->rps_interactive) {
@@ -14507,7 +14511,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
/* Should only be called after a successful intel_prepare_plane_fb()! */
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_plane_unpin_fb(to_intel_plane_state(old_state));
+ intel_plane_unpin_fb(old_plane_state);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
2019-10-04 11:34 ` [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Maarten Lankhorst
@ 2019-10-04 13:23 ` Ville Syrjälä
2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 13:23 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:55PM +0200, Maarten Lankhorst wrote:
> We need to look at the hw fb in the plane split, so replace all the places
> that use drm_plane_state with intel_plane_state.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++---------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9e34be48c770..b5ed097d6a59 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14380,12 +14380,14 @@ static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
> */
> int
> intel_prepare_plane_fb(struct drm_plane *plane,
> - struct drm_plane_state *new_state)
> + struct drm_plane_state *_new_plane_state)
> {
> + struct intel_plane_state *new_plane_state =
> + to_intel_plane_state(_new_plane_state);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_state->state);
> + to_intel_atomic_state(new_plane_state->base.state);
> struct drm_i915_private *dev_priv = to_i915(plane->dev);
> - struct drm_framebuffer *fb = new_state->fb;
> + struct drm_framebuffer *fb = new_plane_state->base.fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> int ret;
> @@ -14416,9 +14418,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
> }
>
> - if (new_state->fence) { /* explicit fencing */
> + if (new_plane_state->base.fence) { /* explicit fencing */
> ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
> - new_state->fence,
> + new_plane_state->base.fence,
> I915_FENCE_TIMEOUT,
> GFP_KERNEL);
> if (ret < 0)
> @@ -14438,7 +14440,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> return ret;
> }
>
> - ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
> + ret = intel_plane_pin_fb(new_plane_state);
>
> mutex_unlock(&dev_priv->drm.struct_mutex);
> i915_gem_object_unpin_pages(obj);
> @@ -14448,7 +14450,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> fb_obj_bump_render_priority(obj);
> intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
>
> - if (!new_state->fence) { /* implicit fencing */
> + if (!new_plane_state->base.fence) { /* implicit fencing */
> struct dma_fence *fence;
>
> ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
> @@ -14460,11 +14462,11 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>
> fence = dma_resv_get_excl_rcu(obj->base.resv);
> if (fence) {
> - add_rps_boost_after_vblank(new_state->crtc, fence);
> + add_rps_boost_after_vblank(new_plane_state->base.crtc, fence);
> dma_fence_put(fence);
> }
> } else {
> - add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
> + add_rps_boost_after_vblank(new_plane_state->base.crtc, new_plane_state->base.fence);
> }
>
> /*
> @@ -14494,10 +14496,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> */
> void
> intel_cleanup_plane_fb(struct drm_plane *plane,
> - struct drm_plane_state *old_state)
> + struct drm_plane_state *_old_plane_state)
> {
> + struct intel_plane_state *old_plane_state =
> + to_intel_plane_state(_old_plane_state);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(old_state->state);
> + to_intel_atomic_state(old_plane_state->base.state);
> struct drm_i915_private *dev_priv = to_i915(plane->dev);
>
> if (intel_state->rps_interactive) {
> @@ -14507,7 +14511,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
>
> /* Should only be called after a successful intel_prepare_plane_fb()! */
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_plane_unpin_fb(to_intel_plane_state(old_state));
> + intel_plane_unpin_fb(old_plane_state);
> mutex_unlock(&dev_priv->drm.struct_mutex);
> }
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
2019-10-04 11:34 ` [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Maarten Lankhorst
2019-10-04 13:23 ` Ville Syrjälä
@ 2019-10-07 19:37 ` Matt Roper
1 sibling, 0 replies; 60+ messages in thread
From: Matt Roper @ 2019-10-07 19:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:55PM +0200, Maarten Lankhorst wrote:
> We need to look at the hw fb in the plane split, so replace all the places
> that use drm_plane_state with intel_plane_state.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++---------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9e34be48c770..b5ed097d6a59 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14380,12 +14380,14 @@ static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
> */
> int
> intel_prepare_plane_fb(struct drm_plane *plane,
> - struct drm_plane_state *new_state)
> + struct drm_plane_state *_new_plane_state)
> {
> + struct intel_plane_state *new_plane_state =
> + to_intel_plane_state(_new_plane_state);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_state->state);
> + to_intel_atomic_state(new_plane_state->base.state);
> struct drm_i915_private *dev_priv = to_i915(plane->dev);
> - struct drm_framebuffer *fb = new_state->fb;
> + struct drm_framebuffer *fb = new_plane_state->base.fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> int ret;
> @@ -14416,9 +14418,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> }
> }
>
> - if (new_state->fence) { /* explicit fencing */
> + if (new_plane_state->base.fence) { /* explicit fencing */
> ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
> - new_state->fence,
> + new_plane_state->base.fence,
> I915_FENCE_TIMEOUT,
> GFP_KERNEL);
> if (ret < 0)
> @@ -14438,7 +14440,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> return ret;
> }
>
> - ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
> + ret = intel_plane_pin_fb(new_plane_state);
>
> mutex_unlock(&dev_priv->drm.struct_mutex);
> i915_gem_object_unpin_pages(obj);
> @@ -14448,7 +14450,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> fb_obj_bump_render_priority(obj);
> intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
>
> - if (!new_state->fence) { /* implicit fencing */
> + if (!new_plane_state->base.fence) { /* implicit fencing */
> struct dma_fence *fence;
>
> ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
> @@ -14460,11 +14462,11 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>
> fence = dma_resv_get_excl_rcu(obj->base.resv);
> if (fence) {
> - add_rps_boost_after_vblank(new_state->crtc, fence);
> + add_rps_boost_after_vblank(new_plane_state->base.crtc, fence);
> dma_fence_put(fence);
> }
> } else {
> - add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
> + add_rps_boost_after_vblank(new_plane_state->base.crtc, new_plane_state->base.fence);
The two changes in this hunk require line wraps now to stay <80 chars.
Otherwise,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> }
>
> /*
> @@ -14494,10 +14496,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> */
> void
> intel_cleanup_plane_fb(struct drm_plane *plane,
> - struct drm_plane_state *old_state)
> + struct drm_plane_state *_old_plane_state)
> {
> + struct intel_plane_state *old_plane_state =
> + to_intel_plane_state(_old_plane_state);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(old_state->state);
> + to_intel_atomic_state(old_plane_state->base.state);
> struct drm_i915_private *dev_priv = to_i915(plane->dev);
>
> if (intel_state->rps_interactive) {
> @@ -14507,7 +14511,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
>
> /* Should only be called after a successful intel_prepare_plane_fb()! */
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_plane_unpin_fb(to_intel_plane_state(old_state));
> + intel_plane_unpin_fb(old_plane_state);
> mutex_unlock(&dev_priv->drm.struct_mutex);
> }
>
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 06/24] drm/i915: Remove begin/finish_crtc_commit, v4.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (4 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 05/24] drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-07 19:43 ` Matt Roper
2019-10-04 11:34 ` [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check() Maarten Lankhorst
` (20 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Pull in all the changes done during fastset as well. It makes no sense
for it to still exist as a separate function.
Changes since v1:
- Inline intel_update_pipe_config()
Changes since v2:
- Add comments suggested by matt.
- Reorder commit_pipe_config() to remove all nesting. (Ville, Matt)
- Use intel_set_pipe_src_size((). (Matt)
Changes since v3:
- Move atomic_update_watermarks closer to the plane calls.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 210 +++++++++----------
1 file changed, 99 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b5ed097d6a59..ecb15420b5ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -135,8 +135,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
-static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
-static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -4408,45 +4406,6 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
-static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
- const struct intel_crtc_state *new_crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
- /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
- crtc->base.mode = new_crtc_state->base.mode;
-
- /*
- * Update pipe size and adjust fitter if needed: the reason for this is
- * that in compute_mode_changes we check the native mode (not the pfit
- * mode) to see if we can flip rather than do a full mode set. In the
- * fastboot case, we'll flip, but if we don't update the pipesrc and
- * pfit state, we'll end up with a big fb scanned out into the wrong
- * sized surface.
- */
-
- I915_WRITE(PIPESRC(crtc->pipe),
- ((new_crtc_state->pipe_src_w - 1) << 16) |
- (new_crtc_state->pipe_src_h - 1));
-
- /* on skylake this is done by detaching scalers */
- if (INTEL_GEN(dev_priv) >= 9) {
- skl_detach_scalers(new_crtc_state);
-
- if (new_crtc_state->pch_pfit.enabled)
- skylake_pfit_enable(new_crtc_state);
- } else if (HAS_PCH_SPLIT(dev_priv)) {
- if (new_crtc_state->pch_pfit.enabled)
- ironlake_pfit_enable(new_crtc_state);
- else if (old_crtc_state->pch_pfit.enabled)
- ironlake_pfit_disable(old_crtc_state);
- }
-
- if (INTEL_GEN(dev_priv) >= 11)
- icl_set_pipe_chicken(crtc);
-}
-
static void intel_fdi_normal_train(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -13715,13 +13674,95 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
return crtc->base.funcs->get_vblank_counter(&crtc->base);
}
+void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (!IS_GEN(dev_priv, 2))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
+
+ if (crtc_state->has_pch_encoder) {
+ enum pipe pch_transcoder =
+ intel_crtc_pch_transcoder(crtc);
+
+ intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
+ }
+}
+
+static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
+ crtc->base.mode = new_crtc_state->base.mode;
+
+ /*
+ * Update pipe size and adjust fitter if needed: the reason for this is
+ * that in compute_mode_changes we check the native mode (not the pfit
+ * mode) to see if we can flip rather than do a full mode set. In the
+ * fastboot case, we'll flip, but if we don't update the pipesrc and
+ * pfit state, we'll end up with a big fb scanned out into the wrong
+ * sized surface.
+ */
+ intel_set_pipe_src_size(new_crtc_state);
+
+ /* on skylake this is done by detaching scalers */
+ if (INTEL_GEN(dev_priv) >= 9) {
+ skl_detach_scalers(new_crtc_state);
+
+ if (new_crtc_state->pch_pfit.enabled)
+ skylake_pfit_enable(new_crtc_state);
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
+ if (new_crtc_state->pch_pfit.enabled)
+ ironlake_pfit_enable(new_crtc_state);
+ else if (old_crtc_state->pch_pfit.enabled)
+ ironlake_pfit_disable(old_crtc_state);
+ }
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_set_pipe_chicken(crtc);
+}
+
+static void commit_pipe_config(struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ bool modeset = needs_modeset(new_crtc_state);
+
+ /*
+ * During modesets pipe configuration was programmed as the
+ * CRTC was enabled.
+ */
+ if (!modeset) {
+ if (new_crtc_state->base.color_mgmt_changed ||
+ new_crtc_state->update_pipe)
+ intel_color_commit(new_crtc_state);
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ skl_detach_scalers(new_crtc_state);
+
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
+
+ if (new_crtc_state->update_pipe)
+ intel_pipe_fastset(old_crtc_state, new_crtc_state);
+ }
+
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state,
+ new_crtc_state);
+}
+
static void intel_update_crtc(struct intel_crtc *crtc,
struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- struct drm_device *dev = state->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state,
@@ -13745,14 +13786,27 @@ static void intel_update_crtc(struct intel_crtc *crtc,
else if (new_plane_state)
intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
- intel_begin_crtc_commit(state, crtc);
+ /* Perform vblank evasion around commit operation */
+ intel_pipe_update_start(new_crtc_state);
+
+ commit_pipe_config(state, old_crtc_state, new_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
- intel_finish_crtc_commit(state, crtc);
+ intel_pipe_update_end(new_crtc_state);
+
+ /*
+ * We usually enable FIFO underrun interrupts as part of the
+ * CRTC enable sequence during modesets. But when we inherit a
+ * valid pipe configuration from the BIOS we need to take care
+ * of enabling them on the CRTC's first fastset.
+ */
+ if (new_crtc_state->update_pipe && !modeset &&
+ old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
+ intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
@@ -14553,72 +14607,6 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
return max_scale;
}
-static void intel_begin_crtc_commit(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
- struct intel_crtc_state *new_crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- bool modeset = needs_modeset(new_crtc_state);
-
- /* Perform vblank evasion around commit operation */
- intel_pipe_update_start(new_crtc_state);
-
- if (modeset)
- goto out;
-
- if (new_crtc_state->base.color_mgmt_changed ||
- new_crtc_state->update_pipe)
- intel_color_commit(new_crtc_state);
-
- if (new_crtc_state->update_pipe)
- intel_update_pipe_config(old_crtc_state, new_crtc_state);
- else if (INTEL_GEN(dev_priv) >= 9)
- skl_detach_scalers(new_crtc_state);
-
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
-
-out:
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state,
- new_crtc_state);
-}
-
-void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
- if (!IS_GEN(dev_priv, 2))
- intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
-
- if (crtc_state->has_pch_encoder) {
- enum pipe pch_transcoder =
- intel_crtc_pch_transcoder(crtc);
-
- intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
- }
-}
-
-static void intel_finish_crtc_commit(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
- struct intel_crtc_state *new_crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
-
- intel_pipe_update_end(new_crtc_state);
-
- if (new_crtc_state->update_pipe &&
- !needs_modeset(new_crtc_state) &&
- old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
- intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
-}
-
/**
* intel_plane_destroy - destroy a plane
* @plane: plane to destroy
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 06/24] drm/i915: Remove begin/finish_crtc_commit, v4.
2019-10-04 11:34 ` [PATCH 06/24] drm/i915: Remove begin/finish_crtc_commit, v4 Maarten Lankhorst
@ 2019-10-07 19:43 ` Matt Roper
0 siblings, 0 replies; 60+ messages in thread
From: Matt Roper @ 2019-10-07 19:43 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:56PM +0200, Maarten Lankhorst wrote:
> This can all be done from the intel_update_crtc function. Split out the
> pipe update into a separate function, just like is done for the planes.
> Pull in all the changes done during fastset as well. It makes no sense
> for it to still exist as a separate function.
>
> Changes since v1:
> - Inline intel_update_pipe_config()
> Changes since v2:
> - Add comments suggested by matt.
> - Reorder commit_pipe_config() to remove all nesting. (Ville, Matt)
> - Use intel_set_pipe_src_size((). (Matt)
> Changes since v3:
> - Move atomic_update_watermarks closer to the plane calls.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 210 +++++++++----------
> 1 file changed, 99 insertions(+), 111 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b5ed097d6a59..ecb15420b5ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -135,8 +135,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> static void chv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> -static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
> -static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
> static void intel_crtc_init_scalers(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
> @@ -4408,45 +4406,6 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
> -static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> - const struct intel_crtc_state *new_crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
> - /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> - crtc->base.mode = new_crtc_state->base.mode;
> -
> - /*
> - * Update pipe size and adjust fitter if needed: the reason for this is
> - * that in compute_mode_changes we check the native mode (not the pfit
> - * mode) to see if we can flip rather than do a full mode set. In the
> - * fastboot case, we'll flip, but if we don't update the pipesrc and
> - * pfit state, we'll end up with a big fb scanned out into the wrong
> - * sized surface.
> - */
> -
> - I915_WRITE(PIPESRC(crtc->pipe),
> - ((new_crtc_state->pipe_src_w - 1) << 16) |
> - (new_crtc_state->pipe_src_h - 1));
> -
> - /* on skylake this is done by detaching scalers */
> - if (INTEL_GEN(dev_priv) >= 9) {
> - skl_detach_scalers(new_crtc_state);
> -
> - if (new_crtc_state->pch_pfit.enabled)
> - skylake_pfit_enable(new_crtc_state);
> - } else if (HAS_PCH_SPLIT(dev_priv)) {
> - if (new_crtc_state->pch_pfit.enabled)
> - ironlake_pfit_enable(new_crtc_state);
> - else if (old_crtc_state->pch_pfit.enabled)
> - ironlake_pfit_disable(old_crtc_state);
> - }
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - icl_set_pipe_chicken(crtc);
> -}
> -
> static void intel_fdi_normal_train(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -13715,13 +13674,95 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> return crtc->base.funcs->get_vblank_counter(&crtc->base);
> }
>
> +void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + if (!IS_GEN(dev_priv, 2))
> + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
> +
> + if (crtc_state->has_pch_encoder) {
> + enum pipe pch_transcoder =
> + intel_crtc_pch_transcoder(crtc);
> +
> + intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
> + }
> +}
> +
> +static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> + crtc->base.mode = new_crtc_state->base.mode;
> +
> + /*
> + * Update pipe size and adjust fitter if needed: the reason for this is
> + * that in compute_mode_changes we check the native mode (not the pfit
> + * mode) to see if we can flip rather than do a full mode set. In the
> + * fastboot case, we'll flip, but if we don't update the pipesrc and
> + * pfit state, we'll end up with a big fb scanned out into the wrong
> + * sized surface.
> + */
> + intel_set_pipe_src_size(new_crtc_state);
> +
> + /* on skylake this is done by detaching scalers */
> + if (INTEL_GEN(dev_priv) >= 9) {
> + skl_detach_scalers(new_crtc_state);
> +
> + if (new_crtc_state->pch_pfit.enabled)
> + skylake_pfit_enable(new_crtc_state);
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> + if (new_crtc_state->pch_pfit.enabled)
> + ironlake_pfit_enable(new_crtc_state);
> + else if (old_crtc_state->pch_pfit.enabled)
> + ironlake_pfit_disable(old_crtc_state);
> + }
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_set_pipe_chicken(crtc);
> +}
> +
> +static void commit_pipe_config(struct intel_atomic_state *state,
> + struct intel_crtc_state *old_crtc_state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + bool modeset = needs_modeset(new_crtc_state);
> +
> + /*
> + * During modesets pipe configuration was programmed as the
> + * CRTC was enabled.
> + */
> + if (!modeset) {
> + if (new_crtc_state->base.color_mgmt_changed ||
> + new_crtc_state->update_pipe)
> + intel_color_commit(new_crtc_state);
> +
> + if (INTEL_GEN(dev_priv) >= 9)
> + skl_detach_scalers(new_crtc_state);
> +
> + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> + bdw_set_pipemisc(new_crtc_state);
> +
> + if (new_crtc_state->update_pipe)
> + intel_pipe_fastset(old_crtc_state, new_crtc_state);
> + }
> +
> + if (dev_priv->display.atomic_update_watermarks)
> + dev_priv->display.atomic_update_watermarks(state,
> + new_crtc_state);
> +}
> +
> static void intel_update_crtc(struct intel_crtc *crtc,
> struct intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> - struct drm_device *dev = state->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> bool modeset = needs_modeset(new_crtc_state);
> struct intel_plane_state *new_plane_state =
> intel_atomic_get_new_plane_state(state,
> @@ -13745,14 +13786,27 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> else if (new_plane_state)
> intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
>
> - intel_begin_crtc_commit(state, crtc);
> + /* Perform vblank evasion around commit operation */
> + intel_pipe_update_start(new_crtc_state);
> +
> + commit_pipe_config(state, old_crtc_state, new_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9)
> skl_update_planes_on_crtc(state, crtc);
> else
> i9xx_update_planes_on_crtc(state, crtc);
>
> - intel_finish_crtc_commit(state, crtc);
> + intel_pipe_update_end(new_crtc_state);
> +
> + /*
> + * We usually enable FIFO underrun interrupts as part of the
> + * CRTC enable sequence during modesets. But when we inherit a
> + * valid pipe configuration from the BIOS we need to take care
> + * of enabling them on the CRTC's first fastset.
> + */
> + if (new_crtc_state->update_pipe && !modeset &&
> + old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> + intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> }
>
> static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> @@ -14553,72 +14607,6 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
> return max_scale;
> }
>
> -static void intel_begin_crtc_commit(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_crtc_state *old_crtc_state =
> - intel_atomic_get_old_crtc_state(state, crtc);
> - struct intel_crtc_state *new_crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> - bool modeset = needs_modeset(new_crtc_state);
> -
> - /* Perform vblank evasion around commit operation */
> - intel_pipe_update_start(new_crtc_state);
> -
> - if (modeset)
> - goto out;
> -
> - if (new_crtc_state->base.color_mgmt_changed ||
> - new_crtc_state->update_pipe)
> - intel_color_commit(new_crtc_state);
> -
> - if (new_crtc_state->update_pipe)
> - intel_update_pipe_config(old_crtc_state, new_crtc_state);
> - else if (INTEL_GEN(dev_priv) >= 9)
> - skl_detach_scalers(new_crtc_state);
> -
> - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> - bdw_set_pipemisc(new_crtc_state);
> -
> -out:
> - if (dev_priv->display.atomic_update_watermarks)
> - dev_priv->display.atomic_update_watermarks(state,
> - new_crtc_state);
> -}
> -
> -void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> - struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
> - if (!IS_GEN(dev_priv, 2))
> - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
> -
> - if (crtc_state->has_pch_encoder) {
> - enum pipe pch_transcoder =
> - intel_crtc_pch_transcoder(crtc);
> -
> - intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
> - }
> -}
> -
> -static void intel_finish_crtc_commit(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> -{
> - struct intel_crtc_state *old_crtc_state =
> - intel_atomic_get_old_crtc_state(state, crtc);
> - struct intel_crtc_state *new_crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> -
> - intel_pipe_update_end(new_crtc_state);
> -
> - if (new_crtc_state->update_pipe &&
> - !needs_modeset(new_crtc_state) &&
> - old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> - intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> -}
> -
> /**
> * intel_plane_destroy - destroy a plane
> * @plane: plane to destroy
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (5 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 06/24] drm/i915: Remove begin/finish_crtc_commit, v4 Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-08 17:03 ` Ville Syrjälä
2019-10-04 11:34 ` [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state Maarten Lankhorst
` (19 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and planar YUV support having
extra planes outside of the core's view that wouldn't be added otherwise.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 41 +++++++++----------
.../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++++---
drivers/gpu/drm/i915/display/intel_color.c | 7 ++--
.../drm/i915/display/intel_display_types.h | 6 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ++++---
6 files changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..e6cb85d41c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_plane *plane = NULL;
- struct intel_plane *intel_plane;
- struct intel_plane_state *plane_state = NULL;
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
struct drm_atomic_state *drm_state = crtc_state->base.state;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
+ struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
int num_scalers_need;
int i;
@@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
/* walkthrough scaler_users bits and start assigning scalers */
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+ struct intel_plane_state *plane_state = NULL;
int *scaler_id;
const char *name;
int idx;
@@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
/* panel fitter case: assign as a crtc scaler */
scaler_id = &scaler_state->scaler_id;
} else {
- name = "PLANE";
+ struct intel_plane *plane;
/* plane scaler case: assign as a plane scaler */
/* find the plane that set the bit as scaler_user */
- plane = drm_state->planes[i].ptr;
/*
* to enable/disable hq mode, add planes that are using scaler
* into this transaction
*/
- if (!plane) {
- struct drm_plane_state *state;
-
+ if (!drm_state->planes[i].ptr) {
/*
* GLK+ scalers don't have a HQ mode so it
* isn't necessary to change between HQ and dyn mode
@@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
continue;
- plane = drm_plane_from_index(&dev_priv->drm, i);
- state = drm_atomic_get_plane_state(drm_state, plane);
- if (IS_ERR(state)) {
- DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
- plane->base.id);
- return PTR_ERR(state);
+ plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
+ plane_state =
+ intel_atomic_get_plane_state_after_check(state,
+ crtc_state,
+ plane);
+ if (IS_ERR(plane_state)) {
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
+ plane->base.base.id, PTR_ERR(plane_state));
+ return PTR_ERR(plane_state);
}
+ } else {
+ plane = to_intel_plane(drm_state->planes[i].ptr);
+ plane_state = intel_atomic_get_new_plane_state(state,
+ plane);
}
- intel_plane = to_intel_plane(plane);
- idx = plane->base.id;
-
/* plane on different crtc cannot be a scaler user of this crtc */
- if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
+ if (WARN_ON(plane->pipe != intel_crtc->pipe))
continue;
- plane_state = intel_atomic_get_new_plane_state(intel_state,
- intel_plane);
+ name = "PLANE";
+ idx = plane->base.base.id;
scaler_id = &plane_state->scaler_id;
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 98b7766eaa7a..4eaab0de98bf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -366,6 +366,25 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
}
}
+struct intel_plane_state *
+intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state,
+ struct intel_plane *plane)
+{
+ struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+
+ if (plane_state)
+ return plane_state;
+
+ plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return plane_state;
+
+ new_crtc_state->update_planes |= BIT(plane->id);
+ return plane_state;
+}
+
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 43564295b864..42bd02638d32 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2249,6 +2249,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
*/
for_each_intel_crtc(&dev_priv->drm, crtc) {
struct intel_crtc_state *crtc_state;
+ struct intel_plane *plane;
int ret;
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
@@ -2266,12 +2267,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
if (ret)
return ret;
- ret = drm_atomic_add_affected_planes(&state->base,
- &crtc->base);
- if (ret)
- return ret;
-
- crtc_state->update_planes |= crtc_state->active_planes;
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ struct intel_plane_state *plane_state =
+ intel_atomic_get_plane_state_after_check(state,
+ crtc_state,
+ plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 9ab34902663e..1e3a623eaf82 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
if (!need_plane_update(plane, new_crtc_state))
continue;
- plane_state = intel_atomic_get_plane_state(state, plane);
+ plane_state =
+ intel_atomic_get_plane_state_after_check(state,
+ new_crtc_state,
+ plane);
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
-
- new_crtc_state->update_planes |= BIT(plane->id);
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 976669f01a8c..526423437f63 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1541,4 +1541,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+/* intel_atomic_plane.c */
+struct intel_plane_state *
+intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane);
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53358e33df1b..5e6e54cb22fe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5242,11 +5242,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
continue;
- plane_state = intel_atomic_get_plane_state(state, plane);
+ plane_state =
+ intel_atomic_get_plane_state_after_check(state,
+ new_crtc_state,
+ plane);
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
-
- new_crtc_state->update_planes |= BIT(plane_id);
}
return 0;
@@ -5534,11 +5535,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
&new_crtc_state->wm.skl.optimal.planes[plane_id]))
continue;
- plane_state = intel_atomic_get_plane_state(state, plane);
+ plane_state =
+ intel_atomic_get_plane_state_after_check(state,
+ new_crtc_state,
+ plane);
if (IS_ERR(plane_state))
return PTR_ERR(plane_state);
-
- new_crtc_state->update_planes |= BIT(plane_id);
}
return 0;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
2019-10-04 11:34 ` [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check() Maarten Lankhorst
@ 2019-10-08 17:03 ` Ville Syrjälä
2019-10-10 11:56 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-08 17:03 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> Use this in all the places where we try to acquire planes after the planes
> atomic_check().
>
> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
> but seems like it will be in the future. To add some paranoia, add all planes
> rather than active planes, because of bigjoiner and planar YUV support having
> extra planes outside of the core's view that wouldn't be added otherwise.
If the plane isn't active what good does adding it do?
Maybe the only real exception I can think of is the watermarks
and the primary vs. gamma/csc_enable on pre-skl, but those are
already handled correctly.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +++++++++----------
> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++
> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++++---
> drivers/gpu/drm/i915/display/intel_color.c | 7 ++--
> .../drm/i915/display/intel_display_types.h | 6 +++
> drivers/gpu/drm/i915/intel_pm.c | 14 ++++---
> 6 files changed, 66 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..e6cb85d41c8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_plane *plane = NULL;
> - struct intel_plane *intel_plane;
> - struct intel_plane_state *plane_state = NULL;
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> struct drm_atomic_state *drm_state = crtc_state->base.state;
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> int num_scalers_need;
> int i;
>
> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>
> /* walkthrough scaler_users bits and start assigning scalers */
> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> + struct intel_plane_state *plane_state = NULL;
> int *scaler_id;
> const char *name;
> int idx;
> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> /* panel fitter case: assign as a crtc scaler */
> scaler_id = &scaler_state->scaler_id;
> } else {
> - name = "PLANE";
> + struct intel_plane *plane;
>
> /* plane scaler case: assign as a plane scaler */
> /* find the plane that set the bit as scaler_user */
> - plane = drm_state->planes[i].ptr;
>
> /*
> * to enable/disable hq mode, add planes that are using scaler
> * into this transaction
> */
> - if (!plane) {
> - struct drm_plane_state *state;
> -
> + if (!drm_state->planes[i].ptr) {
> /*
> * GLK+ scalers don't have a HQ mode so it
> * isn't necessary to change between HQ and dyn mode
> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> continue;
>
> - plane = drm_plane_from_index(&dev_priv->drm, i);
> - state = drm_atomic_get_plane_state(drm_state, plane);
> - if (IS_ERR(state)) {
> - DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
> - plane->base.id);
> - return PTR_ERR(state);
> + plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
> + plane_state =
> + intel_atomic_get_plane_state_after_check(state,
> + crtc_state,
> + plane);
> + if (IS_ERR(plane_state)) {
> + DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
> + plane->base.base.id, PTR_ERR(plane_state));
> + return PTR_ERR(plane_state);
> }
> + } else {
> + plane = to_intel_plane(drm_state->planes[i].ptr);
> + plane_state = intel_atomic_get_new_plane_state(state,
> + plane);
> }
>
> - intel_plane = to_intel_plane(plane);
> - idx = plane->base.id;
> -
> /* plane on different crtc cannot be a scaler user of this crtc */
> - if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
> + if (WARN_ON(plane->pipe != intel_crtc->pipe))
> continue;
>
> - plane_state = intel_atomic_get_new_plane_state(intel_state,
> - intel_plane);
> + name = "PLANE";
> + idx = plane->base.base.id;
> scaler_id = &plane_state->scaler_id;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 98b7766eaa7a..4eaab0de98bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -366,6 +366,25 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> }
> }
>
> +struct intel_plane_state *
> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state,
> + struct intel_plane *plane)
> +{
> + struct intel_plane_state *plane_state =
> + intel_atomic_get_new_plane_state(state, plane);
> +
> + if (plane_state)
> + return plane_state;
> +
> + plane_state = intel_atomic_get_plane_state(state, plane);
> + if (IS_ERR(plane_state))
> + return plane_state;
> +
> + new_crtc_state->update_planes |= BIT(plane->id);
I also don't really like burying this all the way down. Seems
rather non-obvious from the caller. Also seems wrong to not set
the flag if the plane was already part of the state.
I'd say we just need to hand roll add_affected_planes() for the
cdclk code. And there is should definitely be sufficient to
add just the active planes.
> + return plane_state;
> +}
> +
> const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> .prepare_fb = intel_prepare_plane_fb,
> .cleanup_fb = intel_cleanup_plane_fb,
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 43564295b864..42bd02638d32 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2249,6 +2249,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> */
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> struct intel_crtc_state *crtc_state;
> + struct intel_plane *plane;
> int ret;
>
> crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> @@ -2266,12 +2267,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - ret = drm_atomic_add_affected_planes(&state->base,
> - &crtc->base);
> - if (ret)
> - return ret;
> -
> - crtc_state->update_planes |= crtc_state->active_planes;
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + struct intel_plane_state *plane_state =
> + intel_atomic_get_plane_state_after_check(state,
> + crtc_state,
> + plane);
> + if (IS_ERR(plane_state))
> + return PTR_ERR(plane_state);
> + }
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 9ab34902663e..1e3a623eaf82 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> if (!need_plane_update(plane, new_crtc_state))
> continue;
>
> - plane_state = intel_atomic_get_plane_state(state, plane);
> + plane_state =
> + intel_atomic_get_plane_state_after_check(state,
> + new_crtc_state,
> + plane);
> if (IS_ERR(plane_state))
> return PTR_ERR(plane_state);
> -
> - new_crtc_state->update_planes |= BIT(plane->id);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 976669f01a8c..526423437f63 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1541,4 +1541,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> return i915_ggtt_offset(state->vma);
> }
>
> +/* intel_atomic_plane.c */
> +struct intel_plane_state *
> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> + struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane);
> +
> #endif /* __INTEL_DISPLAY_TYPES_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 53358e33df1b..5e6e54cb22fe 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5242,11 +5242,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
> continue;
>
> - plane_state = intel_atomic_get_plane_state(state, plane);
> + plane_state =
> + intel_atomic_get_plane_state_after_check(state,
> + new_crtc_state,
> + plane);
> if (IS_ERR(plane_state))
> return PTR_ERR(plane_state);
> -
> - new_crtc_state->update_planes |= BIT(plane_id);
> }
>
> return 0;
> @@ -5534,11 +5535,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
> continue;
>
> - plane_state = intel_atomic_get_plane_state(state, plane);
> + plane_state =
> + intel_atomic_get_plane_state_after_check(state,
> + new_crtc_state,
> + plane);
> if (IS_ERR(plane_state))
> return PTR_ERR(plane_state);
> -
> - new_crtc_state->update_planes |= BIT(plane_id);
> }
>
> return 0;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
2019-10-08 17:03 ` Ville Syrjälä
@ 2019-10-10 11:56 ` Maarten Lankhorst
2019-10-10 12:39 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 11:56 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
>> Use this in all the places where we try to acquire planes after the planes
>> atomic_check().
>>
>> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
>> but seems like it will be in the future. To add some paranoia, add all planes
>> rather than active planes, because of bigjoiner and planar YUV support having
>> extra planes outside of the core's view that wouldn't be added otherwise.
> If the plane isn't active what good does adding it do?
>
> Maybe the only real exception I can think of is the watermarks
> and the primary vs. gamma/csc_enable on pre-skl, but those are
> already handled correctly.
Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
typing up special case support I thought it was easier to just add all
planes. On bigjoiner slave no planes are enabled either, even if they're
active.
>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +++++++++----------
>> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++++---
>> drivers/gpu/drm/i915/display/intel_color.c | 7 ++--
>> .../drm/i915/display/intel_display_types.h | 6 +++
>> drivers/gpu/drm/i915/intel_pm.c | 14 ++++---
>> 6 files changed, 66 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index c5a552a69752..e6cb85d41c8d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>> struct intel_crtc *intel_crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> - struct drm_plane *plane = NULL;
>> - struct intel_plane *intel_plane;
>> - struct intel_plane_state *plane_state = NULL;
>> struct intel_crtc_scaler_state *scaler_state =
>> &crtc_state->scaler_state;
>> struct drm_atomic_state *drm_state = crtc_state->base.state;
>> - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
>> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
>> int num_scalers_need;
>> int i;
>>
>> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>
>> /* walkthrough scaler_users bits and start assigning scalers */
>> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>> + struct intel_plane_state *plane_state = NULL;
>> int *scaler_id;
>> const char *name;
>> int idx;
>> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>> /* panel fitter case: assign as a crtc scaler */
>> scaler_id = &scaler_state->scaler_id;
>> } else {
>> - name = "PLANE";
>> + struct intel_plane *plane;
>>
>> /* plane scaler case: assign as a plane scaler */
>> /* find the plane that set the bit as scaler_user */
>> - plane = drm_state->planes[i].ptr;
>>
>> /*
>> * to enable/disable hq mode, add planes that are using scaler
>> * into this transaction
>> */
>> - if (!plane) {
>> - struct drm_plane_state *state;
>> -
>> + if (!drm_state->planes[i].ptr) {
>> /*
>> * GLK+ scalers don't have a HQ mode so it
>> * isn't necessary to change between HQ and dyn mode
>> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> continue;
>>
>> - plane = drm_plane_from_index(&dev_priv->drm, i);
>> - state = drm_atomic_get_plane_state(drm_state, plane);
>> - if (IS_ERR(state)) {
>> - DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
>> - plane->base.id);
>> - return PTR_ERR(state);
>> + plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
>> + plane_state =
>> + intel_atomic_get_plane_state_after_check(state,
>> + crtc_state,
>> + plane);
>> + if (IS_ERR(plane_state)) {
>> + DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
>> + plane->base.base.id, PTR_ERR(plane_state));
>> + return PTR_ERR(plane_state);
>> }
>> + } else {
>> + plane = to_intel_plane(drm_state->planes[i].ptr);
>> + plane_state = intel_atomic_get_new_plane_state(state,
>> + plane);
>> }
>>
>> - intel_plane = to_intel_plane(plane);
>> - idx = plane->base.id;
>> -
>> /* plane on different crtc cannot be a scaler user of this crtc */
>> - if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
>> + if (WARN_ON(plane->pipe != intel_crtc->pipe))
>> continue;
>>
>> - plane_state = intel_atomic_get_new_plane_state(intel_state,
>> - intel_plane);
>> + name = "PLANE";
>> + idx = plane->base.base.id;
>> scaler_id = &plane_state->scaler_id;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 98b7766eaa7a..4eaab0de98bf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -366,6 +366,25 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
>> }
>> }
>>
>> +struct intel_plane_state *
>> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>> + struct intel_crtc_state *new_crtc_state,
>> + struct intel_plane *plane)
>> +{
>> + struct intel_plane_state *plane_state =
>> + intel_atomic_get_new_plane_state(state, plane);
>> +
>> + if (plane_state)
>> + return plane_state;
>> +
>> + plane_state = intel_atomic_get_plane_state(state, plane);
>> + if (IS_ERR(plane_state))
>> + return plane_state;
>> +
>> + new_crtc_state->update_planes |= BIT(plane->id);
> I also don't really like burying this all the way down. Seems
> rather non-obvious from the caller. Also seems wrong to not set
> the flag if the plane was already part of the state.
>
> I'd say we just need to hand roll add_affected_planes() for the
> cdclk code. And there is should definitely be sufficient to
> add just the active planes.
>
>> + return plane_state;
>> +}
>> +
>> const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
>> .prepare_fb = intel_prepare_plane_fb,
>> .cleanup_fb = intel_cleanup_plane_fb,
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 43564295b864..42bd02638d32 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2249,6 +2249,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>> */
>> for_each_intel_crtc(&dev_priv->drm, crtc) {
>> struct intel_crtc_state *crtc_state;
>> + struct intel_plane *plane;
>> int ret;
>>
>> crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
>> @@ -2266,12 +2267,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>> if (ret)
>> return ret;
>>
>> - ret = drm_atomic_add_affected_planes(&state->base,
>> - &crtc->base);
>> - if (ret)
>> - return ret;
>> -
>> - crtc_state->update_planes |= crtc_state->active_planes;
>> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>> + struct intel_plane_state *plane_state =
>> + intel_atomic_get_plane_state_after_check(state,
>> + crtc_state,
>> + plane);
>> + if (IS_ERR(plane_state))
>> + return PTR_ERR(plane_state);
>> + }
>> }
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>> index 9ab34902663e..1e3a623eaf82 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>> if (!need_plane_update(plane, new_crtc_state))
>> continue;
>>
>> - plane_state = intel_atomic_get_plane_state(state, plane);
>> + plane_state =
>> + intel_atomic_get_plane_state_after_check(state,
>> + new_crtc_state,
>> + plane);
>> if (IS_ERR(plane_state))
>> return PTR_ERR(plane_state);
>> -
>> - new_crtc_state->update_planes |= BIT(plane->id);
>> }
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 976669f01a8c..526423437f63 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1541,4 +1541,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
>> return i915_ggtt_offset(state->vma);
>> }
>>
>> +/* intel_atomic_plane.c */
>> +struct intel_plane_state *
>> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>> + struct intel_crtc_state *crtc_state,
>> + struct intel_plane *plane);
>> +
>> #endif /* __INTEL_DISPLAY_TYPES_H__ */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 53358e33df1b..5e6e54cb22fe 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -5242,11 +5242,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
>> &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
>> continue;
>>
>> - plane_state = intel_atomic_get_plane_state(state, plane);
>> + plane_state =
>> + intel_atomic_get_plane_state_after_check(state,
>> + new_crtc_state,
>> + plane);
>> if (IS_ERR(plane_state))
>> return PTR_ERR(plane_state);
>> -
>> - new_crtc_state->update_planes |= BIT(plane_id);
>> }
>>
>> return 0;
>> @@ -5534,11 +5535,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
>> continue;
>>
>> - plane_state = intel_atomic_get_plane_state(state, plane);
>> + plane_state =
>> + intel_atomic_get_plane_state_after_check(state,
>> + new_crtc_state,
>> + plane);
>> if (IS_ERR(plane_state))
>> return PTR_ERR(plane_state);
>> -
>> - new_crtc_state->update_planes |= BIT(plane_id);
>> }
>>
>> return 0;
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
2019-10-10 11:56 ` Maarten Lankhorst
@ 2019-10-10 12:39 ` Ville Syrjälä
2019-10-10 13:01 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-10 12:39 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> >> Use this in all the places where we try to acquire planes after the planes
> >> atomic_check().
> >>
> >> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
> >> but seems like it will be in the future. To add some paranoia, add all planes
> >> rather than active planes, because of bigjoiner and planar YUV support having
> >> extra planes outside of the core's view that wouldn't be added otherwise.
> > If the plane isn't active what good does adding it do?
> >
> > Maybe the only real exception I can think of is the watermarks
> > and the primary vs. gamma/csc_enable on pre-skl, but those are
> > already handled correctly.
>
> Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
> typing up special case support I thought it was easier to just add all
> planes. On bigjoiner slave no planes are enabled either, even if they're
> active.
I think once we have the state split we should get rid of all the
special casing of the Y planes. Then they (and the bigjoiner slave
planes) should just look like an active planes which is not
logically enabled by uapi.
>
> >
> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +++++++++----------
> >> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++
> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++++---
> >> drivers/gpu/drm/i915/display/intel_color.c | 7 ++--
> >> .../drm/i915/display/intel_display_types.h | 6 +++
> >> drivers/gpu/drm/i915/intel_pm.c | 14 ++++---
> >> 6 files changed, 66 insertions(+), 36 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> index c5a552a69752..e6cb85d41c8d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> >> struct intel_crtc *intel_crtc,
> >> struct intel_crtc_state *crtc_state)
> >> {
> >> - struct drm_plane *plane = NULL;
> >> - struct intel_plane *intel_plane;
> >> - struct intel_plane_state *plane_state = NULL;
> >> struct intel_crtc_scaler_state *scaler_state =
> >> &crtc_state->scaler_state;
> >> struct drm_atomic_state *drm_state = crtc_state->base.state;
> >> - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
> >> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> >> int num_scalers_need;
> >> int i;
> >>
> >> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> >>
> >> /* walkthrough scaler_users bits and start assigning scalers */
> >> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> >> + struct intel_plane_state *plane_state = NULL;
> >> int *scaler_id;
> >> const char *name;
> >> int idx;
> >> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> >> /* panel fitter case: assign as a crtc scaler */
> >> scaler_id = &scaler_state->scaler_id;
> >> } else {
> >> - name = "PLANE";
> >> + struct intel_plane *plane;
> >>
> >> /* plane scaler case: assign as a plane scaler */
> >> /* find the plane that set the bit as scaler_user */
> >> - plane = drm_state->planes[i].ptr;
> >>
> >> /*
> >> * to enable/disable hq mode, add planes that are using scaler
> >> * into this transaction
> >> */
> >> - if (!plane) {
> >> - struct drm_plane_state *state;
> >> -
> >> + if (!drm_state->planes[i].ptr) {
> >> /*
> >> * GLK+ scalers don't have a HQ mode so it
> >> * isn't necessary to change between HQ and dyn mode
> >> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> >> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> >> continue;
> >>
> >> - plane = drm_plane_from_index(&dev_priv->drm, i);
> >> - state = drm_atomic_get_plane_state(drm_state, plane);
> >> - if (IS_ERR(state)) {
> >> - DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
> >> - plane->base.id);
> >> - return PTR_ERR(state);
> >> + plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
> >> + plane_state =
> >> + intel_atomic_get_plane_state_after_check(state,
> >> + crtc_state,
> >> + plane);
> >> + if (IS_ERR(plane_state)) {
> >> + DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
> >> + plane->base.base.id, PTR_ERR(plane_state));
> >> + return PTR_ERR(plane_state);
> >> }
> >> + } else {
> >> + plane = to_intel_plane(drm_state->planes[i].ptr);
> >> + plane_state = intel_atomic_get_new_plane_state(state,
> >> + plane);
> >> }
> >>
> >> - intel_plane = to_intel_plane(plane);
> >> - idx = plane->base.id;
> >> -
> >> /* plane on different crtc cannot be a scaler user of this crtc */
> >> - if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
> >> + if (WARN_ON(plane->pipe != intel_crtc->pipe))
> >> continue;
> >>
> >> - plane_state = intel_atomic_get_new_plane_state(intel_state,
> >> - intel_plane);
> >> + name = "PLANE";
> >> + idx = plane->base.base.id;
> >> scaler_id = &plane_state->scaler_id;
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> index 98b7766eaa7a..4eaab0de98bf 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> @@ -366,6 +366,25 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
> >> }
> >> }
> >>
> >> +struct intel_plane_state *
> >> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> >> + struct intel_crtc_state *new_crtc_state,
> >> + struct intel_plane *plane)
> >> +{
> >> + struct intel_plane_state *plane_state =
> >> + intel_atomic_get_new_plane_state(state, plane);
> >> +
> >> + if (plane_state)
> >> + return plane_state;
> >> +
> >> + plane_state = intel_atomic_get_plane_state(state, plane);
> >> + if (IS_ERR(plane_state))
> >> + return plane_state;
> >> +
> >> + new_crtc_state->update_planes |= BIT(plane->id);
> > I also don't really like burying this all the way down. Seems
> > rather non-obvious from the caller. Also seems wrong to not set
> > the flag if the plane was already part of the state.
> >
> > I'd say we just need to hand roll add_affected_planes() for the
> > cdclk code. And there is should definitely be sufficient to
> > add just the active planes.
> >
> >> + return plane_state;
> >> +}
> >> +
> >> const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> >> .prepare_fb = intel_prepare_plane_fb,
> >> .cleanup_fb = intel_cleanup_plane_fb,
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 43564295b864..42bd02638d32 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -2249,6 +2249,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> >> */
> >> for_each_intel_crtc(&dev_priv->drm, crtc) {
> >> struct intel_crtc_state *crtc_state;
> >> + struct intel_plane *plane;
> >> int ret;
> >>
> >> crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> >> @@ -2266,12 +2267,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> >> if (ret)
> >> return ret;
> >>
> >> - ret = drm_atomic_add_affected_planes(&state->base,
> >> - &crtc->base);
> >> - if (ret)
> >> - return ret;
> >> -
> >> - crtc_state->update_planes |= crtc_state->active_planes;
> >> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> >> + struct intel_plane_state *plane_state =
> >> + intel_atomic_get_plane_state_after_check(state,
> >> + crtc_state,
> >> + plane);
> >> + if (IS_ERR(plane_state))
> >> + return PTR_ERR(plane_state);
> >> + }
> >> }
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> >> index 9ab34902663e..1e3a623eaf82 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> >> @@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> >> if (!need_plane_update(plane, new_crtc_state))
> >> continue;
> >>
> >> - plane_state = intel_atomic_get_plane_state(state, plane);
> >> + plane_state =
> >> + intel_atomic_get_plane_state_after_check(state,
> >> + new_crtc_state,
> >> + plane);
> >> if (IS_ERR(plane_state))
> >> return PTR_ERR(plane_state);
> >> -
> >> - new_crtc_state->update_planes |= BIT(plane->id);
> >> }
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 976669f01a8c..526423437f63 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1541,4 +1541,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> >> return i915_ggtt_offset(state->vma);
> >> }
> >>
> >> +/* intel_atomic_plane.c */
> >> +struct intel_plane_state *
> >> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> >> + struct intel_crtc_state *crtc_state,
> >> + struct intel_plane *plane);
> >> +
> >> #endif /* __INTEL_DISPLAY_TYPES_H__ */
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index 53358e33df1b..5e6e54cb22fe 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -5242,11 +5242,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> >> &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
> >> continue;
> >>
> >> - plane_state = intel_atomic_get_plane_state(state, plane);
> >> + plane_state =
> >> + intel_atomic_get_plane_state_after_check(state,
> >> + new_crtc_state,
> >> + plane);
> >> if (IS_ERR(plane_state))
> >> return PTR_ERR(plane_state);
> >> -
> >> - new_crtc_state->update_planes |= BIT(plane_id);
> >> }
> >>
> >> return 0;
> >> @@ -5534,11 +5535,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> >> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
> >> continue;
> >>
> >> - plane_state = intel_atomic_get_plane_state(state, plane);
> >> + plane_state =
> >> + intel_atomic_get_plane_state_after_check(state,
> >> + new_crtc_state,
> >> + plane);
> >> if (IS_ERR(plane_state))
> >> return PTR_ERR(plane_state);
> >> -
> >> - new_crtc_state->update_planes |= BIT(plane_id);
> >> }
> >>
> >> return 0;
> >> --
> >> 2.23.0
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
2019-10-10 12:39 ` Ville Syrjälä
@ 2019-10-10 13:01 ` Maarten Lankhorst
0 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 13:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 10-10-2019 om 14:39 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
>>>> Use this in all the places where we try to acquire planes after the planes
>>>> atomic_check().
>>>>
>>>> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
>>>> but seems like it will be in the future. To add some paranoia, add all planes
>>>> rather than active planes, because of bigjoiner and planar YUV support having
>>>> extra planes outside of the core's view that wouldn't be added otherwise.
>>> If the plane isn't active what good does adding it do?
>>>
>>> Maybe the only real exception I can think of is the watermarks
>>> and the primary vs. gamma/csc_enable on pre-skl, but those are
>>> already handled correctly.
>> Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
>> typing up special case support I thought it was easier to just add all
>> planes. On bigjoiner slave no planes are enabled either, even if they're
>> active.
> I think once we have the state split we should get rid of all the
> special casing of the Y planes. Then they (and the bigjoiner slave
> planes) should just look like an active planes which is not
> logically enabled by uapi.
With the plane split it's doable, even for watermarks, but prefer to do it later on, not change the world too much. :)
There is no issue in the core with adding planes that are disabled, so I don't see the problem?
~Maarten
>>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +++++++++----------
>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +++++++++
>>>> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 ++++---
>>>> drivers/gpu/drm/i915/display/intel_color.c | 7 ++--
>>>> .../drm/i915/display/intel_display_types.h | 6 +++
>>>> drivers/gpu/drm/i915/intel_pm.c | 14 ++++---
>>>> 6 files changed, 66 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
>>>> index c5a552a69752..e6cb85d41c8d 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>>>> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>>> struct intel_crtc *intel_crtc,
>>>> struct intel_crtc_state *crtc_state)
>>>> {
>>>> - struct drm_plane *plane = NULL;
>>>> - struct intel_plane *intel_plane;
>>>> - struct intel_plane_state *plane_state = NULL;
>>>> struct intel_crtc_scaler_state *scaler_state =
>>>> &crtc_state->scaler_state;
>>>> struct drm_atomic_state *drm_state = crtc_state->base.state;
>>>> - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
>>>> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
>>>> int num_scalers_need;
>>>> int i;
>>>>
>>>> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>>>
>>>> /* walkthrough scaler_users bits and start assigning scalers */
>>>> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>>>> + struct intel_plane_state *plane_state = NULL;
>>>> int *scaler_id;
>>>> const char *name;
>>>> int idx;
>>>> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>>> /* panel fitter case: assign as a crtc scaler */
>>>> scaler_id = &scaler_state->scaler_id;
>>>> } else {
>>>> - name = "PLANE";
>>>> + struct intel_plane *plane;
>>>>
>>>> /* plane scaler case: assign as a plane scaler */
>>>> /* find the plane that set the bit as scaler_user */
>>>> - plane = drm_state->planes[i].ptr;
>>>>
>>>> /*
>>>> * to enable/disable hq mode, add planes that are using scaler
>>>> * into this transaction
>>>> */
>>>> - if (!plane) {
>>>> - struct drm_plane_state *state;
>>>> -
>>>> + if (!drm_state->planes[i].ptr) {
>>>> /*
>>>> * GLK+ scalers don't have a HQ mode so it
>>>> * isn't necessary to change between HQ and dyn mode
>>>> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>>> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>>>> continue;
>>>>
>>>> - plane = drm_plane_from_index(&dev_priv->drm, i);
>>>> - state = drm_atomic_get_plane_state(drm_state, plane);
>>>> - if (IS_ERR(state)) {
>>>> - DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
>>>> - plane->base.id);
>>>> - return PTR_ERR(state);
>>>> + plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
>>>> + plane_state =
>>>> + intel_atomic_get_plane_state_after_check(state,
>>>> + crtc_state,
>>>> + plane);
>>>> + if (IS_ERR(plane_state)) {
>>>> + DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
>>>> + plane->base.base.id, PTR_ERR(plane_state));
>>>> + return PTR_ERR(plane_state);
>>>> }
>>>> + } else {
>>>> + plane = to_intel_plane(drm_state->planes[i].ptr);
>>>> + plane_state = intel_atomic_get_new_plane_state(state,
>>>> + plane);
>>>> }
>>>>
>>>> - intel_plane = to_intel_plane(plane);
>>>> - idx = plane->base.id;
>>>> -
>>>> /* plane on different crtc cannot be a scaler user of this crtc */
>>>> - if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
>>>> + if (WARN_ON(plane->pipe != intel_crtc->pipe))
>>>> continue;
>>>>
>>>> - plane_state = intel_atomic_get_new_plane_state(intel_state,
>>>> - intel_plane);
>>>> + name = "PLANE";
>>>> + idx = plane->base.base.id;
>>>> scaler_id = &plane_state->scaler_id;
>>>> }
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> index 98b7766eaa7a..4eaab0de98bf 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> @@ -366,6 +366,25 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
>>>> }
>>>> }
>>>>
>>>> +struct intel_plane_state *
>>>> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>>>> + struct intel_crtc_state *new_crtc_state,
>>>> + struct intel_plane *plane)
>>>> +{
>>>> + struct intel_plane_state *plane_state =
>>>> + intel_atomic_get_new_plane_state(state, plane);
>>>> +
>>>> + if (plane_state)
>>>> + return plane_state;
>>>> +
>>>> + plane_state = intel_atomic_get_plane_state(state, plane);
>>>> + if (IS_ERR(plane_state))
>>>> + return plane_state;
>>>> +
>>>> + new_crtc_state->update_planes |= BIT(plane->id);
>>> I also don't really like burying this all the way down. Seems
>>> rather non-obvious from the caller. Also seems wrong to not set
>>> the flag if the plane was already part of the state.
>>>
>>> I'd say we just need to hand roll add_affected_planes() for the
>>> cdclk code. And there is should definitely be sufficient to
>>> add just the active planes.
>>>
>>>> + return plane_state;
>>>> +}
>>>> +
>>>> const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
>>>> .prepare_fb = intel_prepare_plane_fb,
>>>> .cleanup_fb = intel_cleanup_plane_fb,
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> index 43564295b864..42bd02638d32 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>>> @@ -2249,6 +2249,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>>>> */
>>>> for_each_intel_crtc(&dev_priv->drm, crtc) {
>>>> struct intel_crtc_state *crtc_state;
>>>> + struct intel_plane *plane;
>>>> int ret;
>>>>
>>>> crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
>>>> @@ -2266,12 +2267,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>>>> if (ret)
>>>> return ret;
>>>>
>>>> - ret = drm_atomic_add_affected_planes(&state->base,
>>>> - &crtc->base);
>>>> - if (ret)
>>>> - return ret;
>>>> -
>>>> - crtc_state->update_planes |= crtc_state->active_planes;
>>>> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>>>> + struct intel_plane_state *plane_state =
>>>> + intel_atomic_get_plane_state_after_check(state,
>>>> + crtc_state,
>>>> + plane);
>>>> + if (IS_ERR(plane_state))
>>>> + return PTR_ERR(plane_state);
>>>> + }
>>>> }
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>>>> index 9ab34902663e..1e3a623eaf82 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>>>> @@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>>>> if (!need_plane_update(plane, new_crtc_state))
>>>> continue;
>>>>
>>>> - plane_state = intel_atomic_get_plane_state(state, plane);
>>>> + plane_state =
>>>> + intel_atomic_get_plane_state_after_check(state,
>>>> + new_crtc_state,
>>>> + plane);
>>>> if (IS_ERR(plane_state))
>>>> return PTR_ERR(plane_state);
>>>> -
>>>> - new_crtc_state->update_planes |= BIT(plane->id);
>>>> }
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index 976669f01a8c..526423437f63 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1541,4 +1541,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
>>>> return i915_ggtt_offset(state->vma);
>>>> }
>>>>
>>>> +/* intel_atomic_plane.c */
>>>> +struct intel_plane_state *
>>>> +intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>>>> + struct intel_crtc_state *crtc_state,
>>>> + struct intel_plane *plane);
>>>> +
>>>> #endif /* __INTEL_DISPLAY_TYPES_H__ */
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index 53358e33df1b..5e6e54cb22fe 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -5242,11 +5242,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
>>>> &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
>>>> continue;
>>>>
>>>> - plane_state = intel_atomic_get_plane_state(state, plane);
>>>> + plane_state =
>>>> + intel_atomic_get_plane_state_after_check(state,
>>>> + new_crtc_state,
>>>> + plane);
>>>> if (IS_ERR(plane_state))
>>>> return PTR_ERR(plane_state);
>>>> -
>>>> - new_crtc_state->update_planes |= BIT(plane_id);
>>>> }
>>>>
>>>> return 0;
>>>> @@ -5534,11 +5535,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>>>> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
>>>> continue;
>>>>
>>>> - plane_state = intel_atomic_get_plane_state(state, plane);
>>>> + plane_state =
>>>> + intel_atomic_get_plane_state_after_check(state,
>>>> + new_crtc_state,
>>>> + plane);
>>>> if (IS_ERR(plane_state))
>>>> return PTR_ERR(plane_state);
>>>> -
>>>> - new_crtc_state->update_planes |= BIT(plane_id);
>>>> }
>>>>
>>>> return 0;
>>>> --
>>>> 2.23.0
>>>>
>>>> _______________________________________________
>>>> Intel-gfx mailing list
>>>> Intel-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (6 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check() Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-08 17:06 ` Ville Syrjälä
2019-10-04 11:34 ` [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split Maarten Lankhorst
` (18 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
We want to split drm_crtc_state into the user visible state
and actual hardware state. To prepare for this, we need some
ground rules what should be in each state:
In uapi we use:
- crtc, *_changed flags, event, commit, state, mode_blob,
(plane/connector/encoder)_mask.
In hw state we use what's displayed in hardware:
- enable, active, (adjusted) mode, color property blobs.
clear_intel_crtc_state and hw readout need to be updated for these rules,
which will allow us to enable 2 joined pipes.
Note:
- When making calling atomic_commit() you need to manipulate the uapi
variables, atomic_check() will copy it to hw. This is because you're
just another atomic client. Of course you can still check hw members
at that point to decide if a pipe is active.
- In general you should look at the hw members when available, unless
there's a good reason to do something else.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 18 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 14 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
drivers/gpu/drm/i915/display/intel_audio.c | 12 +-
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
drivers/gpu/drm/i915/display/intel_color.c | 180 +++---
drivers/gpu/drm/i915/display/intel_crt.c | 24 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +-
drivers/gpu/drm/i915/display/intel_display.c | 544 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.h | 6 +-
.../drm/i915/display/intel_display_types.h | 28 +-
drivers/gpu/drm/i915/display/intel_dp.c | 42 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 14 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 14 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 64 +--
drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 12 +-
drivers/gpu/drm/i915/display/intel_panel.c | 14 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 22 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 25 +-
drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 20 +-
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 170 +++---
31 files changed, 700 insertions(+), 665 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..0e24b8e257e5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
u32 dss_ctl2;
u16 hactive = adjusted_mode->crtc_hdisplay;
u16 dl_buffer_depth;
@@ -625,7 +625,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum pipe pipe = intel_crtc->pipe;
u32 tmp;
enum port port;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (intel_dsi->dual_link) {
adjusted_mode->crtc_hdisplay *= 2;
@@ -1242,16 +1242,16 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
- pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
- pipe_config->base.adjusted_mode.crtc_clock *= 2;
+ pipe_config->hw.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1265,11 +1265,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index e6cb85d41c8d..7cf13b9c7d38 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -186,13 +186,14 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
struct drm_crtc_state *
intel_crtc_duplicate_state(struct drm_crtc *crtc)
{
+ const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
struct intel_crtc_state *crtc_state;
- crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
+ crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
if (!crtc_state)
return NULL;
- __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
+ __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
@@ -204,7 +205,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
- return &crtc_state->base;
+ return &crtc_state->uapi;
}
/**
@@ -219,7 +220,10 @@ void
intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
- drm_atomic_helper_crtc_destroy_state(crtc, state);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+
+ __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ kfree(crtc_state);
}
static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
@@ -315,7 +319,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
{
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
- struct drm_atomic_state *drm_state = crtc_state->base.state;
+ struct drm_atomic_state *drm_state = crtc_state->uapi.state;
struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
int num_scalers_need;
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4eaab0de98bf..ca82167d4ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -271,7 +271,7 @@ void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_update_plane(&plane->base, crtc);
plane->update_plane(plane, crtc_state, plane_state);
@@ -281,7 +281,7 @@ void intel_update_slave(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_update_plane(&plane->base, crtc);
plane->update_slave(plane, crtc_state, plane_state);
@@ -290,7 +290,7 @@ void intel_update_slave(struct intel_plane *plane,
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_disable_plane(&plane->base, crtc);
plane->disable_plane(plane, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 54638d99e021..19b2af4b9f81 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
{
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
int i;
for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
@@ -554,7 +554,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
const struct drm_connector_state *old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
u32 tmp, eldv;
@@ -601,7 +601,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
@@ -691,10 +691,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
@@ -752,7 +752,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct i915_audio_component *acomp = dev_priv->audio_component;
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 22e83f857de8..3f6e29f61323 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -297,7 +297,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
unsigned int data_rate = 0;
enum plane_id plane_id;
@@ -318,7 +318,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
bw_state->data_rate[crtc->pipe] =
intel_bw_crtc_data_rate(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 42bd02638d32..e7e952f0eac0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1917,10 +1917,10 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
- to_i915(crtc_state->base.crtc->dev);
+ to_i915(crtc_state->uapi.crtc->dev);
int min_cdclk;
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
return 0;
min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
@@ -2043,7 +2043,7 @@ static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
sizeof(state->min_voltage_level));
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- if (crtc_state->base.enable)
+ if (crtc_state->hw.enable)
state->min_voltage_level[i] =
crtc_state->min_voltage_level;
else
@@ -2129,7 +2129,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
vco = dev_priv->skl_preferred_vco_freq;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
continue;
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
@@ -2256,11 +2256,11 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
- if (!crtc_state->base.active ||
- drm_atomic_crtc_needs_modeset(&crtc_state->base))
+ if (!crtc_state->hw.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
continue;
- crtc_state->base.mode_changed = true;
+ crtc_state->uapi.mode_changed = true;
ret = drm_atomic_add_affected_connectors(&state->base,
&crtc->base);
@@ -2313,7 +2313,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
if (crtc_state &&
- drm_atomic_crtc_needs_modeset(&crtc_state->base))
+ drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
pipe = INVALID_PIPE;
} else {
pipe = INVALID_PIPE;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 1e3a623eaf82..703e5e70b4e5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
{
- return !crtc_state->base.degamma_lut &&
- !crtc_state->base.ctm &&
- crtc_state->base.gamma_lut &&
- lut_is_legacy(crtc_state->base.gamma_lut);
+ return !crtc_state->hw.degamma_lut &&
+ !crtc_state->hw.ctm &&
+ crtc_state->hw.gamma_lut &&
+ lut_is_legacy(crtc_state->hw.gamma_lut);
}
/*
@@ -205,7 +205,7 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/*
* FIXME if there's a gamma LUT after the CSC, we should
@@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
u16 coeffs[9])
{
- const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
const u64 *input;
u64 temp[9];
int i;
@@ -270,11 +270,11 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
bool limited_color_range = ilk_csc_limited_range(crtc_state);
- if (crtc_state->base.ctm) {
+ if (crtc_state->hw.ctm) {
u16 coeff[9];
ilk_csc_convert_ctm(crtc_state, coeff);
@@ -309,10 +309,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (crtc_state->base.ctm) {
+ if (crtc_state->hw.ctm) {
u16 coeff[9];
ilk_csc_convert_ctm(crtc_state, coeff);
@@ -338,12 +338,12 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
*/
static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (crtc_state->base.ctm) {
- const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+ if (crtc_state->hw.ctm) {
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
u16 coeffs[9] = {};
int i;
@@ -404,7 +404,7 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
const struct drm_property_blob *blob)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
int i;
@@ -435,12 +435,12 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
{
- i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
+ i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
}
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 val;
@@ -453,7 +453,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 val;
@@ -468,7 +468,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -478,7 +478,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
static void skl_color_commit(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 val = 0;
@@ -524,8 +524,8 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
static void i965_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
i9xx_load_luts(crtc_state);
@@ -547,8 +547,8 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
i9xx_load_luts(crtc_state);
@@ -654,9 +654,9 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
i9xx_load_luts(crtc_state);
@@ -677,9 +677,9 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
i9xx_load_luts(crtc_state);
@@ -700,11 +700,11 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
- const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
+ const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
u32 i;
/*
@@ -739,7 +739,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -766,8 +766,8 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
static void glk_load_luts(const struct intel_crtc_state *crtc_state)
{
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
/*
* On GLK+ both pipe CSC and degamma LUT are controlled
@@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
* the degama LUT so that we don't have to reload
* it every time the pipe CSC is being enabled.
*/
- if (crtc_state->base.degamma_lut)
+ if (crtc_state->hw.degamma_lut)
glk_load_degamma_lut(crtc_state);
else
glk_load_degamma_lut_linear(crtc_state);
@@ -808,7 +808,7 @@ static void
icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
@@ -822,8 +822,8 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
@@ -854,8 +854,8 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
static void
icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
const struct drm_color_lut *lut = blob->data;
const struct drm_color_lut *entry;
struct intel_dsb *dsb = intel_dsb_get(crtc);
@@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
static void icl_load_luts(const struct intel_crtc_state *crtc_state)
{
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_dsb *dsb = intel_dsb_get(crtc);
- if (crtc_state->base.degamma_lut)
+ if (crtc_state->hw.degamma_lut)
glk_load_degamma_lut(crtc_state);
switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
@@ -990,9 +990,9 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
static void chv_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
cherryview_load_csc_matrix(crtc_state);
@@ -1010,28 +1010,28 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
dev_priv->display.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
dev_priv->display.color_commit(crtc_state);
}
int intel_color_check(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
return dev_priv->display.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (dev_priv->display.read_luts)
dev_priv->display.read_luts(crtc_state);
@@ -1055,16 +1055,16 @@ static bool need_plane_update(struct intel_plane *plane,
static int
intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->base.state);
+ to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_plane *plane;
- if (!new_crtc_state->base.active ||
- drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
+ if (!new_crtc_state->hw.active ||
+ drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
return 0;
if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
@@ -1107,9 +1107,9 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
static int check_luts(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
int gamma_length, degamma_length;
u32 gamma_tests, degamma_tests;
@@ -1157,7 +1157,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
return ret;
crtc_state->gamma_enable =
- crtc_state->base.gamma_lut &&
+ crtc_state->hw.gamma_lut &&
!crtc_state->c8_planes;
crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
@@ -1176,11 +1176,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
if (crtc_state_is_legacy_gamma(crtc_state))
return 0;
- if (crtc_state->base.degamma_lut)
+ if (crtc_state->hw.degamma_lut)
cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
- if (crtc_state->base.ctm)
+ if (crtc_state->hw.ctm)
cgm_mode |= CGM_PIPE_MODE_CSC;
- if (crtc_state->base.gamma_lut)
+ if (crtc_state->hw.gamma_lut)
cgm_mode |= CGM_PIPE_MODE_GAMMA;
return cgm_mode;
@@ -1254,7 +1254,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
return ret;
crtc_state->gamma_enable =
- crtc_state->base.gamma_lut &&
+ crtc_state->hw.gamma_lut &&
!crtc_state->c8_planes;
/*
@@ -1280,8 +1280,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
if (!crtc_state->gamma_enable ||
crtc_state_is_legacy_gamma(crtc_state))
return GAMMA_MODE_MODE_8BIT;
- else if (crtc_state->base.gamma_lut &&
- crtc_state->base.degamma_lut)
+ else if (crtc_state->hw.gamma_lut &&
+ crtc_state->hw.degamma_lut)
return GAMMA_MODE_MODE_SPLIT;
else
return GAMMA_MODE_MODE_10BIT;
@@ -1295,7 +1295,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
* CSC comes after the LUT in degamma, RGB->YCbCr,
* and RGB full->limited range mode.
*/
- if (crtc_state->base.degamma_lut ||
+ if (crtc_state->hw.degamma_lut ||
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
limited_color_range)
return 0;
@@ -1313,13 +1313,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
return ret;
crtc_state->gamma_enable =
- (crtc_state->base.gamma_lut ||
- crtc_state->base.degamma_lut) &&
+ (crtc_state->hw.gamma_lut ||
+ crtc_state->hw.degamma_lut) &&
!crtc_state->c8_planes;
crtc_state->csc_enable =
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
- crtc_state->base.ctm || limited_color_range;
+ crtc_state->hw.ctm || limited_color_range;
crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
@@ -1350,14 +1350,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
return ret;
crtc_state->gamma_enable =
- crtc_state->base.gamma_lut &&
+ crtc_state->hw.gamma_lut &&
!crtc_state->c8_planes;
/* On GLK+ degamma LUT is controlled by csc_enable */
crtc_state->csc_enable =
- crtc_state->base.degamma_lut ||
+ crtc_state->hw.degamma_lut ||
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
- crtc_state->base.ctm || crtc_state->limited_color_range;
+ crtc_state->hw.ctm || crtc_state->limited_color_range;
crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
@@ -1374,14 +1374,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
{
u32 gamma_mode = 0;
- if (crtc_state->base.degamma_lut)
+ if (crtc_state->hw.degamma_lut)
gamma_mode |= PRE_CSC_GAMMA_ENABLE;
- if (crtc_state->base.gamma_lut &&
+ if (crtc_state->hw.gamma_lut &&
!crtc_state->c8_planes)
gamma_mode |= POST_CSC_GAMMA_ENABLE;
- if (!crtc_state->base.gamma_lut ||
+ if (!crtc_state->hw.gamma_lut ||
crtc_state_is_legacy_gamma(crtc_state))
gamma_mode |= GAMMA_MODE_MODE_8BIT;
else
@@ -1394,7 +1394,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
{
u32 csc_mode = 0;
- if (crtc_state->base.ctm)
+ if (crtc_state->hw.ctm)
csc_mode |= ICL_CSC_ENABLE;
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
@@ -1471,7 +1471,7 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!crtc_state->gamma_enable)
@@ -1580,7 +1580,7 @@ static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
static struct drm_property_blob *
i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
@@ -1614,13 +1614,13 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
{
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
}
static struct drm_property_blob *
i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
@@ -1661,15 +1661,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
static void i965_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
+ crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
}
static struct drm_property_blob *
chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
@@ -1703,15 +1703,15 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
static void chv_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
+ crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
}
static struct drm_property_blob *
ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
@@ -1744,15 +1744,15 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
static void ilk_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
+ crtc_state->uapi.gamma_lut = ilk_read_lut_10(crtc_state);
}
static struct drm_property_blob *
glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int hw_lut_size = ivb_lut_10_size(prec_index);
enum pipe pipe = crtc->pipe;
@@ -1790,9 +1790,9 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
static void glk_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+ crtc_state->uapi.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
void intel_color_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index ff6126ea793c..164af1936d38 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
{
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
- pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
+ pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
- pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(encoder, pipe_config);
- pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
+ pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
DRM_MODE_FLAG_NHSYNC |
DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_NVSYNC);
- pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
+ pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
- pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
+ pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
}
/* Note: The caller is required to filter out dpms modes not supported by the
@@ -161,8 +161,8 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 adpa;
if (INTEL_GEN(dev_priv) >= 5)
@@ -271,7 +271,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
WARN_ON(!crtc_state->has_pch_encoder);
@@ -288,7 +288,7 @@ static void hsw_enable_crt(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
WARN_ON(!crtc_state->has_pch_encoder);
@@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c1e885e0187..052caf2372d0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1527,7 +1527,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
}
static void icl_ddi_clock_get(struct intel_encoder *encoder,
@@ -1742,7 +1742,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 temp;
@@ -1802,7 +1802,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 temp;
@@ -1824,7 +1824,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
static u32
intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -1856,9 +1856,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
BUG();
}
- if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
temp |= TRANS_DDI_PVSYNC;
- if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DDI_PHSYNC;
if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1911,7 +1911,7 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 temp;
@@ -1927,7 +1927,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
static void
intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 temp;
@@ -1939,7 +1939,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
@@ -2237,7 +2237,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
enum port port = encoder->port;
@@ -2255,7 +2255,7 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_EDP) {
@@ -3562,7 +3562,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -3987,7 +3987,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
WARN_ON(crtc && crtc->active);
intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
- if (crtc_state && crtc_state->base.active)
+ if (crtc_state && crtc_state->hw.active)
intel_update_active_dpll(state, crtc, encoder);
}
@@ -4117,7 +4117,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
@@ -4135,7 +4135,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_NVSYNC;
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
switch (temp & TRANS_DDI_BPC_MASK) {
case TRANS_DDI_BPC_6:
@@ -4281,7 +4281,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
int ret;
@@ -4412,7 +4412,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return 0;
if (!crtc_state->hdmi_high_tmds_clock_ratio &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ecb15420b5ca..f555ff6b1f6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -516,7 +516,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
static bool
needs_modeset(const struct intel_crtc_state *state)
{
- return drm_atomic_crtc_needs_modeset(&state->base);
+ return drm_atomic_crtc_needs_modeset(&state->uapi);
}
/*
@@ -630,7 +630,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
const struct intel_crtc_state *crtc_state,
int target)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
/*
@@ -666,7 +666,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct dpll clock;
int err = target;
@@ -724,7 +724,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct dpll clock;
int err = target;
@@ -780,7 +780,7 @@ g4x_find_best_dpll(const struct intel_limit *limit,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct dpll clock;
int max_n;
bool found = false;
@@ -874,7 +874,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct dpll clock;
unsigned int bestppm = 1000000;
@@ -934,7 +934,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
int target, int refclk, struct dpll *match_clock,
struct dpll *best_clock)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
unsigned int best_error_ppm;
struct dpll clock;
@@ -1013,7 +1013,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
* for atomic.
*/
return crtc->active && crtc->base.primary->state->fb &&
- crtc->config->base.adjusted_mode.crtc_clock;
+ crtc->config->hw.adjusted_mode.crtc_clock;
}
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -1067,7 +1067,7 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
static void
intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (INTEL_GEN(dev_priv) >= 4) {
@@ -1526,7 +1526,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -1617,7 +1617,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t reg;
@@ -1761,7 +1761,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/*
* On i965gm the hardware frame counter reads
@@ -1781,7 +1781,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state
static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
drm_crtc_set_max_vblank_count(&crtc->base,
intel_crtc_max_vblank_count(crtc_state));
@@ -1790,7 +1790,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -1848,7 +1848,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
enum pipe pipe = crtc->pipe;
@@ -3114,14 +3114,14 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
plane_state->base.visible = visible;
if (visible)
- crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
+ crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
else
- crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
+ crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
}
static void fixup_active_planes(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct drm_plane *plane;
/*
@@ -3132,7 +3132,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
crtc_state->active_planes = 0;
drm_for_each_plane_mask(plane, &dev_priv->drm,
- crtc_state->base.plane_mask)
+ crtc_state->uapi.plane_mask)
crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
}
@@ -3606,7 +3606,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dspcntr = 0;
@@ -3760,7 +3760,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
return ret;
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
- &crtc_state->base,
+ &crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
i9xx_plane_has_windowing(plane),
@@ -3936,7 +3936,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
*/
static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
int i;
@@ -4131,7 +4131,7 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_ctl = 0;
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -4187,7 +4187,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 plane_color_ctl = 0;
if (INTEL_GEN(dev_priv) >= 11)
@@ -4803,7 +4803,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
enum pipe pipe = intel_crtc->pipe;
i915_reg_t reg;
@@ -4964,9 +4964,9 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int clock = crtc_state->base.adjusted_mode.crtc_clock;
+ int clock = crtc_state->hw.adjusted_mode.crtc_clock;
u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp;
@@ -5080,7 +5080,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
enum pipe pch_transcoder)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -5123,7 +5123,7 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e
static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
switch (crtc->pipe) {
@@ -5153,7 +5153,7 @@ static struct intel_encoder *
intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_connector_state *connector_state;
const struct drm_connector *connector;
struct intel_encoder *encoder = NULL;
@@ -5185,7 +5185,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
static void ironlake_pch_enable(const struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
@@ -5239,7 +5239,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
if (HAS_PCH_CPT(dev_priv) &&
intel_crtc_has_dp_encoder(crtc_state)) {
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
enum port port;
@@ -5269,7 +5269,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
static void lpt_pch_enable(const struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -5386,10 +5386,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
struct intel_crtc *intel_crtc =
- to_intel_crtc(crtc_state->base.crtc);
+ to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
/*
* Src coordinates are already rotated by 270 degrees for
@@ -5405,7 +5405,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
* Once NV12 is enabled, handle it here while allocating scaler
* for NV12.
*/
- if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+ if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
return -EINVAL;
@@ -5477,13 +5477,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
*/
int skl_update_scaler_crtc(struct intel_crtc_state *state)
{
- const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
bool need_scaler = false;
if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
need_scaler = true;
- return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
+ return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
&state->scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
adjusted_mode->crtc_hdisplay,
@@ -5583,7 +5583,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
@@ -5620,7 +5620,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -5641,7 +5641,7 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5677,7 +5677,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -5787,7 +5787,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!old_crtc_state->ips_enabled)
@@ -5803,7 +5803,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
* Disable IPS before we program the LUT.
*/
if (IS_HASWELL(dev_priv) &&
- (new_crtc_state->base.color_mgmt_changed ||
+ (new_crtc_state->uapi.color_mgmt_changed ||
new_crtc_state->update_pipe) &&
new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
return true;
@@ -5814,7 +5814,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!new_crtc_state->ips_enabled)
@@ -5830,7 +5830,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
* Re-enable IPS after the LUT has been programmed.
*/
if (IS_HASWELL(dev_priv) &&
- (new_crtc_state->base.color_mgmt_changed ||
+ (new_crtc_state->uapi.color_mgmt_changed ||
new_crtc_state->update_pipe) &&
new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
return true;
@@ -5840,7 +5840,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
* forcibly enable IPS on the first fastset.
*/
if (new_crtc_state->update_pipe &&
- old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
+ old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
return true;
return !old_crtc_state->ips_enabled;
@@ -5871,10 +5871,10 @@ static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *state = old_crtc_state->base.state;
+ struct drm_atomic_state *state = old_crtc_state->uapi.state;
struct intel_crtc_state *pipe_config =
intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
crtc);
@@ -5884,7 +5884,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
- if (pipe_config->update_wm_post && pipe_config->base.active)
+ if (pipe_config->update_wm_post && pipe_config->hw.active)
intel_update_watermarks(crtc);
if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
@@ -5914,10 +5914,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *pipe_config)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *state = old_crtc_state->base.state;
+ struct drm_atomic_state *state = old_crtc_state->uapi.state;
struct drm_plane *primary = crtc->base.primary;
struct drm_plane_state *old_primary_state =
drm_atomic_get_old_plane_state(state, primary);
@@ -5962,7 +5962,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* event which is after the vblank start event, so we need to have a
* wait-for-vblank between disabling the plane and the pipe.
*/
- if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
+ if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
intel_wait_for_vblank(dev_priv, crtc->pipe);
@@ -5974,7 +5974,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* WaCxSRDisabledForSpriteScaling:ivb
*/
if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
- old_crtc_state->base.active)
+ old_crtc_state->hw.active)
intel_wait_for_vblank(dev_priv, crtc->pipe);
/*
@@ -6269,7 +6269,7 @@ static void intel_encoders_update_pipe(struct intel_crtc *crtc,
static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
plane->disable_plane(plane, crtc_state);
@@ -6278,7 +6278,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6412,7 +6412,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
@@ -6521,7 +6521,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6537,7 +6537,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->base.crtc;
+ struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6596,7 +6596,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->base.crtc;
+ struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -6630,7 +6630,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!crtc_state->gmch_pfit.control)
@@ -6760,14 +6760,14 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_encoder *encoder;
enum pipe pipe = crtc->pipe;
u64 mask;
enum transcoder transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return 0;
mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
@@ -6777,7 +6777,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
drm_for_each_encoder_mask(encoder, &dev_priv->drm,
- crtc_state->base.encoder_mask) {
+ crtc_state->uapi.encoder_mask) {
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
mask |= BIT_ULL(intel_encoder->power_domain);
@@ -6795,7 +6795,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
static u64
modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain domain;
u64 domains, new_domains, old_domains;
@@ -6824,7 +6824,7 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6880,7 +6880,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
@@ -6890,7 +6890,7 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6940,7 +6940,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!old_crtc_state->gmch_pfit.control)
@@ -6956,7 +6956,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->base.crtc;
+ struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -7124,8 +7124,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
if (!crtc_state)
return;
- I915_STATE_WARN(!crtc_state->base.active,
- "connector is active, but attached crtc isn't\n");
+ I915_STATE_WARN(!crtc_state->hw.active,
+ "connector is active, but attached crtc isn't\n");
if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
return;
@@ -7136,8 +7136,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
"attached encoder crtc differs from connector crtc\n");
} else {
- I915_STATE_WARN(crtc_state && crtc_state->base.active,
- "attached crtc is active, but connector isn't\n");
+ I915_STATE_WARN(crtc_state && crtc_state->hw.active,
+ "attached crtc is active, but connector isn't\n");
I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
"best encoder set without crtc!\n");
}
@@ -7145,7 +7145,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
- if (crtc_state->base.enable && crtc_state->has_pch_encoder)
+ if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
return crtc_state->fdi_lanes;
return 0;
@@ -7155,7 +7155,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *state = pipe_config->base.state;
+ struct drm_atomic_state *state = pipe_config->uapi.state;
struct intel_crtc *other_crtc;
struct intel_crtc_state *other_crtc_state;
@@ -7228,7 +7228,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = intel_crtc->base.dev;
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int lane, link_bw, fdi_dotclock, ret;
bool needs_recompute = false;
@@ -7274,7 +7274,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* IPS only exists on ULT machines and is tied to pipe A. */
@@ -7304,9 +7304,9 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
- to_i915(crtc_state->base.crtc->dev);
+ to_i915(crtc_state->uapi.crtc->dev);
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
if (!hsw_crtc_state_ips_capable(crtc_state))
return false;
@@ -7345,7 +7345,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
{
u32 pixel_rate;
- pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
+ pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
/*
* We only use IF-ID interlacing. If we ever use
@@ -7378,12 +7378,12 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (HAS_GMCH(dev_priv))
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
crtc_state->pixel_rate =
- crtc_state->base.adjusted_mode.crtc_clock;
+ crtc_state->hw.adjusted_mode.crtc_clock;
else
crtc_state->pixel_rate =
ilk_pipe_pixel_rate(crtc_state);
@@ -7393,7 +7393,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int clock_limit = dev_priv->max_dotclk_freq;
if (INTEL_GEN(dev_priv) < 4) {
@@ -7419,7 +7419,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
- pipe_config->base.ctm) {
+ pipe_config->hw.ctm) {
/*
* There is only one pipe CSC unit per pipe, and we need that
* for output conversion from RGB->YCBCR. So if CTM is already
@@ -7613,7 +7613,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7640,7 +7640,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
const struct intel_link_m_n *m_n,
const struct intel_link_m_n *m2_n2)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum transcoder transcoder = crtc_state->cpu_transcoder;
@@ -7953,7 +7953,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
if (!pipe_config)
return -ENOMEM;
- pipe_config->base.crtc = &crtc->base;
+ pipe_config->uapi.crtc = &crtc->base;
pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
@@ -8113,11 +8113,11 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
@@ -8175,7 +8175,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -8189,7 +8189,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (IS_GEN(dev_priv, 2))
@@ -8211,39 +8211,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
u32 tmp;
tmp = I915_READ(HTOTAL(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = I915_READ(HBLANK(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_hblank_start =
+ pipe_config->hw.adjusted_mode.crtc_hblank_start =
(tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_hblank_end =
+ pipe_config->hw.adjusted_mode.crtc_hblank_end =
((tmp >> 16) & 0xffff) + 1;
}
tmp = I915_READ(HSYNC(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
tmp = I915_READ(VTOTAL(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = I915_READ(VBLANK(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_vblank_start =
+ pipe_config->hw.adjusted_mode.crtc_vblank_start =
(tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_vblank_end =
+ pipe_config->hw.adjusted_mode.crtc_vblank_end =
((tmp >> 16) & 0xffff) + 1;
}
tmp = I915_READ(VSYNC(cpu_transcoder));
- pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
- pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
+ pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
if (intel_pipe_is_interlaced(pipe_config)) {
- pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
- pipe_config->base.adjusted_mode.crtc_vtotal += 1;
- pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
+ pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
+ pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
+ pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
}
}
@@ -8258,27 +8258,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
- pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
- pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
+ pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
+ pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
}
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config)
{
- mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
- mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
- mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
- mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
+ mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
+ mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
+ mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
+ mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
- mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
- mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
- mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
- mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
+ mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
+ mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
+ mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
+ mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
- mode->flags = pipe_config->base.adjusted_mode.flags;
+ mode->flags = pipe_config->hw.adjusted_mode.flags;
mode->type = DRM_MODE_TYPE_DRIVER;
- mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
+ mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
mode->hsync = drm_mode_hsync(mode);
mode->vrefresh = drm_mode_vrefresh(mode);
@@ -8287,7 +8287,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 pipeconf;
@@ -8324,7 +8324,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
}
}
- if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (INTEL_GEN(dev_priv) < 4 ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -8733,7 +8733,7 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
@@ -8856,7 +8856,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
* but in case the pipe is enabled w/o any ports we need a sane
* default.
*/
- pipe_config->base.adjusted_mode.crtc_clock =
+ pipe_config->hw.adjusted_mode.crtc_clock =
pipe_config->port_clock / pipe_config->pixel_multiplier;
ret = true;
@@ -9371,7 +9371,7 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
u32 val;
@@ -9399,7 +9399,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
if (crtc_state->dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
@@ -9425,7 +9425,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 val = 0;
@@ -9433,7 +9433,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
if (IS_HASWELL(dev_priv) && crtc_state->dither)
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
- if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
val |= PIPECONF_INTERLACED_ILK;
else
val |= PIPECONF_PROGRESSIVE;
@@ -9448,7 +9448,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 val = 0;
@@ -9634,7 +9634,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
const struct intel_limit *limit;
int refclk = 120000;
@@ -10059,7 +10059,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
INTEL_GEN(dev_priv) >= 11) {
@@ -10630,7 +10630,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
}
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
- &crtc_state->base,
+ &crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
true, true);
@@ -10817,7 +10817,7 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 cntl = 0;
@@ -11229,12 +11229,12 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
goto fail;
}
- crtc_state->base.active = crtc_state->base.enable = true;
+ crtc_state->uapi.active = crtc_state->uapi.enable = true;
if (!mode)
mode = &load_detect_mode;
- ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
+ ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, mode);
if (ret)
goto fail;
@@ -11442,7 +11442,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
* we may need some idea for the dotclock anyway.
* Calculate one based on the FDI configuration.
*/
- pipe_config->base.adjusted_mode.crtc_clock =
+ pipe_config->hw.adjusted_mode.crtc_clock =
intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
&pipe_config->fdi_m_n);
}
@@ -11472,7 +11472,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
return NULL;
}
- crtc_state->base.crtc = &crtc->base;
+ crtc_state->uapi.crtc = &crtc->base;
if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
kfree(crtc_state);
@@ -11543,12 +11543,12 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *plane_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
bool mode_changed = needs_modeset(crtc_state);
- bool was_crtc_enabled = old_crtc_state->base.active;
- bool is_crtc_enabled = crtc_state->base.active;
+ bool was_crtc_enabled = old_crtc_state->hw.active;
+ bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
int ret;
@@ -11715,9 +11715,9 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_plane *plane, *linked;
struct intel_plane_state *plane_state;
int i;
@@ -11787,9 +11787,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->base.state);
+ to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -11807,10 +11807,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
bool mode_changed = needs_modeset(crtc_state);
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
- mode_changed && !crtc_state->base.active)
+ mode_changed && !crtc_state->hw.active)
crtc_state->update_wm_post = true;
- if (mode_changed && crtc_state->base.enable &&
+ if (mode_changed && crtc_state->hw.enable &&
dev_priv->display.crtc_compute_clock &&
!WARN_ON(crtc_state->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
@@ -11823,10 +11823,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
* when C8 planes are getting enabled/disabled.
*/
if (c8_planes_changed(crtc_state))
- crtc_state->base.color_mgmt_changed = true;
+ crtc_state->uapi.color_mgmt_changed = true;
if (mode_changed || crtc_state->update_pipe ||
- crtc_state->base.color_mgmt_changed) {
+ crtc_state->uapi.color_mgmt_changed) {
ret = intel_color_check(crtc_state);
if (ret)
return ret;
@@ -11948,7 +11948,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct drm_atomic_state *state = pipe_config->base.state;
+ struct drm_atomic_state *state = pipe_config->uapi.state;
struct drm_connector *connector;
struct drm_connector_state *connector_state;
int bpp, i;
@@ -12101,7 +12101,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state,
const char *context)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct intel_plane_state *plane_state;
struct intel_plane *plane;
@@ -12110,14 +12110,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
crtc->base.base.id, crtc->base.name,
- yesno(pipe_config->base.enable), context);
+ yesno(pipe_config->hw.enable), context);
- if (!pipe_config->base.enable)
+ if (!pipe_config->hw.enable)
goto dump_planes;
snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
- yesno(pipe_config->base.active),
+ yesno(pipe_config->hw.active),
buf, pipe_config->output_types,
output_formats(pipe_config->output_format));
@@ -12157,10 +12157,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
DRM_DEBUG_KMS("requested mode:\n");
- drm_mode_debug_printmodeline(&pipe_config->base.mode);
+ drm_mode_debug_printmodeline(&pipe_config->hw.mode);
DRM_DEBUG_KMS("adjusted mode:\n");
- drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
- intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
+ drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
+ intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
pipe_config->port_clock,
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
@@ -12278,7 +12278,7 @@ static int
clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
- to_i915(crtc_state->base.crtc->dev);
+ to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc_state *saved_state;
saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
@@ -12301,9 +12301,10 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
saved_state->wm = crtc_state->wm;
/* Keep base drm_crtc_state intact, only clear our extended struct */
- BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
- memcpy(&crtc_state->base + 1, &saved_state->base + 1,
- sizeof(*crtc_state) - sizeof(crtc_state->base));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
+ memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
+ sizeof(*crtc_state) - sizeof(crtc_state->uapi));
kfree(saved_state);
return 0;
@@ -12312,8 +12313,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
static int
intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
{
- struct drm_crtc *crtc = pipe_config->base.crtc;
- struct drm_atomic_state *state = pipe_config->base.state;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
+ struct drm_atomic_state *state = pipe_config->uapi.state;
struct intel_encoder *encoder;
struct drm_connector *connector;
struct drm_connector_state *connector_state;
@@ -12333,13 +12334,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
* positive or negative polarity is requested, treat this as meaning
* negative polarity.
*/
- if (!(pipe_config->base.adjusted_mode.flags &
+ if (!(pipe_config->hw.adjusted_mode.flags &
(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
- pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+ pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
- if (!(pipe_config->base.adjusted_mode.flags &
+ if (!(pipe_config->hw.adjusted_mode.flags &
(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
- pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+ pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
pipe_config);
@@ -12356,7 +12357,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
* computation to clearly distinguish it from the adjusted mode, which
* can be changed by the connectors in the below retry loop.
*/
- drm_mode_get_hv_timing(&pipe_config->base.mode,
+ drm_mode_get_hv_timing(&pipe_config->hw.mode,
&pipe_config->pipe_src_w,
&pipe_config->pipe_src_h);
@@ -12389,7 +12390,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
pipe_config->pixel_multiplier = 1;
/* Fill in default crtc timings, allow encoders to overwrite them. */
- drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
+ drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
CRTC_STEREO_DOUBLE);
/* Pass our mode to the connectors and the CRTC to give them a chance to
@@ -12414,7 +12415,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
/* Set default port clock if not overwritten by the encoder. Needs to be
* done afterwards in case the encoder adjusts the mode. */
if (!pipe_config->port_clock)
- pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
+ pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
* pipe_config->pixel_multiplier;
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -12458,7 +12459,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
diff = abs(clock1 - clock2);
- if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
+ if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 101)
return true;
return false;
@@ -12578,12 +12579,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
const struct intel_crtc_state *pipe_config,
bool fastset)
{
- struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
bool ret = true;
u32 bp_gamma = 0;
bool fixup_inherited = fastset &&
- (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
- !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
+ (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
+ !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
if (fixup_inherited && !fastboot_enabled(dev_priv)) {
DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
@@ -12772,19 +12773,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -12800,17 +12801,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -12849,7 +12850,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
- PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, uapi.gamma_lut, bp_gamma);
}
@@ -12894,7 +12895,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -12925,7 +12926,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
if (pipe_config->has_pch_encoder) {
int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
&pipe_config->fdi_m_n);
- int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
+ int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
/*
* FDI already provided one idea for the dotclock.
@@ -12953,7 +12954,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
const enum pipe pipe = crtc->pipe;
int plane, level, max_level = ilk_wm_max_level(dev_priv);
- if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
+ if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
return;
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
@@ -13162,12 +13163,12 @@ verify_crtc_state(struct intel_crtc *crtc,
struct drm_atomic_state *state;
bool active;
- state = old_crtc_state->base.state;
- __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
+ state = old_crtc_state->uapi.state;
+ __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
pipe_config = old_crtc_state;
memset(pipe_config, 0, sizeof(*pipe_config));
- pipe_config->base.crtc = &crtc->base;
- pipe_config->base.state = state;
+ pipe_config->uapi.crtc = &crtc->base;
+ pipe_config->uapi.state = state;
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
@@ -13175,23 +13176,26 @@ verify_crtc_state(struct intel_crtc *crtc,
/* we keep both pipes enabled on 830 */
if (IS_I830(dev_priv))
- active = new_crtc_state->base.active;
+ active = new_crtc_state->hw.active;
- I915_STATE_WARN(new_crtc_state->base.active != active,
- "crtc active state doesn't match with hw state "
- "(expected %i, found %i)\n", new_crtc_state->base.active, active);
+ I915_STATE_WARN(new_crtc_state->hw.active != active,
+ "crtc active state doesn't match with hw state "
+ "(expected %i, found %i)\n",
+ new_crtc_state->hw.active, active);
- I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
- "transitional active state does not match atomic hw state "
- "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
+ I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
+ "transitional active state does not match atomic hw state "
+ "(expected %i, found %i)\n",
+ new_crtc_state->hw.active, crtc->active);
for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
enum pipe pipe;
active = encoder->get_hw_state(encoder, &pipe);
- I915_STATE_WARN(active != new_crtc_state->base.active,
- "[ENCODER:%i] active %i with crtc active %i\n",
- encoder->base.base.id, active, new_crtc_state->base.active);
+ I915_STATE_WARN(active != new_crtc_state->hw.active,
+ "[ENCODER:%i] active %i with crtc active %i\n",
+ encoder->base.base.id, active,
+ new_crtc_state->hw.active);
I915_STATE_WARN(active && crtc->pipe != pipe,
"Encoder connected to wrong pipe %c\n",
@@ -13203,7 +13207,7 @@ verify_crtc_state(struct intel_crtc *crtc,
intel_crtc_compute_pixel_rate(pipe_config);
- if (!new_crtc_state->base.active)
+ if (!new_crtc_state->hw.active)
return;
intel_pipe_config_sanity_check(dev_priv, pipe_config);
@@ -13265,7 +13269,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
crtc_mask = drm_crtc_mask(&crtc->base);
- if (new_crtc_state->base.active)
+ if (new_crtc_state->hw.active)
I915_STATE_WARN(!(pll->active_mask & crtc_mask),
"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
@@ -13343,7 +13347,7 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/*
@@ -13374,7 +13378,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
* answer that's slightly in the future.
*/
if (IS_GEN(dev_priv, 2)) {
- const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
int vtotal;
vtotal = adjusted_mode->crtc_vtotal;
@@ -13424,7 +13428,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
/* look at all crtc's that are going to be enabled in during modeset */
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
- if (!crtc_state->base.active ||
+ if (!crtc_state->hw.active ||
!needs_modeset(crtc_state))
continue;
@@ -13449,7 +13453,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
- if (!crtc_state->base.active ||
+ if (!crtc_state->hw.active ||
needs_modeset(crtc_state))
continue;
@@ -13492,12 +13496,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->base.active)
+ if (new_crtc_state->hw.active)
state->active_pipes |= BIT(crtc->pipe);
else
state->active_pipes &= ~BIT(crtc->pipe);
- if (old_crtc_state->base.active != new_crtc_state->base.active)
+ if (old_crtc_state->hw.active != new_crtc_state->hw.active)
state->active_pipe_changes |= BIT(crtc->pipe);
}
@@ -13536,7 +13540,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
return;
- new_crtc_state->base.mode_changed = false;
+ new_crtc_state->uapi.mode_changed = false;
new_crtc_state->update_pipe = true;
/*
@@ -13571,9 +13575,9 @@ static int intel_atomic_check(struct drm_device *dev,
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->base.mode.private_flags !=
- old_crtc_state->base.mode.private_flags)
- new_crtc_state->base.mode_changed = true;
+ if (new_crtc_state->hw.mode.private_flags !=
+ old_crtc_state->hw.mode.private_flags)
+ new_crtc_state->uapi.mode_changed = true;
}
ret = drm_atomic_helper_check_modeset(dev, &state->base);
@@ -13585,7 +13589,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!needs_modeset(new_crtc_state))
continue;
- if (!new_crtc_state->base.enable) {
+ if (!new_crtc_state->uapi.enable) {
any_ms = true;
continue;
}
@@ -13693,11 +13697,11 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
- crtc->base.mode = new_crtc_state->base.mode;
+ crtc->base.mode = new_crtc_state->hw.mode;
/*
* Update pipe size and adjust fitter if needed: the reason for this is
@@ -13738,7 +13742,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
* CRTC was enabled.
*/
if (!modeset) {
- if (new_crtc_state->base.color_mgmt_changed ||
+ if (new_crtc_state->uapi.color_mgmt_changed ||
new_crtc_state->update_pipe)
intel_color_commit(new_crtc_state);
@@ -13805,7 +13809,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
* of enabling them on the CRTC's first fastset.
*/
if (new_crtc_state->update_pipe && !modeset &&
- old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
+ old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
@@ -13837,11 +13841,10 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
intel_check_pch_fifo_underruns(dev_priv);
/* FIXME unify this for all platforms */
- if (!new_crtc_state->base.active &&
+ if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
- new_crtc_state);
+ dev_priv->display.initial_watermarks(state, new_crtc_state);
}
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -13864,7 +13867,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
+ if (old_crtc_state->hw.active)
intel_old_crtc_state_disables(state,
old_crtc_state,
new_crtc_state,
@@ -13879,7 +13882,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
int i;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
- if (!new_crtc_state->base.active)
+ if (!new_crtc_state->hw.active)
continue;
intel_update_crtc(crtc, state, old_crtc_state,
@@ -13902,7 +13905,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
/* ignore allocations for crtc's that have been turned off. */
- if (new_crtc_state->base.active)
+ if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
/* If 2nd DBuf slice required, enable it here */
@@ -13924,7 +13927,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
pipe = crtc->pipe;
- if (updated & cmask || !new_crtc_state->base.active)
+ if (updated & cmask || !new_crtc_state->hw.active)
continue;
if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
@@ -13943,7 +13946,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
*/
if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
&old_crtc_state->wm.skl.ddb) &&
- !new_crtc_state->base.active_changed &&
+ !new_crtc_state->uapi.active_changed &&
state->wm_results.dirty_pipes != updated)
vbl_wait = true;
@@ -14076,12 +14079,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
bool modeset = needs_modeset(new_crtc_state);
/* Complete events for now disable pipes here. */
- if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
+ if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
spin_lock_irq(&dev->event_lock);
- drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
+ drm_crtc_send_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
spin_unlock_irq(&dev->event_lock);
- new_crtc_state->base.event = NULL;
+ new_crtc_state->uapi.event = NULL;
}
}
@@ -14112,9 +14116,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
drm_atomic_helper_wait_for_flip_done(dev, &state->base);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- if (new_crtc_state->base.active &&
+ if (new_crtc_state->hw.active &&
!needs_modeset(new_crtc_state) &&
- (new_crtc_state->base.color_mgmt_changed ||
+ (new_crtc_state->uapi.color_mgmt_changed ||
new_crtc_state->update_pipe))
intel_color_load_luts(new_crtc_state);
}
@@ -14573,16 +14577,16 @@ int
skl_max_scale(const struct intel_crtc_state *crtc_state,
const struct drm_format_info *format)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int max_scale;
int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
return DRM_PLANE_HELPER_NO_SCALING;
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
+ crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
+ max_dotclk = to_intel_atomic_state(crtc_state->uapi.state)->cdclk.logical.cdclk;
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
max_dotclk *= 2;
@@ -14715,7 +14719,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
* When crtc is inactive or there is a modeset pending,
* wait for it to complete in the slowpath
*/
- if (!crtc_state->base.active || needs_modeset(crtc_state) ||
+ if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
crtc_state->update_pipe)
goto slow;
@@ -14809,7 +14813,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
mutex_unlock(&dev_priv->drm.struct_mutex);
out_free:
if (new_crtc_state)
- intel_crtc_destroy_state(crtc, &new_crtc_state->base);
+ intel_crtc_destroy_state(crtc, &new_crtc_state->uapi);
if (ret)
intel_plane_destroy_state(plane, new_plane_state);
else
@@ -15135,7 +15139,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
ret = -ENOMEM;
goto fail;
}
- __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
+ __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
intel_crtc->config = crtc_state;
primary = intel_primary_plane_create(dev_priv, pipe);
@@ -16490,7 +16494,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
}
- if (crtc_state->base.active) {
+ if (crtc_state->hw.active) {
struct intel_plane *plane;
/* Disable everything but the primary plane */
@@ -16515,10 +16519,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
- if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
intel_crtc_disable_noatomic(&crtc->base, ctx);
- if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
+ if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
/*
* We start out with underrun reporting disabled to avoid races.
* For correct bookkeeping mark this on active crtcs.
@@ -16549,7 +16553,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
/*
* Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
@@ -16562,7 +16566,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
* road.
*/
return IS_GEN(dev_priv, 6) &&
- crtc_state->base.active &&
+ crtc_state->hw.active &&
crtc_state->shared_dpll &&
crtc_state->port_clock == 0;
}
@@ -16579,7 +16583,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
* encoder is active and trying to read from a pipe) and the
* pipe itself being active. */
bool has_active_crtc = crtc_state &&
- crtc_state->base.active;
+ crtc_state->hw.active;
if (crtc_state && has_bogus_dpll_config(crtc_state)) {
DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
@@ -16683,22 +16687,22 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
+ __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
memset(crtc_state, 0, sizeof(*crtc_state));
- __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
+ __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
- crtc_state->base.active = crtc_state->base.enable =
+ crtc_state->hw.active = crtc_state->hw.enable =
dev_priv->display.get_pipe_config(crtc, crtc_state);
- crtc->base.enabled = crtc_state->base.enable;
- crtc->active = crtc_state->base.active;
+ crtc->base.enabled = crtc_state->hw.enable;
+ crtc->active = crtc_state->hw.active;
- if (crtc_state->base.active)
+ if (crtc_state->hw.active)
dev_priv->active_pipes |= BIT(crtc->pipe);
DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
crtc->base.base.id, crtc->base.name,
- enableddisabled(crtc_state->base.active));
+ enableddisabled(crtc_state->hw.active));
}
readout_plane_state(dev_priv);
@@ -16720,7 +16724,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- if (crtc_state->base.active &&
+ if (crtc_state->hw.active &&
crtc_state->shared_dpll == pll)
pll->state.crtc_mask |= 1 << crtc->pipe;
}
@@ -16754,21 +16758,24 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
drm_connector_list_iter_begin(dev, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (connector->get_hw_state(connector)) {
- connector->base.dpms = DRM_MODE_DPMS_ON;
+ struct intel_crtc_state *crtc_state = NULL;
+ connector->base.dpms = DRM_MODE_DPMS_ON;
encoder = connector->encoder;
connector->base.encoder = &encoder->base;
- if (encoder->base.crtc &&
- encoder->base.crtc->state->active) {
+ if (encoder->base.crtc)
+ crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
+
+ if (crtc_state && crtc_state->hw.active) {
/*
* This has to be done during hardware readout
* because anything calling .crtc_disable may
* rely on the connector_mask being accurate.
*/
- encoder->base.crtc->state->connector_mask |=
+ crtc_state->uapi.connector_mask |=
drm_connector_mask(&connector->base);
- encoder->base.crtc->state->encoder_mask |=
+ crtc_state->uapi.encoder_mask |=
drm_encoder_mask(&encoder->base);
}
@@ -16791,11 +16798,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
int min_cdclk = 0;
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
- if (crtc_state->base.active) {
+ if (crtc_state->hw.active) {
intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
- intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
+ intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
+ crtc_state);
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
/*
@@ -16807,7 +16815,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
* set a flag to indicate that a full recalculation is
* needed on the next commit.
*/
- crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
+ crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
intel_crtc_compute_pixel_rate(crtc_state);
@@ -16818,7 +16826,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
}
drm_calc_timestamping_constants(&crtc->base,
- &crtc_state->base.adjusted_mode);
+ &crtc_state->hw.adjusted_mode);
update_scanline_offset(crtc_state);
}
@@ -16989,7 +16997,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
drm_crtc_vblank_reset(&crtc->base);
- if (crtc_state->base.active)
+ if (crtc_state->hw.active)
intel_crtc_vblank_on(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bc2cf4bec0e8..44a1c331d6b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -443,10 +443,10 @@ enum phy_fia {
#define intel_atomic_crtc_state_for_each_plane_state( \
plane, plane_state, \
crtc_state) \
- for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
- ((crtc_state)->base.plane_mask)) \
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
+ ((crtc_state)->uapi.plane_mask)) \
for_each_if ((plane_state = \
- to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 526423437f63..0ee69e8f0942 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -749,7 +749,31 @@ enum intel_output_format {
};
struct intel_crtc_state {
- struct drm_crtc_state base;
+ union {
+ /*
+ * uapi (drm) state. This is the software state shown to userspace.
+ * In particular, the following members are used for bookkeeping:
+ * - crtc
+ * - state
+ * - *_changed
+ * - event
+ * - commit
+ * - mode_blob
+ */
+ struct drm_crtc_state uapi;
+
+ /*
+ * actual hardware state, the state we program to the hardware.
+ * The following members are used to verify the hardware state:
+ * - enable
+ * - active
+ * - mode / adjusted_mode
+ * - color property blobs.
+ *
+ * During initial hw readout, they need to be copied to uapi.
+ */
+ struct drm_crtc_state hw;
+ };
/**
* quirks - bitfield with hw state readout quirks
@@ -1093,7 +1117,7 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
-#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
+#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1aa39e92f0df..4297738655c6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1967,7 +1967,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
const struct link_config_limits *limits)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int bpp, clock, lane_count;
int mode_rate, link_clock, link_avail;
@@ -2021,7 +2021,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -2132,7 +2132,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct link_config_limits limits;
int common_len;
@@ -2220,8 +2220,8 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
{
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ &crtc_state->hw.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
int ret;
if (!drm_mode_is_420_only(info, adjusted_mode) ||
@@ -2249,7 +2249,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
const struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
/*
* Our YCbCr output is always limited range.
@@ -2282,11 +2282,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
enum port port = encoder->port;
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
@@ -2400,8 +2400,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
pipe_config->lane_count,
@@ -2998,7 +2998,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -3038,7 +3038,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -3198,7 +3198,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
u32 tmp, flags = 0;
enum port port = encoder->port;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3233,7 +3233,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
}
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
@@ -3250,7 +3250,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->port_clock = 270000;
}
- pipe_config->base.adjusted_mode.crtc_clock =
+ pipe_config->hw.adjusted_mode.crtc_clock =
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
@@ -3465,7 +3465,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
u32 dp_reg = I915_READ(intel_dp->output_reg);
enum pipe pipe = crtc->pipe;
intel_wakeref_t wakeref;
@@ -3598,7 +3598,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
lockdep_assert_held(&dev_priv->pps_mutex);
@@ -4120,7 +4120,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum port port = encoder->port;
u32 DP = intel_dp->DP;
@@ -4881,7 +4881,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return 0;
if (conn_state->commit &&
@@ -6700,7 +6700,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
int refresh_rate)
{
struct intel_dp *intel_dp = dev_priv->drrs.dp;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
if (refresh_rate <= 0) {
@@ -6733,7 +6733,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
return;
}
- if (!crtc_state->base.active) {
+ if (!crtc_state->hw.active) {
DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2203be28ea01..cecb7ba5b482 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -42,13 +42,13 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
- struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
void *port = connector->port;
bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
@@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
void *port = connector->port;
struct link_config_limits limits;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 556d1b30f06a..704f38681c4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
u32 val;
@@ -783,7 +783,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
{
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
unsigned int lane_mask =
@@ -864,7 +864,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel ch = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
int data, i, stagger;
@@ -953,7 +953,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
u32 val;
vlv_dpio_get(dev_priv);
@@ -1016,7 +1016,7 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
{
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel port = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
@@ -1046,7 +1046,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum dpio_channel port = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
u32 val;
@@ -1075,7 +1075,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
{
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum dpio_channel port = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 5e9e84c94a15..c2603aa56767 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -136,7 +136,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
*/
void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -163,7 +163,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
*/
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
@@ -208,7 +208,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
*/
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
@@ -825,7 +825,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
static struct intel_shared_dpll *
hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_shared_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1734,7 +1734,7 @@ static bool
bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
struct bxt_clk_div *clk_div)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct dpll best_clock;
/* Calculate HDMI div */
@@ -2257,7 +2257,7 @@ static bool
cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *wrpll_params)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 afe_clock = crtc_state->port_clock * 5;
u32 ref_clock;
u32 dco_min = 7998000;
@@ -2535,7 +2535,7 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *pll_params)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
dev_priv->cdclk.hw.ref == 24000 ?
icl_dp_combo_pll_24MHz_values :
@@ -2557,7 +2557,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params *pll_params)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (INTEL_GEN(dev_priv) >= 12) {
switch (dev_priv->cdclk.hw.ref) {
@@ -2594,7 +2594,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder,
struct intel_dpll_hw_state *pll_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 cfgcr0, cfgcr1;
struct skl_wrpll_params pll_params = { 0 };
bool ret;
@@ -2726,7 +2726,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int refclk_khz = dev_priv->cdclk.hw.ref;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 9827f99491d1..28770c5765ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_NVSYNC;
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
- pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void intel_disable_dvo(struct intel_encoder *encoder,
@@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
u32 temp = I915_READ(dvo_reg);
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
- &pipe_config->base.mode,
- &pipe_config->base.adjusted_mode);
+ &pipe_config->hw.mode,
+ &pipe_config->hw.adjusted_mode);
I915_WRITE(dvo_reg, temp | DVO_ENABLE);
I915_READ(dvo_reg);
@@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
const struct drm_display_mode *fixed_mode =
intel_dvo->attached_connector->panel.fixed_mode;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
/*
* If we have timings from the BIOS for the panel, put them in
@@ -277,8 +277,8 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
enum pipe pipe = crtc->pipe;
u32 dvo_val;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 3111ecaeabd0..c6cc3775f3b8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->vma = NULL;
cache->flags = 0;
- cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
+ cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0a6846c5ba95..fd75016bd1e6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -279,7 +279,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
int i;
@@ -315,7 +315,7 @@ static void ibx_read_infoframe(struct intel_encoder *encoder,
void *frame, ssize_t len)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
u32 val, *data = frame;
int i;
@@ -334,7 +334,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
u32 val = I915_READ(reg);
@@ -356,7 +356,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
int i;
@@ -395,7 +395,7 @@ static void cpt_read_infoframe(struct intel_encoder *encoder,
void *frame, ssize_t len)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
u32 val, *data = frame;
int i;
@@ -414,7 +414,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -432,7 +432,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
{
const u32 *data = frame;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
int i;
@@ -468,7 +468,7 @@ static void vlv_read_infoframe(struct intel_encoder *encoder,
void *frame, ssize_t len)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
u32 val, *data = frame;
int i;
@@ -487,7 +487,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -700,7 +700,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
{
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
struct drm_connector *connector = conn_state->connector;
int ret;
@@ -796,7 +796,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
conn_state->connector,
- &crtc_state->base.adjusted_mode);
+ &crtc_state->hw.adjusted_mode);
if (WARN_ON(ret))
return false;
@@ -957,7 +957,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
i915_reg_t reg;
if ((crtc_state->infoframes.enable &
@@ -982,7 +982,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
i915_reg_t reg;
if ((crtc_state->infoframes.enable &
@@ -1019,7 +1019,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
/* Enable default_phase whenever the display mode is suitably aligned */
if (gcp_default_phase_possible(crtc_state->pipe_bpp,
- &crtc_state->base.adjusted_mode))
+ &crtc_state->hw.adjusted_mode))
crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
}
@@ -1029,7 +1029,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
@@ -1088,7 +1088,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
@@ -1137,7 +1137,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
@@ -1733,9 +1733,9 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 hdmi_val;
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
@@ -1826,7 +1826,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
tmp & HDMI_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
dotclock = pipe_config->port_clock * 2 / 3;
@@ -1836,7 +1836,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
pipe_config->lane_count = 4;
@@ -1857,7 +1857,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
WARN_ON(!pipe_config->has_hdmi_sink);
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
@@ -1943,7 +1943,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
enum pipe pipe = crtc->pipe;
u32 temp;
@@ -2007,7 +2007,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct intel_digital_port *intel_dig_port =
hdmi_to_dig_port(intel_hdmi);
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
u32 temp;
temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -2207,12 +2207,12 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
int bpc)
{
struct drm_i915_private *dev_priv =
- to_i915(crtc_state->base.crtc->dev);
- struct drm_atomic_state *state = crtc_state->base.state;
+ to_i915(crtc_state->uapi.crtc->dev);
+ struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_connector_state *connector_state;
struct drm_connector *connector;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
int i;
if (HAS_GMCH(dev_priv))
@@ -2237,7 +2237,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
for_each_new_connector_in_state(state, connector, connector_state, i) {
const struct drm_display_info *info = &connector->display_info;
- if (connector_state->crtc != crtc_state->base.crtc)
+ if (connector_state->crtc != crtc_state->uapi.crtc)
continue;
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
@@ -2278,7 +2278,7 @@ static bool
intel_hdmi_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *config)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc);
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
@@ -2333,7 +2333,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
int bpc, clock = adjusted_mode->crtc_clock;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
@@ -2375,7 +2375,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
const struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
/*
* Our YCbCr output is always limited range.
@@ -2403,7 +2403,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_connector *connector = conn_state->connector;
struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
struct intel_digital_connector_state *intel_conn_state =
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f8f1308643a9..5145ff8b962b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
{
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
if (drm_mode_is_420_only(info, adjusted_mode) &&
connector->ycbcr_420_allowed) {
@@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
struct intel_lspcon *lspcon = &dig_port->lspcon;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
if (!lspcon->active) {
DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 13841d7c455b..ca4ebb0f2230 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
else
flags |= DRM_MODE_FLAG_PVSYNC;
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
if (INTEL_GEN(dev_priv) < 5)
pipe_config->gmch_pfit.lvds_border_bits =
@@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
}
- pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+ pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
@@ -230,8 +230,8 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
{
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
u32 temp;
@@ -392,8 +392,8 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
to_lvds_encoder(&intel_encoder->base);
struct intel_connector *intel_connector =
lvds_encoder->attached_connector;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
unsigned int lvds_bpp;
/* Should never happen!! */
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..6f3eaae3761f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
struct intel_crtc_state *pipe_config,
int fitting_mode)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int x = 0, y = 0, width = 0, height = 0;
/* Native modes don't need fitting */
@@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
pipe_config->pipe_src_h;
u32 scaled_height = pipe_config->pipe_src_w *
@@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
u32 *pfit_control, u32 *pfit_pgm_ratios,
u32 *border)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
pipe_config->pipe_src_h;
u32 scaled_height = pipe_config->pipe_src_w *
@@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
{
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
@@ -1047,7 +1047,7 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
- enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
u32 ctl, ctl2;
ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
@@ -1077,7 +1077,7 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
- enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
u32 pwm_ctl, val;
/* Controller 1 uses the utility pin. */
@@ -1189,7 +1189,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
- enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
if (!panel->backlight.present)
return;
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 6260a2082719..2746512f4466 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -309,13 +309,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
goto put_state;
}
- pipe_config->base.mode_changed = pipe_config->has_psr;
+ pipe_config->uapi.mode_changed = pipe_config->has_psr;
pipe_config->crc_enabled = enable;
if (IS_HASWELL(dev_priv) &&
- pipe_config->base.active && crtc->pipe == PIPE_A &&
+ pipe_config->hw.active && crtc->pipe == PIPE_A &&
pipe_config->cpu_transcoder == TRANSCODER_EDP)
- pipe_config->base.mode_changed = true;
+ pipe_config->uapi.mode_changed = true;
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b3c7eef53bf3..8988dbe8c19e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -538,8 +538,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
- int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
+ int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
+ int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0;
if (!dev_priv->psr.sink_psr2_support)
@@ -605,7 +605,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
int psr_setup_time;
if (!CAN_PSR(dev_priv))
@@ -745,7 +745,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
- dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
/*
@@ -988,7 +988,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 47f5d87a938a..1047357c15c4 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
{
struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
int ret;
if (!crtc_state->has_hdmi_sink)
@@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
to_intel_sdvo_connector_state(conn_state);
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(conn_state->connector);
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- struct drm_display_mode *mode = &pipe_config->base.mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_display_mode *mode = &pipe_config->hw.mode;
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
@@ -1429,13 +1429,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
const struct intel_sdvo_connector_state *sdvo_state =
to_intel_sdvo_connector_state(conn_state);
const struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(conn_state->connector);
- const struct drm_display_mode *mode = &crtc_state->base.mode;
+ const struct drm_display_mode *mode = &crtc_state->hw.mode;
struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
u32 sdvox;
struct intel_sdvo_in_out_map in_out;
@@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
}
- pipe_config->base.adjusted_mode.flags |= flags;
+ pipe_config->hw.adjusted_mode.flags |= flags;
/*
* pixel multiplier readout is tricky: Only on i915g/gm it is stored in
@@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
/* Cross check the port pixel multiplier with the sdvo encoder state. */
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
@@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
const struct drm_connector_state *conn_state)
{
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
struct drm_connector *connector = conn_state->connector;
u8 *eld = connector->eld;
@@ -1723,7 +1723,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
u32 temp;
if (old_crtc_state->has_audio)
@@ -1785,7 +1785,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
u32 temp;
bool input1, input2;
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 633fa8069348..526a9366b682 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -81,9 +81,9 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
*/
void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -190,7 +190,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
*/
void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
int scanline_end = intel_get_crtc_scanline(crtc);
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
@@ -203,14 +203,15 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
* while ... */
- if (new_crtc_state->base.event) {
+ if (new_crtc_state->uapi.event) {
WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
spin_lock(&crtc->base.dev->event_lock);
- drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
+ drm_crtc_arm_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
spin_unlock(&crtc->base.dev->event_lock);
- new_crtc_state->base.event = NULL;
+ new_crtc_state->uapi.event = NULL;
}
local_irq_enable();
@@ -1515,7 +1516,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
const struct drm_rect *dst = &plane_state->base.dst;
int src_x, src_w, src_h, crtc_w, crtc_h;
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
unsigned int stride = plane_state->color_plane[0].stride;
unsigned int cpp = fb->format->cpp[0];
unsigned int width_bytes;
@@ -1588,7 +1589,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
}
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
- &crtc_state->base,
+ &crtc_state->uapi,
min_scale, max_scale,
true, true);
if (ret)
@@ -1645,7 +1646,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return ret;
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
- &crtc_state->base,
+ &crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
true, true);
@@ -1729,8 +1730,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
}
/* Y-tiling is not supported in IF-ID Interlace mode */
- if (crtc_state->base.enable &&
- crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
+ if (crtc_state->hw.enable &&
+ crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -1810,7 +1811,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
}
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
- &crtc_state->base,
+ &crtc_state->uapi,
min_scale, max_scale,
true, true);
if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 70726b481244..4499d402c316 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -924,7 +924,7 @@ intel_enable_tv(struct intel_encoder *encoder,
/* Prevents vblank waits from timing out in intel_tv_detect_type() */
intel_wait_for_vblank(dev_priv,
- to_intel_crtc(pipe_config->base.crtc)->pipe);
+ to_intel_crtc(pipe_config->uapi.crtc)->pipe);
I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
}
@@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
struct drm_display_mode mode = {};
u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
struct tv_mode tv_mode = {};
@@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
to_intel_tv_connector_state(conn_state);
const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
int hdisplay = adjusted_mode->crtc_hdisplay;
int vdisplay = adjusted_mode->crtc_vdisplay;
@@ -1417,7 +1417,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_tv *intel_tv = enc_to_tv(encoder);
const struct intel_tv_connector_state *tv_conn_state =
to_intel_tv_connector_state(conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d4fb7f16f9f6..38c181499505 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
int column_index = 0;
u8 line_buf_depth = 0;
- vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
- vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
+ vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
+ vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc_params.slice_count);
/*
@@ -459,7 +459,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
@@ -483,7 +483,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
enum pipe pipe = crtc->pipe;
@@ -902,7 +902,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
@@ -938,7 +938,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 50064cde0724..16f93d1e71e5 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -261,9 +261,9 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int ret;
DRM_DEBUG_KMS("\n");
@@ -624,7 +624,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
@@ -746,7 +746,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct drm_crtc *crtc = pipe_config->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
@@ -1032,9 +1032,9 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
struct drm_display_mode *adjusted_mode_sw;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
unsigned int lane_count = intel_dsi->lane_count;
unsigned int bpp, fmt;
@@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
crtc_hblank_start_sw, crtc_hblank_end_sw;
/* FIXME: hw readout should not depend on SW state */
- adjusted_mode_sw = &crtc->config->base.adjusted_mode;
+ adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
/*
* Atleast one port is active as encoder->get_config called only if
@@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
}
if (pclk) {
- pipe_config->base.adjusted_mode.crtc_clock = pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = pclk;
pipe_config->port_clock = pclk;
}
}
@@ -1315,9 +1315,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
enum port port;
unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
u32 val, tmp;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fec9fb7cc384..7ce3ae1ec586 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2752,11 +2752,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
crtc->base.base.id, pipe_name(crtc->pipe),
- yesno(pipe_config->base.active),
+ yesno(pipe_config->hw.active),
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
yesno(pipe_config->dither), pipe_config->pipe_bpp);
- if (pipe_config->base.active) {
+ if (pipe_config->hw.active) {
struct intel_plane *cursor =
to_intel_plane(crtc->base.cursor);
@@ -4208,11 +4208,11 @@ static int i915_drrs_ctl_set(void *data, u64 val)
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (!crtc_state->base.active ||
+ if (!crtc_state->hw.active ||
!crtc_state->has_drrs)
goto out;
- commit = crtc_state->base.commit;
+ commit = crtc_state->uapi.commit;
if (commit) {
ret = wait_for_completion_interruptible(&commit->hw_done);
if (ret)
@@ -4224,7 +4224,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
struct intel_encoder *encoder;
struct intel_dp *intel_dp;
- if (!(crtc_state->base.connector_mask &
+ if (!(crtc_state->uapi.connector_mask &
drm_connector_mask(connector)))
continue;
@@ -4283,14 +4283,14 @@ i915_fifo_underrun_reset_write(struct file *filp,
return ret;
crtc_state = to_intel_crtc_state(intel_crtc->base.state);
- commit = crtc_state->base.commit;
+ commit = crtc_state->uapi.commit;
if (commit) {
ret = wait_for_completion_interruptible(&commit->hw_done);
if (!ret)
ret = wait_for_completion_interruptible(&commit->flip_done);
}
- if (!ret && crtc_state->base.active) {
+ if (!ret && crtc_state->hw.active) {
DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
pipe_name(intel_crtc->pipe));
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5e6e54cb22fe..4c9359981c24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -464,7 +464,7 @@ static const int pessimal_latency_ns = 5000;
static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
enum pipe pipe = crtc->pipe;
@@ -798,7 +798,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
/* FIXME check the 'enable' instead */
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return false;
/*
@@ -851,7 +851,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
crtc = single_enabled_crtc(dev_priv);
if (crtc) {
const struct drm_display_mode *adjusted_mode =
- &crtc->config->base.adjusted_mode;
+ &crtc->config->hw.adjusted_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp = fb->format->cpp[0];
@@ -1087,7 +1087,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
unsigned int clock, htotal, cpp, width, wm;
@@ -1144,7 +1144,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
int level, enum plane_id plane_id, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
bool dirty = false;
for (; level < intel_wm_num_levels(dev_priv); level++) {
@@ -1160,7 +1160,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
int level, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
bool dirty = false;
/* NORMAL level doesn't have an FBC watermark */
@@ -1262,7 +1262,7 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
int level)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (level > dev_priv->wm.max_level)
return false;
@@ -1300,9 +1300,9 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
int num_active_planes = hweight8(crtc_state->active_planes &
~BIT(PLANE_CURSOR));
@@ -1389,17 +1389,17 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(new_crtc_state->base.state);
+ to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(intel_state, crtc);
const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
enum plane_id plane_id;
- if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
*intermediate = *optimal;
intermediate->cxsr = false;
@@ -1531,8 +1531,8 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
static void g4x_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1543,8 +1543,8 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -1593,7 +1593,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
unsigned int clock, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
@@ -1631,7 +1631,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct g4x_pipe_wm *raw =
&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
@@ -1743,7 +1743,7 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
int level, enum plane_id plane_id, u16 value)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int num_levels = intel_wm_num_levels(dev_priv);
bool dirty = false;
@@ -1818,16 +1818,16 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
int num_active_planes = hweight8(crtc_state->active_planes &
~BIT(PLANE_CURSOR));
- bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
+ bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
const struct intel_plane_state *old_plane_state;
const struct intel_plane_state *new_plane_state;
struct intel_plane *plane;
@@ -1926,7 +1926,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
const struct vlv_fifo_state *fifo_state =
@@ -2022,17 +2022,17 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(new_crtc_state->base.state);
+ to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(intel_state, crtc);
const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
int level;
- if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+ if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
*intermediate = *optimal;
intermediate->cxsr = false;
@@ -2150,8 +2150,8 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
static void vlv_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2162,8 +2162,8 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -2188,7 +2188,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
const struct drm_display_mode *adjusted_mode =
- &crtc->config->base.adjusted_mode;
+ &crtc->config->hw.adjusted_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int clock = adjusted_mode->crtc_clock;
@@ -2269,7 +2269,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
- &crtc->config->base.adjusted_mode;
+ &crtc->config->hw.adjusted_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2296,7 +2296,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
- &crtc->config->base.adjusted_mode;
+ &crtc->config->hw.adjusted_mode;
const struct drm_framebuffer *fb =
crtc->base.primary->state->fb;
int cpp;
@@ -2344,7 +2344,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *adjusted_mode =
- &enabled->config->base.adjusted_mode;
+ &enabled->config->hw.adjusted_mode;
const struct drm_framebuffer *fb =
enabled->base.primary->state->fb;
int clock = adjusted_mode->crtc_clock;
@@ -2402,7 +2402,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
if (crtc == NULL)
return;
- adjusted_mode = &crtc->config->base.adjusted_mode;
+ adjusted_mode = &crtc->config->hw.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
&i845_wm_info,
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
@@ -2492,7 +2492,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
return method1;
method2 = ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->base.adjusted_mode.crtc_htotal,
+ crtc_state->hw.adjusted_mode.crtc_htotal,
drm_rect_width(&plane_state->base.dst),
cpp, mem_value);
@@ -2520,7 +2520,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->base.adjusted_mode.crtc_htotal,
+ crtc_state->hw.adjusted_mode.crtc_htotal,
drm_rect_width(&plane_state->base.dst),
cpp, mem_value);
return min(method1, method2);
@@ -2545,7 +2545,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
cpp = plane_state->base.fb->format->cpp[0];
return ilk_wm_method2(crtc_state->pixel_rate,
- crtc_state->base.adjusted_mode.crtc_htotal,
+ crtc_state->hw.adjusted_mode.crtc_htotal,
drm_rect_width(&plane_state->base.dst),
cpp, mem_value);
}
@@ -2767,12 +2767,12 @@ static u32
hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
{
const struct intel_atomic_state *intel_state =
- to_intel_atomic_state(crtc_state->base.state);
+ to_intel_atomic_state(crtc_state->uapi.state);
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
u32 linetime, ips_linetime;
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return 0;
if (WARN_ON(adjusted_mode->crtc_clock == 0))
return 0;
@@ -3082,11 +3082,9 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
/* Compute new watermarks for the pipe */
static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct drm_atomic_state *state = crtc_state->base.state;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_pipe_wm *pipe_wm;
- struct drm_device *dev = state->dev;
- const struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
const struct intel_plane_state *pristate = NULL;
@@ -3106,7 +3104,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
curstate = plane_state;
}
- pipe_wm->pipe_enabled = crtc_state->base.active;
+ pipe_wm->pipe_enabled = crtc_state->hw.active;
if (sprstate) {
pipe_wm->sprites_enabled = sprstate->base.visible;
pipe_wm->sprites_scaled = sprstate->base.visible &&
@@ -3163,11 +3161,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
*/
static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(newstate->base.state);
+ to_intel_atomic_state(newstate->uapi.state);
const struct intel_crtc_state *oldstate =
intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
@@ -3179,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
* and after the vblank.
*/
*a = newstate->wm.ilk.optimal;
- if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
+ if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
intel_state->skip_intermediate_wm)
return 0;
@@ -3756,7 +3754,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
- if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
@@ -3806,7 +3804,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->base.adjusted_mode;
+ adjusted_mode = &crtc_state->hw.adjusted_mode;
total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
/*
@@ -3835,16 +3833,16 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
- struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct drm_crtc *for_crtc = crtc_state->base.crtc;
+ struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
const struct intel_crtc *crtc;
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
u32 i;
- if (WARN_ON(!state) || !crtc_state->base.active) {
+ if (WARN_ON(!state) || !crtc_state->hw.active) {
alloc->start = 0;
alloc->end = 0;
*num_active = hweight8(dev_priv->active_pipes);
@@ -3883,11 +3881,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
*/
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
+ &crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3918,7 +3916,7 @@ static unsigned int
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
int num_active)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level wm = {};
int ret, min_ddb_alloc = 0;
@@ -4076,7 +4074,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
{
uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
return pipe_downscale;
if (crtc_state->pch_pfit.enabled) {
@@ -4108,7 +4106,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
const struct intel_plane_state *plane_state;
struct intel_plane *plane;
int crtc_clock, dotclk;
@@ -4116,7 +4114,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
uint_fixed_16_16_t pipe_downscale;
uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
- if (!crtc_state->base.enable)
+ if (!crtc_state->hw.enable)
return 0;
intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
@@ -4142,7 +4140,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
+ crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
@@ -4209,7 +4207,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
u64 *plane_data_rate,
u64 *uv_plane_data_rate)
{
- struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
@@ -4244,7 +4242,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state;
u64 total_data_rate = 0;
- if (WARN_ON(!crtc_state->base.state))
+ if (WARN_ON(!crtc_state->uapi.state))
return 0;
/* Calculate and cache data rate for each plane */
@@ -4288,8 +4286,8 @@ static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
{
- struct drm_atomic_state *state = crtc_state->base.state;
- struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
@@ -4311,7 +4309,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
if (WARN_ON(!state))
return 0;
- if (!crtc_state->base.active) {
+ if (!crtc_state->hw.active) {
alloc->start = alloc->end = 0;
return 0;
}
@@ -4553,7 +4551,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
u32 crtc_htotal;
uint_fixed_16_16_t linetime_us;
- if (!crtc_state->base.active)
+ if (!crtc_state->hw.active)
return u32_to_fixed16(0);
pixel_rate = crtc_state->pixel_rate;
@@ -4561,7 +4559,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
if (WARN_ON(pixel_rate == 0))
return u32_to_fixed16(0);
- crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
+ crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
return linetime_us;
@@ -4596,7 +4594,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 interm_pbpl;
@@ -4717,7 +4715,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
@@ -4743,14 +4741,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
wp->cpp, latency, wp->dbuf_block_size);
method2 = skl_wm_method2(wp->plane_pixel_rate,
- crtc_state->base.adjusted_mode.crtc_htotal,
+ crtc_state->hw.adjusted_mode.crtc_htotal,
latency,
wp->plane_blocks_per_line);
if (wp->y_tiled) {
selected_result = max_fixed16(method2, wp->y_tile_minimum);
} else {
- if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
+ if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
wp->dbuf_block_size < 1) &&
(wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
selected_result = method2;
@@ -4841,7 +4839,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
struct skl_wm_level *result_prev = &levels[0];
@@ -4858,7 +4856,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
static u32
skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
{
- struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_i915_private *dev_priv = to_i915(state->dev);
uint_fixed_16_16_t linetime_us;
u32 linetime_wm;
@@ -4877,7 +4875,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
{
- struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
u16 trans_min, trans_y_tile_min;
const u16 trans_amount = 10; /* This is configurable amount */
@@ -5037,7 +5035,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
@@ -5227,8 +5225,8 @@ static int
skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+ struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
@@ -5529,7 +5527,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
* power well the hardware state will go out of sync
* with the software state.
*/
- if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
+ if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
skl_plane_wm_equals(dev_priv,
&old_crtc_state->wm.skl.optimal.planes[plane_id],
&new_crtc_state->wm.skl.optimal.planes[plane_id]))
@@ -5597,7 +5595,7 @@ skl_compute_wm(struct intel_atomic_state *state)
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
@@ -5611,7 +5609,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
static void skl_initial_wm(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct skl_ddb_values *results = &state->wm_results;
@@ -5621,7 +5619,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
- if (crtc_state->base.active_changed)
+ if (crtc_state->uapi.active_changed)
skl_atomic_update_crtc_wm(state, crtc_state);
mutex_unlock(&dev_priv->wm.wm_mutex);
@@ -5680,8 +5678,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
static void ilk_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5692,8 +5690,8 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
--
2.23.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
2019-10-04 11:34 ` [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state Maarten Lankhorst
@ 2019-10-08 17:06 ` Ville Syrjälä
2019-10-10 14:21 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-08 17:06 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> We want to split drm_crtc_state into the user visible state
> and actual hardware state. To prepare for this, we need some
> ground rules what should be in each state:
>
> In uapi we use:
> - crtc, *_changed flags, event, commit, state, mode_blob,
> (plane/connector/encoder)_mask.
>
> In hw state we use what's displayed in hardware:
> - enable, active, (adjusted) mode, color property blobs.
>
> clear_intel_crtc_state and hw readout need to be updated for these rules,
> which will allow us to enable 2 joined pipes.
I still have hard time with reading this patch. I still think it
would be easier to read if we didn't do both the "uapi" and "hw" changes
at the same time.
step 1.
struct drm_crtc_state uapi;
struct {
// hw state
} base;
step 2.
s/base/hw/
I think that would make it more obvious which parts of the code are
looking at which state.
>
> Note:
> - When making calling atomic_commit() you need to manipulate the uapi
> variables, atomic_check() will copy it to hw. This is because you're
> just another atomic client. Of course you can still check hw members
> at that point to decide if a pipe is active.
> - In general you should look at the hw members when available, unless
> there's a good reason to do something else.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 18 +-
> drivers/gpu/drm/i915/display/intel_atomic.c | 14 +-
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 12 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
> drivers/gpu/drm/i915/display/intel_color.c | 180 +++---
> drivers/gpu/drm/i915/display/intel_crt.c | 24 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +-
> drivers/gpu/drm/i915/display/intel_display.c | 544 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 28 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 42 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 14 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +-
> drivers/gpu/drm/i915/display/intel_dvo.c | 14 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 64 +--
> drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 12 +-
> drivers/gpu/drm/i915/display/intel_panel.c | 14 +-
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 22 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 25 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 20 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
> drivers/gpu/drm/i915/intel_pm.c | 170 +++---
> 31 files changed, 700 insertions(+), 665 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..0e24b8e257e5 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
>
> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> u32 dss_ctl2;
> u16 hactive = adjusted_mode->crtc_hdisplay;
> u16 dl_buffer_depth;
> @@ -625,7 +625,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum pipe pipe = intel_crtc->pipe;
> u32 tmp;
> enum port port;
> @@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> enum port port;
> enum transcoder dsi_trans;
> /* horizontal timings */
> @@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (intel_dsi->dual_link) {
> adjusted_mode->crtc_hdisplay *= 2;
> @@ -1242,16 +1242,16 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> pipe_config->port_clock =
> cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
>
> - pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> + pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> - pipe_config->base.adjusted_mode.crtc_clock *= 2;
> + pipe_config->hw.adjusted_mode.crtc_clock *= 2;
>
> gen11_dsi_get_timings(encoder, pipe_config);
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> @@ -1265,11 +1265,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> const struct drm_display_mode *fixed_mode =
> intel_connector->panel.fixed_mode;
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index e6cb85d41c8d..7cf13b9c7d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -186,13 +186,14 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
> struct drm_crtc_state *
> intel_crtc_duplicate_state(struct drm_crtc *crtc)
> {
> + const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
> struct intel_crtc_state *crtc_state;
>
> - crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
> + crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
> if (!crtc_state)
> return NULL;
>
> - __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
> + __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
>
> crtc_state->update_pipe = false;
> crtc_state->disable_lp_wm = false;
> @@ -204,7 +205,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> crtc_state->fb_bits = 0;
> crtc_state->update_planes = 0;
>
> - return &crtc_state->base;
> + return &crtc_state->uapi;
> }
>
> /**
> @@ -219,7 +220,10 @@ void
> intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state)
> {
> - drm_atomic_helper_crtc_destroy_state(crtc, state);
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> +
> + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> + kfree(crtc_state);
> }
>
> static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> @@ -315,7 +319,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> {
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> - struct drm_atomic_state *drm_state = crtc_state->base.state;
> + struct drm_atomic_state *drm_state = crtc_state->uapi.state;
> struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> int num_scalers_need;
> int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 4eaab0de98bf..ca82167d4ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -271,7 +271,7 @@ void intel_update_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_update_plane(&plane->base, crtc);
> plane->update_plane(plane, crtc_state, plane_state);
> @@ -281,7 +281,7 @@ void intel_update_slave(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_update_plane(&plane->base, crtc);
> plane->update_slave(plane, crtc_state, plane_state);
> @@ -290,7 +290,7 @@ void intel_update_slave(struct intel_plane *plane,
> void intel_disable_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_disable_plane(&plane->base, crtc);
> plane->disable_plane(plane, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 54638d99e021..19b2af4b9f81 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
> static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
> {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int i;
>
> for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> @@ -554,7 +554,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
> const struct drm_connector_state *old_conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> enum port port = encoder->port;
> u32 tmp, eldv;
> @@ -601,7 +601,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> enum pipe pipe = crtc->pipe;
> enum port port = encoder->port;
> @@ -691,10 +691,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct i915_audio_component *acomp = dev_priv->audio_component;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> enum port port = encoder->port;
> enum pipe pipe = crtc->pipe;
>
> @@ -752,7 +752,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct i915_audio_component *acomp = dev_priv->audio_component;
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum port port = encoder->port;
> enum pipe pipe = crtc->pipe;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..3f6e29f61323 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -297,7 +297,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
>
> static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> unsigned int data_rate = 0;
> enum plane_id plane_id;
>
> @@ -318,7 +318,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> bw_state->data_rate[crtc->pipe] =
> intel_bw_crtc_data_rate(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 42bd02638d32..e7e952f0eac0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1917,10 +1917,10 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> int min_cdclk;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return 0;
>
> min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
> @@ -2043,7 +2043,7 @@ static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> sizeof(state->min_voltage_level));
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (crtc_state->base.enable)
> + if (crtc_state->hw.enable)
> state->min_voltage_level[i] =
> crtc_state->min_voltage_level;
> else
> @@ -2129,7 +2129,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
> vco = dev_priv->skl_preferred_vco_freq;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> continue;
>
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> @@ -2256,11 +2256,11 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> if (IS_ERR(crtc_state))
> return PTR_ERR(crtc_state);
>
> - if (!crtc_state->base.active ||
> - drm_atomic_crtc_needs_modeset(&crtc_state->base))
> + if (!crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> continue;
>
> - crtc_state->base.mode_changed = true;
> + crtc_state->uapi.mode_changed = true;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -2313,7 +2313,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> if (crtc_state &&
> - drm_atomic_crtc_needs_modeset(&crtc_state->base))
> + drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> } else {
> pipe = INVALID_PIPE;
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 1e3a623eaf82..703e5e70b4e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
>
> static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
> {
> - return !crtc_state->base.degamma_lut &&
> - !crtc_state->base.ctm &&
> - crtc_state->base.gamma_lut &&
> - lut_is_legacy(crtc_state->base.gamma_lut);
> + return !crtc_state->hw.degamma_lut &&
> + !crtc_state->hw.ctm &&
> + crtc_state->hw.gamma_lut &&
> + lut_is_legacy(crtc_state->hw.gamma_lut);
> }
>
> /*
> @@ -205,7 +205,7 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
>
> static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * FIXME if there's a gamma LUT after the CSC, we should
> @@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> u16 coeffs[9])
> {
> - const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> const u64 *input;
> u64 temp[9];
> int i;
> @@ -270,11 +270,11 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>
> static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> bool limited_color_range = ilk_csc_limited_range(crtc_state);
>
> - if (crtc_state->base.ctm) {
> + if (crtc_state->hw.ctm) {
> u16 coeff[9];
>
> ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -309,10 +309,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>
> static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (crtc_state->base.ctm) {
> + if (crtc_state->hw.ctm) {
> u16 coeff[9];
>
> ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -338,12 +338,12 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> */
> static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (crtc_state->base.ctm) {
> - const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> + if (crtc_state->hw.ctm) {
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> u16 coeffs[9] = {};
> int i;
>
> @@ -404,7 +404,7 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
> static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
> const struct drm_property_blob *blob)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> int i;
> @@ -435,12 +435,12 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>
> static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> + i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
> }
>
> static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -453,7 +453,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -468,7 +468,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> @@ -478,7 +478,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void skl_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val = 0;
> @@ -524,8 +524,8 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
>
> static void i965_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> i9xx_load_luts(crtc_state);
> @@ -547,8 +547,8 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
>
> static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> i9xx_load_luts(crtc_state);
> @@ -654,9 +654,9 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>
> static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> i9xx_load_luts(crtc_state);
> @@ -677,9 +677,9 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>
> static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> i9xx_load_luts(crtc_state);
> @@ -700,11 +700,11 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
>
> static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> - const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> + const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
> u32 i;
>
> /*
> @@ -739,7 +739,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>
> static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -766,8 +766,8 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
>
> static void glk_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> /*
> * On GLK+ both pipe CSC and degamma LUT are controlled
> @@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
> * the degama LUT so that we don't have to reload
> * it every time the pipe CSC is being enabled.
> */
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
> else
> glk_load_degamma_lut_linear(crtc_state);
> @@ -808,7 +808,7 @@ static void
> icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> const struct drm_color_lut *color)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
>
> @@ -822,8 +822,8 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> static void
> icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
> @@ -854,8 +854,8 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> static void
> icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> const struct drm_color_lut *entry;
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> @@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>
> static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsb *dsb = intel_dsb_get(crtc);
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
>
> switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> @@ -990,9 +990,9 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>
> static void chv_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> cherryview_load_csc_matrix(crtc_state);
>
> @@ -1010,28 +1010,28 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>
> void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> dev_priv->display.load_luts(crtc_state);
> }
>
> void intel_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> dev_priv->display.color_commit(crtc_state);
> }
>
> int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> return dev_priv->display.color_check(crtc_state);
> }
>
> void intel_color_get_config(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (dev_priv->display.read_luts)
> dev_priv->display.read_luts(crtc_state);
> @@ -1055,16 +1055,16 @@ static bool need_plane_update(struct intel_plane *plane,
> static int
> intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_plane *plane;
>
> - if (!new_crtc_state->base.active ||
> - drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
> + if (!new_crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return 0;
>
> if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> @@ -1107,9 +1107,9 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
>
> static int check_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
> int gamma_length, degamma_length;
> u32 gamma_tests, degamma_tests;
>
> @@ -1157,7 +1157,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
> @@ -1176,11 +1176,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> if (crtc_state_is_legacy_gamma(crtc_state))
> return 0;
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
> - if (crtc_state->base.ctm)
> + if (crtc_state->hw.ctm)
> cgm_mode |= CGM_PIPE_MODE_CSC;
> - if (crtc_state->base.gamma_lut)
> + if (crtc_state->hw.gamma_lut)
> cgm_mode |= CGM_PIPE_MODE_GAMMA;
>
> return cgm_mode;
> @@ -1254,7 +1254,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> /*
> @@ -1280,8 +1280,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
> if (!crtc_state->gamma_enable ||
> crtc_state_is_legacy_gamma(crtc_state))
> return GAMMA_MODE_MODE_8BIT;
> - else if (crtc_state->base.gamma_lut &&
> - crtc_state->base.degamma_lut)
> + else if (crtc_state->hw.gamma_lut &&
> + crtc_state->hw.degamma_lut)
> return GAMMA_MODE_MODE_SPLIT;
> else
> return GAMMA_MODE_MODE_10BIT;
> @@ -1295,7 +1295,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
> * CSC comes after the LUT in degamma, RGB->YCbCr,
> * and RGB full->limited range mode.
> */
> - if (crtc_state->base.degamma_lut ||
> + if (crtc_state->hw.degamma_lut ||
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> limited_color_range)
> return 0;
> @@ -1313,13 +1313,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - (crtc_state->base.gamma_lut ||
> - crtc_state->base.degamma_lut) &&
> + (crtc_state->hw.gamma_lut ||
> + crtc_state->hw.degamma_lut) &&
> !crtc_state->c8_planes;
>
> crtc_state->csc_enable =
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> - crtc_state->base.ctm || limited_color_range;
> + crtc_state->hw.ctm || limited_color_range;
>
> crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
>
> @@ -1350,14 +1350,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> /* On GLK+ degamma LUT is controlled by csc_enable */
> crtc_state->csc_enable =
> - crtc_state->base.degamma_lut ||
> + crtc_state->hw.degamma_lut ||
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> - crtc_state->base.ctm || crtc_state->limited_color_range;
> + crtc_state->hw.ctm || crtc_state->limited_color_range;
>
> crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
>
> @@ -1374,14 +1374,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
> {
> u32 gamma_mode = 0;
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> gamma_mode |= PRE_CSC_GAMMA_ENABLE;
>
> - if (crtc_state->base.gamma_lut &&
> + if (crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes)
> gamma_mode |= POST_CSC_GAMMA_ENABLE;
>
> - if (!crtc_state->base.gamma_lut ||
> + if (!crtc_state->hw.gamma_lut ||
> crtc_state_is_legacy_gamma(crtc_state))
> gamma_mode |= GAMMA_MODE_MODE_8BIT;
> else
> @@ -1394,7 +1394,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
> {
> u32 csc_mode = 0;
>
> - if (crtc_state->base.ctm)
> + if (crtc_state->hw.ctm)
> csc_mode |= ICL_CSC_ENABLE;
>
> if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> @@ -1471,7 +1471,7 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!crtc_state->gamma_enable)
> @@ -1580,7 +1580,7 @@ static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
> static struct drm_property_blob *
> i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> @@ -1614,13 +1614,13 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>
> static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> {
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> static struct drm_property_blob *
> i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1661,15 +1661,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> static void i965_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
> + crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
> }
>
> static struct drm_property_blob *
> chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1703,15 +1703,15 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> static void chv_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> + crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
> }
>
> static struct drm_property_blob *
> ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1744,15 +1744,15 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
> + crtc_state->uapi.gamma_lut = ilk_read_lut_10(crtc_state);
> }
>
> static struct drm_property_blob *
> glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int hw_lut_size = ivb_lut_10_size(prec_index);
> enum pipe pipe = crtc->pipe;
> @@ -1790,9 +1790,9 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> static void glk_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> + crtc_state->uapi.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> void intel_color_init(struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index ff6126ea793c..164af1936d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
> {
> pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
>
> - pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> + pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void hsw_crt_get_config(struct intel_encoder *encoder,
> @@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
>
> intel_ddi_get_config(encoder, pipe_config);
>
> - pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> + pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> DRM_MODE_FLAG_NHSYNC |
> DRM_MODE_FLAG_PVSYNC |
> DRM_MODE_FLAG_NVSYNC);
> - pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> + pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>
> - pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
> + pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
> }
>
> /* Note: The caller is required to filter out dpms modes not supported by the
> @@ -161,8 +161,8 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 adpa;
>
> if (INTEL_GEN(dev_priv) >= 5)
> @@ -271,7 +271,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> WARN_ON(!crtc_state->has_pch_encoder);
> @@ -288,7 +288,7 @@ static void hsw_enable_crt(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> WARN_ON(!crtc_state->has_pch_encoder);
> @@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> @@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> @@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3c1e885e0187..052caf2372d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1527,7 +1527,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
> }
>
> static void icl_ddi_clock_get(struct intel_encoder *encoder,
> @@ -1742,7 +1742,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1802,7 +1802,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> bool state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1824,7 +1824,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> static u32
> intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> @@ -1856,9 +1856,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
> BUG();
> }
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DDI_PVSYNC;
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DDI_PHSYNC;
>
> if (cpu_transcoder == TRANSCODER_EDP) {
> @@ -1911,7 +1911,7 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1927,7 +1927,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> static void
> intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1939,7 +1939,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> @@ -2237,7 +2237,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>
> void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = encoder->port;
> @@ -2255,7 +2255,7 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP) {
> @@ -3562,7 +3562,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -3987,7 +3987,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
> WARN_ON(crtc && crtc->active);
>
> intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
> - if (crtc_state && crtc_state->base.active)
> + if (crtc_state && crtc_state->hw.active)
> intel_update_active_dpll(state, crtc, encoder);
> }
>
> @@ -4117,7 +4117,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> u32 temp, flags = 0;
>
> @@ -4135,7 +4135,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> switch (temp & TRANS_DDI_BPC_MASK) {
> case TRANS_DDI_BPC_6:
> @@ -4281,7 +4281,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> int ret;
> @@ -4412,7 +4412,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
>
> WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> if (!crtc_state->hdmi_high_tmds_clock_ratio &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ecb15420b5ca..f555ff6b1f6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -516,7 +516,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> static bool
> needs_modeset(const struct intel_crtc_state *state)
> {
> - return drm_atomic_crtc_needs_modeset(&state->base);
> + return drm_atomic_crtc_needs_modeset(&state->uapi);
> }
>
> /*
> @@ -630,7 +630,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
> const struct intel_crtc_state *crtc_state,
> int target)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> /*
> @@ -666,7 +666,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int err = target;
>
> @@ -724,7 +724,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int err = target;
>
> @@ -780,7 +780,7 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int max_n;
> bool found = false;
> @@ -874,7 +874,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct dpll clock;
> unsigned int bestppm = 1000000;
> @@ -934,7 +934,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> unsigned int best_error_ppm;
> struct dpll clock;
> @@ -1013,7 +1013,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
> * for atomic.
> */
> return crtc->active && crtc->base.primary->state->fb &&
> - crtc->config->base.adjusted_mode.crtc_clock;
> + crtc->config->hw.adjusted_mode.crtc_clock;
> }
>
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> @@ -1067,7 +1067,7 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
> static void
> intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (INTEL_GEN(dev_priv) >= 4) {
> @@ -1526,7 +1526,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
>
> static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -1617,7 +1617,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>
> static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> @@ -1761,7 +1761,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
>
> static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * On i965gm the hardware frame counter reads
> @@ -1781,7 +1781,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state
>
> static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> drm_crtc_set_max_vblank_count(&crtc->base,
> intel_crtc_max_vblank_count(crtc_state));
> @@ -1790,7 +1790,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
>
> static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> @@ -1848,7 +1848,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
>
> static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> @@ -3114,14 +3114,14 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> plane_state->base.visible = visible;
>
> if (visible)
> - crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
> + crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
> else
> - crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
> + crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
> }
>
> static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct drm_plane *plane;
>
> /*
> @@ -3132,7 +3132,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> crtc_state->active_planes = 0;
>
> drm_for_each_plane_mask(plane, &dev_priv->drm,
> - crtc_state->base.plane_mask)
> + crtc_state->uapi.plane_mask)
> crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
> }
>
> @@ -3606,7 +3606,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
>
> static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dspcntr = 0;
>
> @@ -3760,7 +3760,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> return ret;
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> i9xx_plane_has_windowing(plane),
> @@ -3936,7 +3936,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> */
> static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> int i;
> @@ -4131,7 +4131,7 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
>
> u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_ctl = 0;
>
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -4187,7 +4187,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_color_ctl = 0;
>
> if (INTEL_GEN(dev_priv) >= 11)
> @@ -4803,7 +4803,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>
> static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> enum pipe pipe = intel_crtc->pipe;
> i915_reg_t reg;
> @@ -4964,9 +4964,9 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> /* Program iCLKIP clock to the desired frequency */
> static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int clock = crtc_state->base.adjusted_mode.crtc_clock;
> + int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> u32 divsel, phaseinc, auxdiv, phasedir = 0;
> u32 temp;
>
> @@ -5080,7 +5080,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
> static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
> enum pipe pch_transcoder)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> @@ -5123,7 +5123,7 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e
>
> static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> switch (crtc->pipe) {
> @@ -5153,7 +5153,7 @@ static struct intel_encoder *
> intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_connector_state *connector_state;
> const struct drm_connector *connector;
> struct intel_encoder *encoder = NULL;
> @@ -5185,7 +5185,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> static void ironlake_pch_enable(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum pipe pipe = crtc->pipe;
> @@ -5239,7 +5239,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
> if (HAS_PCH_CPT(dev_priv) &&
> intel_crtc_has_dp_encoder(crtc_state)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> i915_reg_t reg = TRANS_DP_CTL(pipe);
> enum port port;
> @@ -5269,7 +5269,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
> static void lpt_pch_enable(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> @@ -5386,10 +5386,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> struct intel_crtc *intel_crtc =
> - to_intel_crtc(crtc_state->base.crtc);
> + to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Src coordinates are already rotated by 270 degrees for
> @@ -5405,7 +5405,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> * Once NV12 is enabled, handle it here while allocating scaler
> * for NV12.
> */
> - if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> + if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
> need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
> return -EINVAL;
> @@ -5477,13 +5477,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> */
> int skl_update_scaler_crtc(struct intel_crtc_state *state)
> {
> - const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
> bool need_scaler = false;
>
> if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> need_scaler = true;
>
> - return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
> + return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
> &state->scaler_state.scaler_id,
> state->pipe_src_w, state->pipe_src_h,
> adjusted_mode->crtc_hdisplay,
> @@ -5583,7 +5583,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
>
> static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const struct intel_crtc_scaler_state *scaler_state =
> @@ -5620,7 +5620,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -5641,7 +5641,7 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> @@ -5677,7 +5677,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>
> void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> @@ -5787,7 +5787,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!old_crtc_state->ips_enabled)
> @@ -5803,7 +5803,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
> * Disable IPS before we program the LUT.
> */
> if (IS_HASWELL(dev_priv) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe) &&
> new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> return true;
> @@ -5814,7 +5814,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
> static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!new_crtc_state->ips_enabled)
> @@ -5830,7 +5830,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
> * Re-enable IPS after the LUT has been programmed.
> */
> if (IS_HASWELL(dev_priv) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe) &&
> new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> return true;
> @@ -5840,7 +5840,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
> * forcibly enable IPS on the first fastset.
> */
> if (new_crtc_state->update_pipe &&
> - old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
> + old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
> return true;
>
> return !old_crtc_state->ips_enabled;
> @@ -5871,10 +5871,10 @@ static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
>
> static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = old_crtc_state->base.state;
> + struct drm_atomic_state *state = old_crtc_state->uapi.state;
> struct intel_crtc_state *pipe_config =
> intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
> crtc);
> @@ -5884,7 +5884,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>
> intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
>
> - if (pipe_config->update_wm_post && pipe_config->base.active)
> + if (pipe_config->update_wm_post && pipe_config->hw.active)
> intel_update_watermarks(crtc);
>
> if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> @@ -5914,10 +5914,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
> static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *pipe_config)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = old_crtc_state->base.state;
> + struct drm_atomic_state *state = old_crtc_state->uapi.state;
> struct drm_plane *primary = crtc->base.primary;
> struct drm_plane_state *old_primary_state =
> drm_atomic_get_old_plane_state(state, primary);
> @@ -5962,7 +5962,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * event which is after the vblank start event, so we need to have a
> * wait-for-vblank between disabling the plane and the pipe.
> */
> - if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
> + if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
> intel_wait_for_vblank(dev_priv, crtc->pipe);
>
> @@ -5974,7 +5974,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * WaCxSRDisabledForSpriteScaling:ivb
> */
> if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
> - old_crtc_state->base.active)
> + old_crtc_state->hw.active)
> intel_wait_for_vblank(dev_priv, crtc->pipe);
>
> /*
> @@ -6269,7 +6269,7 @@ static void intel_encoders_update_pipe(struct intel_crtc *crtc,
>
> static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>
> plane->disable_plane(plane, crtc_state);
> @@ -6278,7 +6278,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6412,7 +6412,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
> @@ -6521,7 +6521,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6537,7 +6537,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6596,7 +6596,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> @@ -6630,7 +6630,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!crtc_state->gmch_pfit.control)
> @@ -6760,14 +6760,14 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
>
> static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_encoder *encoder;
> enum pipe pipe = crtc->pipe;
> u64 mask;
> enum transcoder transcoder = crtc_state->cpu_transcoder;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
> @@ -6777,7 +6777,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
>
> drm_for_each_encoder_mask(encoder, &dev_priv->drm,
> - crtc_state->base.encoder_mask) {
> + crtc_state->uapi.encoder_mask) {
> struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
>
> mask |= BIT_ULL(intel_encoder->power_domain);
> @@ -6795,7 +6795,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> static u64
> modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain domain;
> u64 domains, new_domains, old_domains;
> @@ -6824,7 +6824,7 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6880,7 +6880,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
> @@ -6890,7 +6890,7 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6940,7 +6940,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!old_crtc_state->gmch_pfit.control)
> @@ -6956,7 +6956,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -7124,8 +7124,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> if (!crtc_state)
> return;
>
> - I915_STATE_WARN(!crtc_state->base.active,
> - "connector is active, but attached crtc isn't\n");
> + I915_STATE_WARN(!crtc_state->hw.active,
> + "connector is active, but attached crtc isn't\n");
>
> if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
> return;
> @@ -7136,8 +7136,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
> "attached encoder crtc differs from connector crtc\n");
> } else {
> - I915_STATE_WARN(crtc_state && crtc_state->base.active,
> - "attached crtc is active, but connector isn't\n");
> + I915_STATE_WARN(crtc_state && crtc_state->hw.active,
> + "attached crtc is active, but connector isn't\n");
> I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
> "best encoder set without crtc!\n");
> }
> @@ -7145,7 +7145,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>
> static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->base.enable && crtc_state->has_pch_encoder)
> + if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
> return crtc_state->fdi_lanes;
>
> return 0;
> @@ -7155,7 +7155,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct intel_crtc *other_crtc;
> struct intel_crtc_state *other_crtc_state;
>
> @@ -7228,7 +7228,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = intel_crtc->base.dev;
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int lane, link_bw, fdi_dotclock, ret;
> bool needs_recompute = false;
>
> @@ -7274,7 +7274,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* IPS only exists on ULT machines and is tied to pipe A. */
> @@ -7304,9 +7304,9 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
>
> if (!hsw_crtc_state_ips_capable(crtc_state))
> return false;
> @@ -7345,7 +7345,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
> {
> u32 pixel_rate;
>
> - pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
> + pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
>
> /*
> * We only use IF-ID interlacing. If we ever use
> @@ -7378,12 +7378,12 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
>
> static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (HAS_GMCH(dev_priv))
> /* FIXME calculate proper pipe pixel rate for GMCH pfit */
> crtc_state->pixel_rate =
> - crtc_state->base.adjusted_mode.crtc_clock;
> + crtc_state->hw.adjusted_mode.crtc_clock;
> else
> crtc_state->pixel_rate =
> ilk_pipe_pixel_rate(crtc_state);
> @@ -7393,7 +7393,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int clock_limit = dev_priv->max_dotclk_freq;
>
> if (INTEL_GEN(dev_priv) < 4) {
> @@ -7419,7 +7419,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>
> if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
> - pipe_config->base.ctm) {
> + pipe_config->hw.ctm) {
> /*
> * There is only one pipe CSC unit per pipe, and we need that
> * for output conversion from RGB->YCBCR. So if CTM is already
> @@ -7613,7 +7613,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
> static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> const struct intel_link_m_n *m_n)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7640,7 +7640,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
> const struct intel_link_m_n *m_n,
> const struct intel_link_m_n *m2_n2)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> enum transcoder transcoder = crtc_state->cpu_transcoder;
> @@ -7953,7 +7953,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
> if (!pipe_config)
> return -ENOMEM;
>
> - pipe_config->base.crtc = &crtc->base;
> + pipe_config->uapi.crtc = &crtc->base;
> pipe_config->pixel_multiplier = 1;
> pipe_config->dpll = *dpll;
>
> @@ -8113,11 +8113,11 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>
> static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> @@ -8175,7 +8175,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -8189,7 +8189,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>
> static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (IS_GEN(dev_priv, 2))
> @@ -8211,39 +8211,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
> u32 tmp;
>
> tmp = I915_READ(HTOTAL(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = I915_READ(HBLANK(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hblank_start =
> + pipe_config->hw.adjusted_mode.crtc_hblank_start =
> (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_hblank_end =
> + pipe_config->hw.adjusted_mode.crtc_hblank_end =
> ((tmp >> 16) & 0xffff) + 1;
> }
> tmp = I915_READ(HSYNC(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
>
> tmp = I915_READ(VTOTAL(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = I915_READ(VBLANK(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vblank_start =
> + pipe_config->hw.adjusted_mode.crtc_vblank_start =
> (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vblank_end =
> + pipe_config->hw.adjusted_mode.crtc_vblank_end =
> ((tmp >> 16) & 0xffff) + 1;
> }
> tmp = I915_READ(VSYNC(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
>
> if (intel_pipe_is_interlaced(pipe_config)) {
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> - pipe_config->base.adjusted_mode.crtc_vtotal += 1;
> - pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> + pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
> + pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
> }
> }
>
> @@ -8258,27 +8258,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
>
> - pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
> - pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
> + pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
> + pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
> }
>
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config)
> {
> - mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
> - mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
> - mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
> - mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
> + mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> + mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> + mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> + mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
>
> - mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
> - mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
> - mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
> - mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
> + mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> + mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> + mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> + mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
>
> - mode->flags = pipe_config->base.adjusted_mode.flags;
> + mode->flags = pipe_config->hw.adjusted_mode.flags;
> mode->type = DRM_MODE_TYPE_DRIVER;
>
> - mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
> + mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
>
> mode->hsync = drm_mode_hsync(mode);
> mode->vrefresh = drm_mode_vrefresh(mode);
> @@ -8287,7 +8287,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>
> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 pipeconf;
>
> @@ -8324,7 +8324,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> }
> }
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> if (INTEL_GEN(dev_priv) < 4 ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> @@ -8733,7 +8733,7 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
>
> static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -8856,7 +8856,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> * but in case the pipe is enabled w/o any ports we need a sane
> * default.
> */
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> pipe_config->port_clock / pipe_config->pixel_multiplier;
>
> ret = true;
> @@ -9371,7 +9371,7 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
>
> static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -9399,7 +9399,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> if (crtc_state->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -9425,7 +9425,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>
> static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 val = 0;
> @@ -9433,7 +9433,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
> if (IS_HASWELL(dev_priv) && crtc_state->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -9448,7 +9448,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
>
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val = 0;
>
> @@ -9634,7 +9634,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> const struct intel_limit *limit;
> int refclk = 120000;
>
> @@ -10059,7 +10059,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
>
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> INTEL_GEN(dev_priv) >= 11) {
> @@ -10630,7 +10630,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> true, true);
> @@ -10817,7 +10817,7 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
>
> static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 cntl = 0;
>
> @@ -11229,12 +11229,12 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
> goto fail;
> }
>
> - crtc_state->base.active = crtc_state->base.enable = true;
> + crtc_state->uapi.active = crtc_state->uapi.enable = true;
>
> if (!mode)
> mode = &load_detect_mode;
>
> - ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
> + ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, mode);
> if (ret)
> goto fail;
>
> @@ -11442,7 +11442,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
> * we may need some idea for the dotclock anyway.
> * Calculate one based on the FDI configuration.
> */
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> &pipe_config->fdi_m_n);
> }
> @@ -11472,7 +11472,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> return NULL;
> }
>
> - crtc_state->base.crtc = &crtc->base;
> + crtc_state->uapi.crtc = &crtc->base;
>
> if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
> kfree(crtc_state);
> @@ -11543,12 +11543,12 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> const struct intel_plane_state *old_plane_state,
> struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> bool mode_changed = needs_modeset(crtc_state);
> - bool was_crtc_enabled = old_crtc_state->base.active;
> - bool is_crtc_enabled = crtc_state->base.active;
> + bool was_crtc_enabled = old_crtc_state->hw.active;
> + bool is_crtc_enabled = crtc_state->hw.active;
> bool turn_off, turn_on, visible, was_visible;
> int ret;
>
> @@ -11715,9 +11715,9 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
>
> static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_plane *plane, *linked;
> struct intel_plane_state *plane_state;
> int i;
> @@ -11787,9 +11787,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>
> static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
>
> @@ -11807,10 +11807,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
> bool mode_changed = needs_modeset(crtc_state);
>
> if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
> - mode_changed && !crtc_state->base.active)
> + mode_changed && !crtc_state->hw.active)
> crtc_state->update_wm_post = true;
>
> - if (mode_changed && crtc_state->base.enable &&
> + if (mode_changed && crtc_state->hw.enable &&
> dev_priv->display.crtc_compute_clock &&
> !WARN_ON(crtc_state->shared_dpll)) {
> ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> @@ -11823,10 +11823,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
> * when C8 planes are getting enabled/disabled.
> */
> if (c8_planes_changed(crtc_state))
> - crtc_state->base.color_mgmt_changed = true;
> + crtc_state->uapi.color_mgmt_changed = true;
>
> if (mode_changed || crtc_state->update_pipe ||
> - crtc_state->base.color_mgmt_changed) {
> + crtc_state->uapi.color_mgmt_changed) {
> ret = intel_color_check(crtc_state);
> if (ret)
> return ret;
> @@ -11948,7 +11948,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> int bpp, i;
> @@ -12101,7 +12101,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state,
> const char *context)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct intel_plane_state *plane_state;
> struct intel_plane *plane;
> @@ -12110,14 +12110,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
> crtc->base.base.id, crtc->base.name,
> - yesno(pipe_config->base.enable), context);
> + yesno(pipe_config->hw.enable), context);
>
> - if (!pipe_config->base.enable)
> + if (!pipe_config->hw.enable)
> goto dump_planes;
>
> snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
> - yesno(pipe_config->base.active),
> + yesno(pipe_config->hw.active),
> buf, pipe_config->output_types,
> output_formats(pipe_config->output_format));
>
> @@ -12157,10 +12157,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
>
> DRM_DEBUG_KMS("requested mode:\n");
> - drm_mode_debug_printmodeline(&pipe_config->base.mode);
> + drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> DRM_DEBUG_KMS("adjusted mode:\n");
> - drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
> - intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
> + drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> + intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
> DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
> pipe_config->port_clock,
> pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> @@ -12278,7 +12278,7 @@ static int
> clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> struct intel_crtc_state *saved_state;
>
> saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
> @@ -12301,9 +12301,10 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> saved_state->wm = crtc_state->wm;
>
> /* Keep base drm_crtc_state intact, only clear our extended struct */
> - BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> - memcpy(&crtc_state->base + 1, &saved_state->base + 1,
> - sizeof(*crtc_state) - sizeof(crtc_state->base));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
> + memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
> + sizeof(*crtc_state) - sizeof(crtc_state->uapi));
>
> kfree(saved_state);
> return 0;
> @@ -12312,8 +12313,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> static int
> intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct intel_encoder *encoder;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> @@ -12333,13 +12334,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> * positive or negative polarity is requested, treat this as meaning
> * negative polarity.
> */
> - if (!(pipe_config->base.adjusted_mode.flags &
> + if (!(pipe_config->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (!(pipe_config->base.adjusted_mode.flags &
> + if (!(pipe_config->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>
> ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
> pipe_config);
> @@ -12356,7 +12357,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> * computation to clearly distinguish it from the adjusted mode, which
> * can be changed by the connectors in the below retry loop.
> */
> - drm_mode_get_hv_timing(&pipe_config->base.mode,
> + drm_mode_get_hv_timing(&pipe_config->hw.mode,
> &pipe_config->pipe_src_w,
> &pipe_config->pipe_src_h);
>
> @@ -12389,7 +12390,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> pipe_config->pixel_multiplier = 1;
>
> /* Fill in default crtc timings, allow encoders to overwrite them. */
> - drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
> + drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
> CRTC_STEREO_DOUBLE);
>
> /* Pass our mode to the connectors and the CRTC to give them a chance to
> @@ -12414,7 +12415,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> /* Set default port clock if not overwritten by the encoder. Needs to be
> * done afterwards in case the encoder adjusts the mode. */
> if (!pipe_config->port_clock)
> - pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
> + pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
> * pipe_config->pixel_multiplier;
>
> ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
> @@ -12458,7 +12459,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
>
> diff = abs(clock1 - clock2);
>
> - if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
> + if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 101)
> return true;
>
> return false;
> @@ -12578,12 +12579,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> bool fastset)
> {
> - struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
> bool ret = true;
> u32 bp_gamma = 0;
> bool fixup_inherited = fastset &&
> - (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> - !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
> + (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> + !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
>
> if (fixup_inherited && !fastboot_enabled(dev_priv)) {
> DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
> @@ -12772,19 +12773,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(output_types);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
>
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(output_format);
> @@ -12800,17 +12801,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_INTERLACE);
>
> if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PVSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NVSYNC);
> }
>
> @@ -12849,7 +12850,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
> if (bp_gamma)
> - PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
> + PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, uapi.gamma_lut, bp_gamma);
>
> }
>
> @@ -12894,7 +12895,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
>
> PIPE_CONF_CHECK_I(min_voltage_level);
> @@ -12925,7 +12926,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
> if (pipe_config->has_pch_encoder) {
> int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> &pipe_config->fdi_m_n);
> - int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
> + int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
>
> /*
> * FDI already provided one idea for the dotclock.
> @@ -12953,7 +12954,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
> const enum pipe pipe = crtc->pipe;
> int plane, level, max_level = ilk_wm_max_level(dev_priv);
>
> - if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> + if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
> return;
>
> hw = kzalloc(sizeof(*hw), GFP_KERNEL);
> @@ -13162,12 +13163,12 @@ verify_crtc_state(struct intel_crtc *crtc,
> struct drm_atomic_state *state;
> bool active;
>
> - state = old_crtc_state->base.state;
> - __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
> + state = old_crtc_state->uapi.state;
> + __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
> pipe_config = old_crtc_state;
> memset(pipe_config, 0, sizeof(*pipe_config));
> - pipe_config->base.crtc = &crtc->base;
> - pipe_config->base.state = state;
> + pipe_config->uapi.crtc = &crtc->base;
> + pipe_config->uapi.state = state;
>
> DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
>
> @@ -13175,23 +13176,26 @@ verify_crtc_state(struct intel_crtc *crtc,
>
> /* we keep both pipes enabled on 830 */
> if (IS_I830(dev_priv))
> - active = new_crtc_state->base.active;
> + active = new_crtc_state->hw.active;
>
> - I915_STATE_WARN(new_crtc_state->base.active != active,
> - "crtc active state doesn't match with hw state "
> - "(expected %i, found %i)\n", new_crtc_state->base.active, active);
> + I915_STATE_WARN(new_crtc_state->hw.active != active,
> + "crtc active state doesn't match with hw state "
> + "(expected %i, found %i)\n",
> + new_crtc_state->hw.active, active);
>
> - I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
> - "transitional active state does not match atomic hw state "
> - "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
> + I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
> + "transitional active state does not match atomic hw state "
> + "(expected %i, found %i)\n",
> + new_crtc_state->hw.active, crtc->active);
>
> for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> enum pipe pipe;
>
> active = encoder->get_hw_state(encoder, &pipe);
> - I915_STATE_WARN(active != new_crtc_state->base.active,
> - "[ENCODER:%i] active %i with crtc active %i\n",
> - encoder->base.base.id, active, new_crtc_state->base.active);
> + I915_STATE_WARN(active != new_crtc_state->hw.active,
> + "[ENCODER:%i] active %i with crtc active %i\n",
> + encoder->base.base.id, active,
> + new_crtc_state->hw.active);
>
> I915_STATE_WARN(active && crtc->pipe != pipe,
> "Encoder connected to wrong pipe %c\n",
> @@ -13203,7 +13207,7 @@ verify_crtc_state(struct intel_crtc *crtc,
>
> intel_crtc_compute_pixel_rate(pipe_config);
>
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.active)
> return;
>
> intel_pipe_config_sanity_check(dev_priv, pipe_config);
> @@ -13265,7 +13269,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
>
> crtc_mask = drm_crtc_mask(&crtc->base);
>
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
> pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> @@ -13343,7 +13347,7 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
>
> static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /*
> @@ -13374,7 +13378,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
> * answer that's slightly in the future.
> */
> if (IS_GEN(dev_priv, 2)) {
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> int vtotal;
>
> vtotal = adjusted_mode->crtc_vtotal;
> @@ -13424,7 +13428,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>
> /* look at all crtc's that are going to be enabled in during modeset */
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> !needs_modeset(crtc_state))
> continue;
>
> @@ -13449,7 +13453,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>
> crtc_state->hsw_workaround_pipe = INVALID_PIPE;
>
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> needs_modeset(crtc_state))
> continue;
>
> @@ -13492,12 +13496,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> state->active_pipes |= BIT(crtc->pipe);
> else
> state->active_pipes &= ~BIT(crtc->pipe);
>
> - if (old_crtc_state->base.active != new_crtc_state->base.active)
> + if (old_crtc_state->hw.active != new_crtc_state->hw.active)
> state->active_pipe_changes |= BIT(crtc->pipe);
> }
>
> @@ -13536,7 +13540,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> return;
>
> - new_crtc_state->base.mode_changed = false;
> + new_crtc_state->uapi.mode_changed = false;
> new_crtc_state->update_pipe = true;
>
> /*
> @@ -13571,9 +13575,9 @@ static int intel_atomic_check(struct drm_device *dev,
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->base.mode.private_flags !=
> - old_crtc_state->base.mode.private_flags)
> - new_crtc_state->base.mode_changed = true;
> + if (new_crtc_state->hw.mode.private_flags !=
> + old_crtc_state->hw.mode.private_flags)
> + new_crtc_state->uapi.mode_changed = true;
> }
>
> ret = drm_atomic_helper_check_modeset(dev, &state->base);
> @@ -13585,7 +13589,7 @@ static int intel_atomic_check(struct drm_device *dev,
> if (!needs_modeset(new_crtc_state))
> continue;
>
> - if (!new_crtc_state->base.enable) {
> + if (!new_crtc_state->uapi.enable) {
> any_ms = true;
> continue;
> }
> @@ -13693,11 +13697,11 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> - crtc->base.mode = new_crtc_state->base.mode;
> + crtc->base.mode = new_crtc_state->hw.mode;
>
> /*
> * Update pipe size and adjust fitter if needed: the reason for this is
> @@ -13738,7 +13742,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> * CRTC was enabled.
> */
> if (!modeset) {
> - if (new_crtc_state->base.color_mgmt_changed ||
> + if (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe)
> intel_color_commit(new_crtc_state);
>
> @@ -13805,7 +13809,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> * of enabling them on the CRTC's first fastset.
> */
> if (new_crtc_state->update_pipe && !modeset &&
> - old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> + old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
> intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> }
>
> @@ -13837,11 +13841,10 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> intel_check_pch_fifo_underruns(dev_priv);
>
> /* FIXME unify this for all platforms */
> - if (!new_crtc_state->base.active &&
> + if (!new_crtc_state->hw.active &&
> !HAS_GMCH(dev_priv) &&
> dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.initial_watermarks(state, new_crtc_state);
> }
>
> static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> @@ -13864,7 +13867,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
>
> intel_pre_plane_update(old_crtc_state, new_crtc_state);
>
> - if (old_crtc_state->base.active)
> + if (old_crtc_state->hw.active)
> intel_old_crtc_state_disables(state,
> old_crtc_state,
> new_crtc_state,
> @@ -13879,7 +13882,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
> int i;
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.active)
> continue;
>
> intel_update_crtc(crtc, state, old_crtc_state,
> @@ -13902,7 +13905,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
> /* ignore allocations for crtc's that have been turned off. */
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> entries[i] = old_crtc_state->wm.skl.ddb;
>
> /* If 2nd DBuf slice required, enable it here */
> @@ -13924,7 +13927,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>
> pipe = crtc->pipe;
>
> - if (updated & cmask || !new_crtc_state->base.active)
> + if (updated & cmask || !new_crtc_state->hw.active)
> continue;
>
> if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> @@ -13943,7 +13946,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> */
> if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
> &old_crtc_state->wm.skl.ddb) &&
> - !new_crtc_state->base.active_changed &&
> + !new_crtc_state->uapi.active_changed &&
> state->wm_results.dirty_pipes != updated)
> vbl_wait = true;
>
> @@ -14076,12 +14079,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> bool modeset = needs_modeset(new_crtc_state);
>
> /* Complete events for now disable pipes here. */
> - if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
> + if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
> spin_lock_irq(&dev->event_lock);
> - drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
> + drm_crtc_send_vblank_event(&crtc->base,
> + new_crtc_state->uapi.event);
> spin_unlock_irq(&dev->event_lock);
>
> - new_crtc_state->base.event = NULL;
> + new_crtc_state->uapi.event = NULL;
> }
> }
>
> @@ -14112,9 +14116,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - if (new_crtc_state->base.active &&
> + if (new_crtc_state->hw.active &&
> !needs_modeset(new_crtc_state) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe))
> intel_color_load_luts(new_crtc_state);
> }
> @@ -14573,16 +14577,16 @@ int
> skl_max_scale(const struct intel_crtc_state *crtc_state,
> const struct drm_format_info *format)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int max_scale;
> int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return DRM_PLANE_HELPER_NO_SCALING;
>
> - crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> - max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
> + crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
> + max_dotclk = to_intel_atomic_state(crtc_state->uapi.state)->cdclk.logical.cdclk;
>
> if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> max_dotclk *= 2;
> @@ -14715,7 +14719,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
> * When crtc is inactive or there is a modeset pending,
> * wait for it to complete in the slowpath
> */
> - if (!crtc_state->base.active || needs_modeset(crtc_state) ||
> + if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
> crtc_state->update_pipe)
> goto slow;
>
> @@ -14809,7 +14813,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
> mutex_unlock(&dev_priv->drm.struct_mutex);
> out_free:
> if (new_crtc_state)
> - intel_crtc_destroy_state(crtc, &new_crtc_state->base);
> + intel_crtc_destroy_state(crtc, &new_crtc_state->uapi);
> if (ret)
> intel_plane_destroy_state(plane, new_plane_state);
> else
> @@ -15135,7 +15139,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> ret = -ENOMEM;
> goto fail;
> }
> - __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
> + __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
> intel_crtc->config = crtc_state;
>
> primary = intel_primary_plane_create(dev_priv, pipe);
> @@ -16490,7 +16494,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
> I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
> }
>
> - if (crtc_state->base.active) {
> + if (crtc_state->hw.active) {
> struct intel_plane *plane;
>
> /* Disable everything but the primary plane */
> @@ -16515,10 +16519,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>
> /* Adjust the state of the output pipe according to whether we
> * have active connectors/encoders. */
> - if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
> + if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
> intel_crtc_disable_noatomic(&crtc->base, ctx);
>
> - if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
> + if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
> /*
> * We start out with underrun reporting disabled to avoid races.
> * For correct bookkeeping mark this on active crtcs.
> @@ -16549,7 +16553,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>
> static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
> @@ -16562,7 +16566,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> * road.
> */
> return IS_GEN(dev_priv, 6) &&
> - crtc_state->base.active &&
> + crtc_state->hw.active &&
> crtc_state->shared_dpll &&
> crtc_state->port_clock == 0;
> }
> @@ -16579,7 +16583,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> * encoder is active and trying to read from a pipe) and the
> * pipe itself being active. */
> bool has_active_crtc = crtc_state &&
> - crtc_state->base.active;
> + crtc_state->hw.active;
>
> if (crtc_state && has_bogus_dpll_config(crtc_state)) {
> DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
> @@ -16683,22 +16687,22 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> memset(crtc_state, 0, sizeof(*crtc_state));
> - __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
> + __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
>
> - crtc_state->base.active = crtc_state->base.enable =
> + crtc_state->hw.active = crtc_state->hw.enable =
> dev_priv->display.get_pipe_config(crtc, crtc_state);
>
> - crtc->base.enabled = crtc_state->base.enable;
> - crtc->active = crtc_state->base.active;
> + crtc->base.enabled = crtc_state->hw.enable;
> + crtc->active = crtc_state->hw.active;
>
> - if (crtc_state->base.active)
> + if (crtc_state->hw.active)
> dev_priv->active_pipes |= BIT(crtc->pipe);
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
> crtc->base.base.id, crtc->base.name,
> - enableddisabled(crtc_state->base.active));
> + enableddisabled(crtc_state->hw.active));
> }
>
> readout_plane_state(dev_priv);
> @@ -16720,7 +16724,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - if (crtc_state->base.active &&
> + if (crtc_state->hw.active &&
> crtc_state->shared_dpll == pll)
> pll->state.crtc_mask |= 1 << crtc->pipe;
> }
> @@ -16754,21 +16758,24 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (connector->get_hw_state(connector)) {
> - connector->base.dpms = DRM_MODE_DPMS_ON;
> + struct intel_crtc_state *crtc_state = NULL;
>
> + connector->base.dpms = DRM_MODE_DPMS_ON;
> encoder = connector->encoder;
> connector->base.encoder = &encoder->base;
>
> - if (encoder->base.crtc &&
> - encoder->base.crtc->state->active) {
> + if (encoder->base.crtc)
> + crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
> +
> + if (crtc_state && crtc_state->hw.active) {
> /*
> * This has to be done during hardware readout
> * because anything calling .crtc_disable may
> * rely on the connector_mask being accurate.
> */
> - encoder->base.crtc->state->connector_mask |=
> + crtc_state->uapi.connector_mask |=
> drm_connector_mask(&connector->base);
> - encoder->base.crtc->state->encoder_mask |=
> + crtc_state->uapi.encoder_mask |=
> drm_encoder_mask(&encoder->base);
> }
>
> @@ -16791,11 +16798,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> int min_cdclk = 0;
>
> memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
> - if (crtc_state->base.active) {
> + if (crtc_state->hw.active) {
> intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
> crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
> crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
> - intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
> + intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
> + crtc_state);
> WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
>
> /*
> @@ -16807,7 +16815,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> * set a flag to indicate that a full recalculation is
> * needed on the next commit.
> */
> - crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
> + crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
>
> intel_crtc_compute_pixel_rate(crtc_state);
>
> @@ -16818,7 +16826,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> }
>
> drm_calc_timestamping_constants(&crtc->base,
> - &crtc_state->base.adjusted_mode);
> + &crtc_state->hw.adjusted_mode);
> update_scanline_offset(crtc_state);
> }
>
> @@ -16989,7 +16997,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>
> drm_crtc_vblank_reset(&crtc->base);
>
> - if (crtc_state->base.active)
> + if (crtc_state->hw.active)
> intel_crtc_vblank_on(crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index bc2cf4bec0e8..44a1c331d6b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -443,10 +443,10 @@ enum phy_fia {
> #define intel_atomic_crtc_state_for_each_plane_state( \
> plane, plane_state, \
> crtc_state) \
> - for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> - ((crtc_state)->base.plane_mask)) \
> + for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
> + ((crtc_state)->uapi.plane_mask)) \
> for_each_if ((plane_state = \
> - to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> + to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
>
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 526423437f63..0ee69e8f0942 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -749,7 +749,31 @@ enum intel_output_format {
> };
>
> struct intel_crtc_state {
> - struct drm_crtc_state base;
> + union {
> + /*
> + * uapi (drm) state. This is the software state shown to userspace.
> + * In particular, the following members are used for bookkeeping:
> + * - crtc
> + * - state
> + * - *_changed
> + * - event
> + * - commit
> + * - mode_blob
> + */
> + struct drm_crtc_state uapi;
> +
> + /*
> + * actual hardware state, the state we program to the hardware.
> + * The following members are used to verify the hardware state:
> + * - enable
> + * - active
> + * - mode / adjusted_mode
> + * - color property blobs.
> + *
> + * During initial hw readout, they need to be copied to uapi.
> + */
> + struct drm_crtc_state hw;
> + };
>
> /**
> * quirks - bitfield with hw state readout quirks
> @@ -1093,7 +1117,7 @@ struct cxsr_latency {
>
> #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
> #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
> -#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
> +#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
> #define to_intel_connector(x) container_of(x, struct intel_connector, base)
> #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
> #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1aa39e92f0df..4297738655c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1967,7 +1967,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> const struct link_config_limits *limits)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int bpp, clock, lane_count;
> int mode_rate, link_clock, link_avail;
>
> @@ -2021,7 +2021,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u8 dsc_max_bpc;
> int pipe_bpp;
> int ret;
> @@ -2132,7 +2132,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct link_config_limits limits;
> int common_len;
> @@ -2220,8 +2220,8 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> {
> const struct drm_display_info *info = &connector->display_info;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + &crtc_state->hw.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> int ret;
>
> if (!drm_mode_is_420_only(info, adjusted_mode) ||
> @@ -2249,7 +2249,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
> const struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Our YCbCr output is always limited range.
> @@ -2282,11 +2282,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
> enum port port = encoder->port;
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> @@ -2400,8 +2400,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
> pipe_config->lane_count,
> @@ -2998,7 +2998,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
> static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
> const struct intel_crtc_state *pipe_config)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3038,7 +3038,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
> static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
> const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3198,7 +3198,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> u32 tmp, flags = 0;
> enum port port = encoder->port;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>
> if (encoder->type == INTEL_OUTPUT_EDP)
> pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
> @@ -3233,7 +3233,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
> }
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
> @@ -3250,7 +3250,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> pipe_config->port_clock = 270000;
> }
>
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> intel_dotclock_calculate(pipe_config->port_clock,
> &pipe_config->dp_m_n);
>
> @@ -3465,7 +3465,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> u32 dp_reg = I915_READ(intel_dp->output_reg);
> enum pipe pipe = crtc->pipe;
> intel_wakeref_t wakeref;
> @@ -3598,7 +3598,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> @@ -4120,7 +4120,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum port port = encoder->port;
> u32 DP = intel_dp->DP;
>
> @@ -4881,7 +4881,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
>
> WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> if (conn_state->commit &&
> @@ -6700,7 +6700,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> int refresh_rate)
> {
> struct intel_dp *intel_dp = dev_priv->drrs.dp;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>
> if (refresh_rate <= 0) {
> @@ -6733,7 +6733,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (!crtc_state->base.active) {
> + if (!crtc_state->hw.active) {
> DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2203be28ea01..cecb7ba5b482 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -42,13 +42,13 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state,
> struct link_config_limits *limits)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> struct intel_dp *intel_dp = &intel_mst->primary->dp;
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> void *port = connector->port;
> bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> DP_DPCD_QUIRK_CONSTANT_N);
> @@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> void *port = connector->port;
> struct link_config_limits limits;
> int ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 556d1b30f06a..704f38681c4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> @@ -783,7 +783,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> unsigned int lane_mask =
> @@ -864,7 +864,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> int data, i, stagger;
> @@ -953,7 +953,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
> u32 val;
>
> vlv_dpio_get(dev_priv);
> @@ -1016,7 +1016,7 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
>
> @@ -1046,7 +1046,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -1075,7 +1075,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 5e9e84c94a15..c2603aa56767 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -136,7 +136,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> */
> void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> @@ -163,7 +163,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
> */
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -208,7 +208,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> */
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -825,7 +825,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
> static struct intel_shared_dpll *
> hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct intel_shared_dpll *pll;
> enum intel_dpll_id pll_id;
> int clock = crtc_state->port_clock;
> @@ -1734,7 +1734,7 @@ static bool
> bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> struct bxt_clk_div *clk_div)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct dpll best_clock;
>
> /* Calculate HDMI div */
> @@ -2257,7 +2257,7 @@ static bool
> cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *wrpll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 afe_clock = crtc_state->port_clock * 5;
> u32 ref_clock;
> u32 dco_min = 7998000;
> @@ -2535,7 +2535,7 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
> static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> const struct icl_combo_pll_params *params =
> dev_priv->cdclk.hw.ref == 24000 ?
> icl_dp_combo_pll_24MHz_values :
> @@ -2557,7 +2557,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> switch (dev_priv->cdclk.hw.ref) {
> @@ -2594,7 +2594,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder,
> struct intel_dpll_hw_state *pll_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
> @@ -2726,7 +2726,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> struct intel_dpll_hw_state *pll_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int refclk_khz = dev_priv->cdclk.hw.ref;
> int clock = crtc_state->port_clock;
> u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 9827f99491d1..28770c5765ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void intel_disable_dvo(struct intel_encoder *encoder,
> @@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
> u32 temp = I915_READ(dvo_reg);
>
> intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> - &pipe_config->base.mode,
> - &pipe_config->base.adjusted_mode);
> + &pipe_config->hw.mode,
> + &pipe_config->hw.adjusted_mode);
>
> I915_WRITE(dvo_reg, temp | DVO_ENABLE);
> I915_READ(dvo_reg);
> @@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> const struct drm_display_mode *fixed_mode =
> intel_dvo->attached_connector->panel.fixed_mode;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> /*
> * If we have timings from the BIOS for the panel, put them in
> @@ -277,8 +277,8 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> enum pipe pipe = crtc->pipe;
> u32 dvo_val;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 3111ecaeabd0..c6cc3775f3b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> cache->vma = NULL;
> cache->flags = 0;
>
> - cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
> + cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0a6846c5ba95..fd75016bd1e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -279,7 +279,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -315,7 +315,7 @@ static void ibx_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -334,7 +334,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
> u32 val = I915_READ(reg);
>
> @@ -356,7 +356,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -395,7 +395,7 @@ static void cpt_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -414,7 +414,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
>
> if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -432,7 +432,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -468,7 +468,7 @@ static void vlv_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -487,7 +487,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
>
> if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -700,7 +700,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
> {
> struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> int ret;
>
> @@ -796,7 +796,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
>
> ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
> conn_state->connector,
> - &crtc_state->base.adjusted_mode);
> + &crtc_state->hw.adjusted_mode);
> if (WARN_ON(ret))
> return false;
>
> @@ -957,7 +957,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg;
>
> if ((crtc_state->infoframes.enable &
> @@ -982,7 +982,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg;
>
> if ((crtc_state->infoframes.enable &
> @@ -1019,7 +1019,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
>
> /* Enable default_phase whenever the display mode is suitably aligned */
> if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> - &crtc_state->base.adjusted_mode))
> + &crtc_state->hw.adjusted_mode))
> crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
> }
>
> @@ -1029,7 +1029,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
> struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> @@ -1088,7 +1088,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> @@ -1137,7 +1137,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> @@ -1733,9 +1733,9 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 hdmi_val;
>
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> @@ -1826,7 +1826,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
> tmp & HDMI_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
> dotclock = pipe_config->port_clock * 2 / 3;
> @@ -1836,7 +1836,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>
> pipe_config->lane_count = 4;
>
> @@ -1857,7 +1857,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>
> WARN_ON(!pipe_config->has_hdmi_sink);
> DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
> @@ -1943,7 +1943,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> enum pipe pipe = crtc->pipe;
> u32 temp;
> @@ -2007,7 +2007,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> struct intel_digital_port *intel_dig_port =
> hdmi_to_dig_port(intel_hdmi);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> u32 temp;
>
> temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -2207,12 +2207,12 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> int bpc)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> - struct drm_atomic_state *state = crtc_state->base.state;
> + to_i915(crtc_state->uapi.crtc->dev);
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct drm_connector_state *connector_state;
> struct drm_connector *connector;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int i;
>
> if (HAS_GMCH(dev_priv))
> @@ -2237,7 +2237,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> for_each_new_connector_in_state(state, connector, connector_state, i) {
> const struct drm_display_info *info = &connector->display_info;
>
> - if (connector_state->crtc != crtc_state->base.crtc)
> + if (connector_state->crtc != crtc_state->uapi.crtc)
> continue;
>
> if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> @@ -2278,7 +2278,7 @@ static bool
> intel_hdmi_ycbcr420_config(struct drm_connector *connector,
> struct intel_crtc_state *config)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc);
>
> if (!connector->ycbcr_420_allowed) {
> DRM_ERROR("Platform doesn't support YCBCR420 output\n");
> @@ -2333,7 +2333,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int bpc, clock = adjusted_mode->crtc_clock;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> @@ -2375,7 +2375,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
> const struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Our YCbCr output is always limited range.
> @@ -2403,7 +2403,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
> struct intel_digital_connector_state *intel_conn_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index f8f1308643a9..5145ff8b962b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
> {
> const struct drm_display_info *info = &connector->display_info;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> if (drm_mode_is_420_only(info, adjusted_mode) &&
> connector->ycbcr_420_allowed) {
> @@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> struct intel_lspcon *lspcon = &dig_port->lspcon;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> if (!lspcon->active) {
> DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 13841d7c455b..ca4ebb0f2230 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_PVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if (INTEL_GEN(dev_priv) < 5)
> pipe_config->gmch_pfit.lvds_border_bits =
> @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
> }
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -230,8 +230,8 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
> {
> struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> u32 temp;
>
> @@ -392,8 +392,8 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> to_lvds_encoder(&intel_encoder->base);
> struct intel_connector *intel_connector =
> lvds_encoder->attached_connector;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> unsigned int lvds_bpp;
>
> /* Should never happen!! */
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index bc14e9c0285a..6f3eaae3761f 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *pipe_config,
> int fitting_mode)
> {
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int x = 0, y = 0, width = 0, height = 0;
>
> /* Native modes don't need fitting */
> @@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
> static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
> u32 *pfit_control)
> {
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u32 scaled_width = adjusted_mode->crtc_hdisplay *
> pipe_config->pipe_src_h;
> u32 scaled_height = pipe_config->pipe_src_w *
> @@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
> u32 *pfit_control, u32 *pfit_pgm_ratios,
> u32 *border)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u32 scaled_width = adjusted_mode->crtc_hdisplay *
> pipe_config->pipe_src_h;
> u32 scaled_height = pipe_config->pipe_src_w *
> @@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> /* Native modes don't need fitting */
> if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
> @@ -1047,7 +1047,7 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> u32 ctl, ctl2;
>
> ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
> @@ -1077,7 +1077,7 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> u32 pwm_ctl, val;
>
> /* Controller 1 uses the utility pin. */
> @@ -1189,7 +1189,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>
> if (!panel->backlight.present)
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 6260a2082719..2746512f4466 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -309,13 +309,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
> goto put_state;
> }
>
> - pipe_config->base.mode_changed = pipe_config->has_psr;
> + pipe_config->uapi.mode_changed = pipe_config->has_psr;
> pipe_config->crc_enabled = enable;
>
> if (IS_HASWELL(dev_priv) &&
> - pipe_config->base.active && crtc->pipe == PIPE_A &&
> + pipe_config->hw.active && crtc->pipe == PIPE_A &&
> pipe_config->cpu_transcoder == TRANSCODER_EDP)
> - pipe_config->base.mode_changed = true;
> + pipe_config->uapi.mode_changed = true;
>
> ret = drm_atomic_commit(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b3c7eef53bf3..8988dbe8c19e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -538,8 +538,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
> - int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
> + int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> + int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> int psr_max_h = 0, psr_max_v = 0;
>
> if (!dev_priv->psr.sink_psr2_support)
> @@ -605,7 +605,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> if (!CAN_PSR(dev_priv))
> @@ -745,7 +745,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>
> dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
> dev_priv->psr.busy_frontbuffer_bits = 0;
> - dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -988,7 +988,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
> int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> u32 *out_value)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 47f5d87a938a..1047357c15c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
> {
> struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int ret;
>
> if (!crtc_state->has_hdmi_sink)
> @@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
> to_intel_sdvo_connector_state(conn_state);
> struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(conn_state->connector);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> - struct drm_display_mode *mode = &pipe_config->base.mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> + struct drm_display_mode *mode = &pipe_config->hw.mode;
>
> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> pipe_config->pipe_bpp = 8*3;
> @@ -1429,13 +1429,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> const struct intel_sdvo_connector_state *sdvo_state =
> to_intel_sdvo_connector_state(conn_state);
> const struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(conn_state->connector);
> - const struct drm_display_mode *mode = &crtc_state->base.mode;
> + const struct drm_display_mode *mode = &crtc_state->hw.mode;
> struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
> u32 sdvox;
> struct intel_sdvo_in_out_map in_out;
> @@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
> }
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> /*
> * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
> @@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>
> /* Cross check the port pixel multiplier with the sdvo encoder state. */
> if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
> @@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
> const struct drm_connector_state *conn_state)
> {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> u8 *eld = connector->eld;
>
> @@ -1723,7 +1723,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> u32 temp;
>
> if (old_crtc_state->has_audio)
> @@ -1785,7 +1785,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> u32 temp;
> bool input1, input2;
> int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 633fa8069348..526a9366b682 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -81,9 +81,9 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> */
> void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -190,7 +190,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> */
> void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> @@ -203,14 +203,15 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> * Would be slightly nice to just grab the vblank count and arm the
> * event outside of the critical section - the spinlock might spin for a
> * while ... */
> - if (new_crtc_state->base.event) {
> + if (new_crtc_state->uapi.event) {
> WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
>
> spin_lock(&crtc->base.dev->event_lock);
> - drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
> + drm_crtc_arm_vblank_event(&crtc->base,
> + new_crtc_state->uapi.event);
> spin_unlock(&crtc->base.dev->event_lock);
>
> - new_crtc_state->base.event = NULL;
> + new_crtc_state->uapi.event = NULL;
> }
>
> local_irq_enable();
> @@ -1515,7 +1516,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
> const struct drm_rect *dst = &plane_state->base.dst;
> int src_x, src_w, src_h, crtc_w, crtc_h;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int stride = plane_state->color_plane[0].stride;
> unsigned int cpp = fb->format->cpp[0];
> unsigned int width_bytes;
> @@ -1588,7 +1589,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> min_scale, max_scale,
> true, true);
> if (ret)
> @@ -1645,7 +1646,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return ret;
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> true, true);
> @@ -1729,8 +1730,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> }
>
> /* Y-tiling is not supported in IF-ID Interlace mode */
> - if (crtc_state->base.enable &&
> - crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
> + if (crtc_state->hw.enable &&
> + crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
> (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> @@ -1810,7 +1811,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> min_scale, max_scale,
> true, true);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index 70726b481244..4499d402c316 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -924,7 +924,7 @@ intel_enable_tv(struct intel_encoder *encoder,
>
> /* Prevents vblank waits from timing out in intel_tv_detect_type() */
> intel_wait_for_vblank(dev_priv,
> - to_intel_crtc(pipe_config->base.crtc)->pipe);
> + to_intel_crtc(pipe_config->uapi.crtc)->pipe);
>
> I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
> }
> @@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> struct drm_display_mode mode = {};
> u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
> struct tv_mode tv_mode = {};
> @@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> to_intel_tv_connector_state(conn_state);
> const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> int hdisplay = adjusted_mode->crtc_hdisplay;
> int vdisplay = adjusted_mode->crtc_vdisplay;
>
> @@ -1417,7 +1417,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_tv *intel_tv = enc_to_tv(encoder);
> const struct intel_tv_connector_state *tv_conn_state =
> to_intel_tv_connector_state(conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d4fb7f16f9f6..38c181499505 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> int column_index = 0;
> u8 line_buf_depth = 0;
>
> - vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
> - vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
> + vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> + vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> pipe_config->dsc_params.slice_count);
> /*
> @@ -459,7 +459,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -483,7 +483,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> enum pipe pipe = crtc->pipe;
> @@ -902,7 +902,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> @@ -938,7 +938,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>
> void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 50064cde0724..16f93d1e71e5 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -261,9 +261,9 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int ret;
>
> DRM_DEBUG_KMS("\n");
> @@ -624,7 +624,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
>
> @@ -746,7 +746,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe;
> @@ -1032,9 +1032,9 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> struct drm_display_mode *adjusted_mode_sw;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> unsigned int lane_count = intel_dsi->lane_count;
> unsigned int bpp, fmt;
> @@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> crtc_hblank_start_sw, crtc_hblank_end_sw;
>
> /* FIXME: hw readout should not depend on SW state */
> - adjusted_mode_sw = &crtc->config->base.adjusted_mode;
> + adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
>
> /*
> * Atleast one port is active as encoder->get_config called only if
> @@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> }
>
> if (pclk) {
> - pipe_config->base.adjusted_mode.crtc_clock = pclk;
> + pipe_config->hw.adjusted_mode.crtc_clock = pclk;
> pipe_config->port_clock = pclk;
> }
> }
> @@ -1315,9 +1315,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> enum port port;
> unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> u32 val, tmp;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fec9fb7cc384..7ce3ae1ec586 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2752,11 +2752,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
> crtc->base.base.id, pipe_name(crtc->pipe),
> - yesno(pipe_config->base.active),
> + yesno(pipe_config->hw.active),
> pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> yesno(pipe_config->dither), pipe_config->pipe_bpp);
>
> - if (pipe_config->base.active) {
> + if (pipe_config->hw.active) {
> struct intel_plane *cursor =
> to_intel_plane(crtc->base.cursor);
>
> @@ -4208,11 +4208,11 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> !crtc_state->has_drrs)
> goto out;
>
> - commit = crtc_state->base.commit;
> + commit = crtc_state->uapi.commit;
> if (commit) {
> ret = wait_for_completion_interruptible(&commit->hw_done);
> if (ret)
> @@ -4224,7 +4224,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
> struct intel_encoder *encoder;
> struct intel_dp *intel_dp;
>
> - if (!(crtc_state->base.connector_mask &
> + if (!(crtc_state->uapi.connector_mask &
> drm_connector_mask(connector)))
> continue;
>
> @@ -4283,14 +4283,14 @@ i915_fifo_underrun_reset_write(struct file *filp,
> return ret;
>
> crtc_state = to_intel_crtc_state(intel_crtc->base.state);
> - commit = crtc_state->base.commit;
> + commit = crtc_state->uapi.commit;
> if (commit) {
> ret = wait_for_completion_interruptible(&commit->hw_done);
> if (!ret)
> ret = wait_for_completion_interruptible(&commit->flip_done);
> }
>
> - if (!ret && crtc_state->base.active) {
> + if (!ret && crtc_state->hw.active) {
> DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
> pipe_name(intel_crtc->pipe));
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5e6e54cb22fe..4c9359981c24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -464,7 +464,7 @@ static const int pessimal_latency_ns = 5000;
>
> static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
> enum pipe pipe = crtc->pipe;
> @@ -798,7 +798,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>
> /* FIXME check the 'enable' instead */
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return false;
>
> /*
> @@ -851,7 +851,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
> crtc = single_enabled_crtc(dev_priv);
> if (crtc) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp = fb->format->cpp[0];
> @@ -1087,7 +1087,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> unsigned int clock, htotal, cpp, width, wm;
>
> @@ -1144,7 +1144,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> int level, enum plane_id plane_id, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> bool dirty = false;
>
> for (; level < intel_wm_num_levels(dev_priv); level++) {
> @@ -1160,7 +1160,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
> int level, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> bool dirty = false;
>
> /* NORMAL level doesn't have an FBC watermark */
> @@ -1262,7 +1262,7 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
> static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
> int level)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (level > dev_priv->wm.max_level)
> return false;
> @@ -1300,9 +1300,9 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
>
> static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
> int num_active_planes = hweight8(crtc_state->active_planes &
> ~BIT(PLANE_CURSOR));
> @@ -1389,17 +1389,17 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>
> static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
> const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
> enum plane_id plane_id;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -1531,8 +1531,8 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> static void g4x_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1543,8 +1543,8 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -1593,7 +1593,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int clock, htotal, cpp, width, wm;
>
> if (dev_priv->wm.pri_latency[level] == 0)
> @@ -1631,7 +1631,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
>
> static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct g4x_pipe_wm *raw =
> &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
> struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
> @@ -1743,7 +1743,7 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
> static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> int level, enum plane_id plane_id, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int num_levels = intel_wm_num_levels(dev_priv);
> bool dirty = false;
>
> @@ -1818,16 +1818,16 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
>
> static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
> const struct vlv_fifo_state *fifo_state =
> &crtc_state->wm.vlv.fifo_state;
> int num_active_planes = hweight8(crtc_state->active_planes &
> ~BIT(PLANE_CURSOR));
> - bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
> + bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
> const struct intel_plane_state *old_plane_state;
> const struct intel_plane_state *new_plane_state;
> struct intel_plane *plane;
> @@ -1926,7 +1926,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_uncore *uncore = &dev_priv->uncore;
> const struct vlv_fifo_state *fifo_state =
> @@ -2022,17 +2022,17 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>
> static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
> const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
> int level;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -2150,8 +2150,8 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> static void vlv_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> @@ -2162,8 +2162,8 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -2188,7 +2188,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 12000;
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int clock = adjusted_mode->crtc_clock;
> @@ -2269,7 +2269,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2296,7 +2296,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2344,7 +2344,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 6000;
> const struct drm_display_mode *adjusted_mode =
> - &enabled->config->base.adjusted_mode;
> + &enabled->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> enabled->base.primary->state->fb;
> int clock = adjusted_mode->crtc_clock;
> @@ -2402,7 +2402,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> if (crtc == NULL)
> return;
>
> - adjusted_mode = &crtc->config->base.adjusted_mode;
> + adjusted_mode = &crtc->config->hw.adjusted_mode;
> planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> &i845_wm_info,
> dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> @@ -2492,7 +2492,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> return method1;
>
> method2 = ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
>
> @@ -2520,7 +2520,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
>
> method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> method2 = ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
> return min(method1, method2);
> @@ -2545,7 +2545,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> cpp = plane_state->base.fb->format->cpp[0];
>
> return ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
> }
> @@ -2767,12 +2767,12 @@ static u32
> hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> u32 linetime, ips_linetime;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
> if (WARN_ON(adjusted_mode->crtc_clock == 0))
> return 0;
> @@ -3082,11 +3082,9 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
> /* Compute new watermarks for the pipe */
> static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_pipe_wm *pipe_wm;
> - struct drm_device *dev = state->dev;
> - const struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> const struct intel_plane_state *pristate = NULL;
> @@ -3106,7 +3104,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> curstate = plane_state;
> }
>
> - pipe_wm->pipe_enabled = crtc_state->base.active;
> + pipe_wm->pipe_enabled = crtc_state->hw.active;
> if (sprstate) {
> pipe_wm->sprites_enabled = sprstate->base.visible;
> pipe_wm->sprites_scaled = sprstate->base.visible &&
> @@ -3163,11 +3161,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> */
> static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(newstate->base.state);
> + to_intel_atomic_state(newstate->uapi.state);
> const struct intel_crtc_state *oldstate =
> intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
> const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
> @@ -3179,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
> * and after the vblank.
> */
> *a = newstate->wm.ilk.optimal;
> - if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
> + if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
> intel_state->skip_intermediate_wm)
> return 0;
>
> @@ -3756,7 +3754,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> - if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> return false;
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> @@ -3806,7 +3804,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> return ddb_size - 4; /* 4 blocks for bypass path allocation */
>
> - adjusted_mode = &crtc_state->base.adjusted_mode;
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
>
> /*
> @@ -3835,16 +3833,16 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> struct skl_ddb_entry *alloc, /* out */
> int *num_active /* out */)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct drm_crtc *for_crtc = crtc_state->base.crtc;
> + struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
> const struct intel_crtc *crtc;
> u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
> enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> u16 ddb_size;
> u32 i;
>
> - if (WARN_ON(!state) || !crtc_state->base.active) {
> + if (WARN_ON(!state) || !crtc_state->hw.active) {
> alloc->start = 0;
> alloc->end = 0;
> *num_active = hweight8(dev_priv->active_pipes);
> @@ -3883,11 +3881,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> */
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> int hdisplay, vdisplay;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> continue;
>
> drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> @@ -3918,7 +3916,7 @@ static unsigned int
> skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> int num_active)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level wm = {};
> int ret, min_ddb_alloc = 0;
> @@ -4076,7 +4074,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
> {
> uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return pipe_downscale;
>
> if (crtc_state->pch_pfit.enabled) {
> @@ -4108,7 +4106,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> const struct intel_plane_state *plane_state;
> struct intel_plane *plane;
> int crtc_clock, dotclk;
> @@ -4116,7 +4114,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return 0;
>
> intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> @@ -4142,7 +4140,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>
> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>
> - crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> + crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
> dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>
> if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> @@ -4209,7 +4207,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate,
> u64 *uv_plane_data_rate)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
> @@ -4244,7 +4242,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> - if (WARN_ON(!crtc_state->base.state))
> + if (WARN_ON(!crtc_state->uapi.state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> @@ -4288,8 +4286,8 @@ static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> + struct drm_crtc *crtc = crtc_state->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> @@ -4311,7 +4309,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> if (WARN_ON(!state))
> return 0;
>
> - if (!crtc_state->base.active) {
> + if (!crtc_state->hw.active) {
> alloc->start = alloc->end = 0;
> return 0;
> }
> @@ -4553,7 +4551,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> u32 crtc_htotal;
> uint_fixed_16_16_t linetime_us;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return u32_to_fixed16(0);
>
> pixel_rate = crtc_state->pixel_rate;
> @@ -4561,7 +4559,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> if (WARN_ON(pixel_rate == 0))
> return u32_to_fixed16(0);
>
> - crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
> + crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
>
> return linetime_us;
> @@ -4596,7 +4594,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> int color_plane)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 interm_pbpl;
>
> @@ -4717,7 +4715,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> @@ -4743,14 +4741,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> wp->cpp, latency, wp->dbuf_block_size);
> method2 = skl_wm_method2(wp->plane_pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> latency,
> wp->plane_blocks_per_line);
>
> if (wp->y_tiled) {
> selected_result = max_fixed16(method2, wp->y_tile_minimum);
> } else {
> - if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
> + if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> wp->dbuf_block_size < 1) &&
> (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> selected_result = method2;
> @@ -4841,7 +4839,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level *result_prev = &levels[0];
>
> @@ -4858,7 +4856,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> static u32
> skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> uint_fixed_16_16_t linetime_us;
> u32 linetime_wm;
> @@ -4877,7 +4875,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wp,
> struct skl_plane_wm *wm)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> u16 trans_min, trans_y_tile_min;
> const u16 trans_amount = 10; /* This is configurable amount */
> @@ -5037,7 +5035,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>
> static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> @@ -5227,8 +5225,8 @@ static int
> skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_plane *plane;
>
> @@ -5529,7 +5527,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> * power well the hardware state will go out of sync
> * with the software state.
> */
> - if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
> + if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
> skl_plane_wm_equals(dev_priv,
> &old_crtc_state->wm.skl.optimal.planes[plane_id],
> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
> @@ -5597,7 +5595,7 @@ skl_compute_wm(struct intel_atomic_state *state)
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> enum pipe pipe = crtc->pipe;
> @@ -5611,7 +5609,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> static void skl_initial_wm(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct skl_ddb_values *results = &state->wm_results;
> @@ -5621,7 +5619,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>
> mutex_lock(&dev_priv->wm.wm_mutex);
>
> - if (crtc_state->base.active_changed)
> + if (crtc_state->uapi.active_changed)
> skl_atomic_update_crtc_wm(state, crtc_state);
>
> mutex_unlock(&dev_priv->wm.wm_mutex);
> @@ -5680,8 +5678,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> @@ -5692,8 +5690,8 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
2019-10-08 17:06 ` Ville Syrjälä
@ 2019-10-10 14:21 ` Maarten Lankhorst
2019-10-10 14:47 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 14:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
>> We want to split drm_crtc_state into the user visible state
>> and actual hardware state. To prepare for this, we need some
>> ground rules what should be in each state:
>>
>> In uapi we use:
>> - crtc, *_changed flags, event, commit, state, mode_blob,
>> (plane/connector/encoder)_mask.
>>
>> In hw state we use what's displayed in hardware:
>> - enable, active, (adjusted) mode, color property blobs.
>>
>> clear_intel_crtc_state and hw readout need to be updated for these rules,
>> which will allow us to enable 2 joined pipes.
> I still have hard time with reading this patch. I still think it
> would be easier to read if we didn't do both the "uapi" and "hw" changes
> at the same time.
>
> step 1.
> struct drm_crtc_state uapi;
> struct {
> // hw state
> } base;
>
> step 2.
> s/base/hw/
>
> I think that would make it more obvious which parts of the code are
> looking at which state.
It wouldn't I think, but here's
a dumb change with spatch on this patch.
//+ struct {
//+ bool active, enable;
//+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
//+ struct drm_display_mode mode, adjusted_mode;
//+ } hw;
@@
struct intel_crtc_state *T;
@@
-T->uapi.active
+T->hw.active
@@
struct intel_crtc_state *T;
@@
-T->uapi.enable
+T->hw.enable
@@
struct intel_crtc_state *T;
@@
-T->uapi.degamma_lut
+T->hw.degamma_lut
@@
struct intel_crtc_state *T;
@@
-T->uapi.gamma_lut
+T->hw.gamma_lut
@@
struct intel_crtc_state *T;
@@
-T->uapi.ctm
+T->hw.ctm
@@
struct intel_crtc_state *T;
@@
-T->uapi.mode
+T->hw.mode
@@
struct intel_crtc_state *T;
@@
-T->uapi.adjusted_mode
+T->hw.adjusted_mode
I replaced all the instances where we use the uapi members instead of the hw members explicitly in this patch, and came up with the following diff below.
Only the intel_color readout is potentially incorrect, the 2 explicit uapi uses in intel_display.c are needed.
Didn't fix it because of hw readout, it possibly needs slightly more thought.
Does this satisfy the readability requirements? :)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ab10c33266bf..cbf4c6e6e661 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11217,7 +11217,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
goto fail;
}
- crtc_state->uapi.active = crtc_state->uapi.enable = true;
+ crtc_state->hw.active = crtc_state->hw.enable = true;
if (!mode)
mode = &load_detect_mode;
@@ -13578,7 +13578,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!needs_modeset(new_crtc_state))
continue;
- if (!new_crtc_state->uapi.enable) {
+ if (!new_crtc_state->hw.enable) {
any_ms = true;
continue;
}
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5586891572f8..52712bb9ed15 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
if (!crtc_state->gamma_enable)
return;
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
}
static struct drm_property_blob *
@@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
return;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
+ crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
}
static struct drm_property_blob *
@@ -1715,7 +1715,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
static void chv_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
- crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
+ crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
else
i965_read_luts(crtc_state);
}
@@ -1762,9 +1762,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
return;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->uapi.gamma_lut = ilk_read_lut_10(crtc_state);
+ crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
}
static struct drm_property_blob *
@@ -1811,9 +1811,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
return;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->uapi.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+ crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
void intel_color_init(struct intel_crtc *crtc)
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^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
2019-10-10 14:21 ` Maarten Lankhorst
@ 2019-10-10 14:47 ` Ville Syrjälä
2019-10-14 8:20 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-10 14:47 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> >> We want to split drm_crtc_state into the user visible state
> >> and actual hardware state. To prepare for this, we need some
> >> ground rules what should be in each state:
> >>
> >> In uapi we use:
> >> - crtc, *_changed flags, event, commit, state, mode_blob,
> >> (plane/connector/encoder)_mask.
> >>
> >> In hw state we use what's displayed in hardware:
> >> - enable, active, (adjusted) mode, color property blobs.
> >>
> >> clear_intel_crtc_state and hw readout need to be updated for these rules,
> >> which will allow us to enable 2 joined pipes.
> > I still have hard time with reading this patch. I still think it
> > would be easier to read if we didn't do both the "uapi" and "hw" changes
> > at the same time.
> >
> > step 1.
> > struct drm_crtc_state uapi;
> > struct {
> > // hw state
> > } base;
> >
> > step 2.
> > s/base/hw/
> >
> > I think that would make it more obvious which parts of the code are
> > looking at which state.
>
> It wouldn't I think, but here's
> a dumb change with spatch on this patch.
>
> //+ struct {
> //+ bool active, enable;
> //+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> //+ struct drm_display_mode mode, adjusted_mode;
> //+ } hw;
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.active
> +T->hw.active
This doesn't really help me. There is no .uapi in upstream
code. I would like to see just the .base->.uapi changes
alone first so I can review which parts start to look at
the uapi state to make sure we aren't changing too much.
Then I'd like to to see the .base->.hw changes so that I
convince myself we didn't miss anything in the .base->.uapi
conversion.
And all the remaining drm_crtc_state usage is going to
make us miss something for sure, so getting rid of all that
first would probably help.
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.enable
> +T->hw.enable
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.degamma_lut
> +T->hw.degamma_lut
>
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.gamma_lut
> +T->hw.gamma_lut
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.ctm
> +T->hw.ctm
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.mode
> +T->hw.mode
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.adjusted_mode
> +T->hw.adjusted_mode
>
> I replaced all the instances where we use the uapi members instead of the hw members explicitly in this patch, and came up with the following diff below.
>
> Only the intel_color readout is potentially incorrect, the 2 explicit uapi uses in intel_display.c are needed.
> Didn't fix it because of hw readout, it possibly needs slightly more thought.
>
> Does this satisfy the readability requirements? :)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ab10c33266bf..cbf4c6e6e661 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11217,7 +11217,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
> goto fail;
> }
>
> - crtc_state->uapi.active = crtc_state->uapi.enable = true;
> + crtc_state->hw.active = crtc_state->hw.enable = true;
>
> if (!mode)
> mode = &load_detect_mode;
> @@ -13578,7 +13578,7 @@ static int intel_atomic_check(struct drm_device *dev,
> if (!needs_modeset(new_crtc_state))
> continue;
>
> - if (!new_crtc_state->uapi.enable) {
> + if (!new_crtc_state->hw.enable) {
> any_ms = true;
> continue;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 5586891572f8..52712bb9ed15 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> if (!crtc_state->gamma_enable)
> return;
>
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> static struct drm_property_blob *
> @@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
> return;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
> + crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
> }
>
> static struct drm_property_blob *
> @@ -1715,7 +1715,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> static void chv_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> - crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
> + crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
> else
> i965_read_luts(crtc_state);
> }
> @@ -1762,9 +1762,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> return;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->uapi.gamma_lut = ilk_read_lut_10(crtc_state);
> + crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
> }
>
> static struct drm_property_blob *
> @@ -1811,9 +1811,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
> return;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->uapi.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> + crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> void intel_color_init(struct intel_crtc *crtc)
--
Ville Syrjälä
Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
2019-10-10 14:47 ` Ville Syrjälä
@ 2019-10-14 8:20 ` Maarten Lankhorst
0 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-14 8:20 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 10-10-2019 om 16:47 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
>>>> We want to split drm_crtc_state into the user visible state
>>>> and actual hardware state. To prepare for this, we need some
>>>> ground rules what should be in each state:
>>>>
>>>> In uapi we use:
>>>> - crtc, *_changed flags, event, commit, state, mode_blob,
>>>> (plane/connector/encoder)_mask.
>>>>
>>>> In hw state we use what's displayed in hardware:
>>>> - enable, active, (adjusted) mode, color property blobs.
>>>>
>>>> clear_intel_crtc_state and hw readout need to be updated for these rules,
>>>> which will allow us to enable 2 joined pipes.
>>> I still have hard time with reading this patch. I still think it
>>> would be easier to read if we didn't do both the "uapi" and "hw" changes
>>> at the same time.
>>>
>>> step 1.
>>> struct drm_crtc_state uapi;
>>> struct {
>>> // hw state
>>> } base;
>>>
>>> step 2.
>>> s/base/hw/
>>>
>>> I think that would make it more obvious which parts of the code are
>>> looking at which state.
>> It wouldn't I think, but here's
>> a dumb change with spatch on this patch.
>>
>> //+ struct {
>> //+ bool active, enable;
>> //+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
>> //+ struct drm_display_mode mode, adjusted_mode;
>> //+ } hw;
>>
>> @@
>> struct intel_crtc_state *T;
>> @@
>> -T->uapi.active
>> +T->hw.active
> This doesn't really help me. There is no .uapi in upstream
> code. I would like to see just the .base->.uapi changes
> alone first so I can review which parts start to look at
> the uapi state to make sure we aren't changing too much.
> Then I'd like to to see the .base->.hw changes so that I
> convince myself we didn't miss anything in the .base->.uapi
> conversion.
>
> And all the remaining drm_crtc_state usage is going to
> make us miss something for sure, so getting rid of all that
> first would probably help.
Hey,
You are correct that there is no upstream use for uapi, but it's simply
called 'base', so it would be just a big rename patch.
For !bigjoiner, the hw and uapi state are aliases. So
for example sdvo/tv it doesn't matter that drm_crtc_state is used.
The spatch I made shows that only intel_get_load_detect_pipe and color readout
use the uapi members instead of the hw members, and there are good reasons to do so.
All other instances all use hw.
As far as I can tell, even without patch 9/24 it will work
correctly, because in intel_initial_commit() atomic_check will pull
in the slave crtc, intel_dp_mst_atomic_check() and intel_psr_fastset_force()
are only called for the master crtc.
Manual verification on the remaining users of drm_crtc_state show that there
is no issue that drm_crtc_state is used. They could be fixed but would never
be affected by bigjoiner.
~Maarten
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (7 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state Maarten Lankhorst
@ 2019-10-04 11:34 ` Maarten Lankhorst
2019-10-04 13:31 ` Ville Syrjälä
2019-10-04 11:35 ` [PATCH 10/24] drm/i915: Complete crtc hw/uapi split, v2 Maarten Lankhorst
` (17 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:34 UTC (permalink / raw)
To: intel-gfx
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead. Look at uapi/hw where appropriate.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f555ff6b1f6a..fcd295ed80ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16139,15 +16139,15 @@ static int intel_initial_commit(struct drm_device *dev)
retry:
state->acquire_ctx = &ctx;
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ crtc_state = intel_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->hw.active) {
+ ret = drm_atomic_add_affected_planes(state, &crtc->base);
if (ret)
goto out;
@@ -16157,7 +16157,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->uapi.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index cecb7ba5b482..adf1d3895419 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (!crtc_state ||
!drm_atomic_crtc_needs_modeset(crtc_state) ||
- crtc_state->enable)
+ to_intel_crtc_state(crtc_state)->hw.enable)
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8988dbe8c19e..979e166f5639 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1068,9 +1068,9 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (crtc_state->active && intel_crtc_state->has_psr) {
+ if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
- crtc_state->mode_changed = true;
+ intel_crtc_state->uapi.mode_changed = true;
break;
}
}
--
2.23.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
2019-10-04 11:34 ` [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split Maarten Lankhorst
@ 2019-10-04 13:31 ` Ville Syrjälä
2019-10-04 15:51 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 13:31 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
> We are still looking at drm_crtc_state in a few places, convert those
> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f555ff6b1f6a..fcd295ed80ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device *dev)
> {
> struct drm_atomic_state *state = NULL;
> struct drm_modeset_acquire_ctx ctx;
> - struct drm_crtc *crtc;
> - struct drm_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
I'd prefer to lift most of this patch to before we do that state split
so it can be pushed out of the way.
> int ret = 0;
>
> state = drm_atomic_state_alloc(dev);
> @@ -16139,15 +16139,15 @@ static int intel_initial_commit(struct drm_device *dev)
> retry:
> state->acquire_ctx = &ctx;
>
> - drm_for_each_crtc(crtc, dev) {
> - crtc_state = drm_atomic_get_crtc_state(state, crtc);
> + for_each_intel_crtc(dev, crtc) {
> + crtc_state = intel_atomic_get_crtc_state(state, crtc);
> if (IS_ERR(crtc_state)) {
> ret = PTR_ERR(crtc_state);
> goto out;
> }
>
> - if (crtc_state->active) {
> - ret = drm_atomic_add_affected_planes(state, crtc);
> + if (crtc_state->hw.active) {
> + ret = drm_atomic_add_affected_planes(state, &crtc->base);
> if (ret)
> goto out;
>
> @@ -16157,7 +16157,7 @@ static int intel_initial_commit(struct drm_device *dev)
> * having a proper LUT loaded. Remove once we
> * have readout for pipe gamma enable.
> */
> - crtc_state->color_mgmt_changed = true;
> + crtc_state->uapi.color_mgmt_changed = true;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index cecb7ba5b482..adf1d3895419 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
>
> if (!crtc_state ||
> !drm_atomic_crtc_needs_modeset(crtc_state) ||
> - crtc_state->enable)
> + to_intel_crtc_state(crtc_state)->hw.enable)
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8988dbe8c19e..979e166f5639 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1068,9 +1068,9 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
>
> intel_crtc_state = to_intel_crtc_state(crtc_state);
>
> - if (crtc_state->active && intel_crtc_state->has_psr) {
> + if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
> /* Mark mode as changed to trigger a pipe->update() */
> - crtc_state->mode_changed = true;
> + intel_crtc_state->uapi.mode_changed = true;
> break;
> }
> }
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
2019-10-04 13:31 ` Ville Syrjälä
@ 2019-10-04 15:51 ` Maarten Lankhorst
2019-10-04 15:56 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 15:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
>> We are still looking at drm_crtc_state in a few places, convert those
>> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
>> 3 files changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index f555ff6b1f6a..fcd295ed80ed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device *dev)
>> {
>> struct drm_atomic_state *state = NULL;
>> struct drm_modeset_acquire_ctx ctx;
>> - struct drm_crtc *crtc;
>> - struct drm_crtc_state *crtc_state;
>> + struct intel_crtc *crtc;
>> + struct intel_crtc_state *crtc_state;
> I'd prefer to lift most of this patch to before we do that state split
> so it can be pushed out of the way.
If you apply
https://lists.freedesktop.org/archives/intel-gfx/2019-September/214268.html
and I put this before the hw split patch, do I get your r-b up to [PATCH 12/24] drm/i915: Split plane hw and uapi state ?
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split
2019-10-04 15:51 ` Maarten Lankhorst
@ 2019-10-04 15:56 ` Ville Syrjälä
0 siblings, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-04 15:56 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 05:51:16PM +0200, Maarten Lankhorst wrote:
> Op 04-10-2019 om 15:31 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:59PM +0200, Maarten Lankhorst wrote:
> >> We are still looking at drm_crtc_state in a few places, convert those
> >> to use intel_crtc_state instead. Look at uapi/hw where appropriate.
> >>
> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
> >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> >> 3 files changed, 10 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index f555ff6b1f6a..fcd295ed80ed 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -16126,8 +16126,8 @@ static int intel_initial_commit(struct drm_device *dev)
> >> {
> >> struct drm_atomic_state *state = NULL;
> >> struct drm_modeset_acquire_ctx ctx;
> >> - struct drm_crtc *crtc;
> >> - struct drm_crtc_state *crtc_state;
> >> + struct intel_crtc *crtc;
> >> + struct intel_crtc_state *crtc_state;
> > I'd prefer to lift most of this patch to before we do that state split
> > so it can be pushed out of the way.
>
> If you apply
>
> https://lists.freedesktop.org/archives/intel-gfx/2019-September/214268.html
>
> and I put this before the hw split patch, do I get your r-b up to [PATCH 12/24] drm/i915: Split plane hw and uapi state ?
Haven't gotten that far yet.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 10/24] drm/i915: Complete crtc hw/uapi split, v2.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (8 preceding siblings ...)
2019-10-04 11:34 ` [PATCH 09/24] drm/i915: Handle a few more cases for crtc hw/uapi split Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 11/24] drm/i915: Preparation for plane split Maarten Lankhorst
` (16 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediately after drm_atomic_helper_check_modeset().
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++---
.../drm/i915/display/intel_display_types.h | 8 ++--
4 files changed, 89 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf13b9c7d38..266d0ce9d03d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return &crtc_state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+
+ if (crtc_state->uapi.degamma_lut)
+ crtc_state->hw.degamma_lut =
+ drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ else
+ crtc_state->hw.degamma_lut = NULL;
+
+ if (crtc_state->uapi.gamma_lut)
+ crtc_state->hw.gamma_lut =
+ drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ else
+ crtc_state->hw.gamma_lut = NULL;
+
+ if (crtc_state->uapi.ctm)
+ crtc_state->hw.ctm =
+ drm_property_blob_get(crtc_state->uapi.ctm);
+ else
+ crtc_state->hw.ctm = NULL;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..42be91e0772a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fcd295ed80ed..c2debb402844 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -7056,6 +7057,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+ copy_uapi_to_hw_state(to_intel_crtc_state(crtc->state));
for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
encoder->base.crtc = NULL;
@@ -12274,6 +12276,23 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
return ret;
}
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->hw.enable = crtc_state->uapi.enable;
+ crtc_state->hw.active = crtc_state->uapi.active;
+ crtc_state->hw.mode = crtc_state->uapi.mode;
+ crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+ intel_crtc_copy_color_blobs(crtc_state);
+}
+
+static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->uapi.enable = crtc_state->hw.enable;
+ crtc_state->uapi.active = crtc_state->hw.active;
+ crtc_state->uapi.mode = crtc_state->hw.mode;
+ crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+}
+
static int
clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
{
@@ -12290,6 +12309,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
* fixed, so that the crtc_state can be safely duplicated. For now,
* only fields that are know to not cause problems are preserved. */
+ saved_state->uapi = crtc_state->uapi;
saved_state->scaler_state = crtc_state->scaler_state;
saved_state->shared_dpll = crtc_state->shared_dpll;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
@@ -12300,11 +12320,9 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
saved_state->wm = crtc_state->wm;
- /* Keep base drm_crtc_state intact, only clear our extended struct */
- BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
- BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
- memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
- sizeof(*crtc_state) - sizeof(crtc_state->uapi));
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ copy_uapi_to_hw_state(crtc_state);
kfree(saved_state);
return 0;
@@ -12444,6 +12462,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
+ /* uapi wants a copy of the adjusted_mode for vblank bookkeeping */
+ pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
+
return 0;
}
@@ -13165,6 +13186,8 @@ verify_crtc_state(struct intel_crtc *crtc,
state = old_crtc_state->uapi.state;
__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
+ intel_crtc_free_hw_state(old_crtc_state);
+
pipe_config = old_crtc_state;
memset(pipe_config, 0, sizeof(*pipe_config));
pipe_config->uapi.crtc = &crtc->base;
@@ -13586,11 +13609,17 @@ static int intel_atomic_check(struct drm_device *dev,
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(new_crtc_state))
+ if (!needs_modeset(new_crtc_state)) {
+ if (new_crtc_state->uapi.color_mgmt_changed)
+ intel_crtc_copy_color_blobs(new_crtc_state);
continue;
+ }
if (!new_crtc_state->uapi.enable) {
any_ms = true;
+ intel_crtc_free_hw_state(new_crtc_state);
+ memset(&new_crtc_state->hw, 0,
+ sizeof(new_crtc_state->hw));
continue;
}
@@ -16688,6 +16717,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
to_intel_crtc_state(crtc->base.state);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
memset(crtc_state, 0, sizeof(*crtc_state));
__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
@@ -16804,6 +16834,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
crtc_state);
+ crtc_state->hw.mode = crtc->base.mode;
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
/*
@@ -16849,6 +16880,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_bw_crtc_update(bw_state, crtc_state);
+ copy_hw_to_uapi_state(crtc_state);
intel_pipe_config_sanity_check(dev_priv, crtc_state);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0ee69e8f0942..9401915bc93a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -749,7 +749,6 @@ enum intel_output_format {
};
struct intel_crtc_state {
- union {
/*
* uapi (drm) state. This is the software state shown to userspace.
* In particular, the following members are used for bookkeeping:
@@ -772,8 +771,11 @@ struct intel_crtc_state {
*
* During initial hw readout, they need to be copied to uapi.
*/
- struct drm_crtc_state hw;
- };
+ struct {
+ bool active, enable;
+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
+ struct drm_display_mode mode, adjusted_mode;
+ } hw;
/**
* quirks - bitfield with hw state readout quirks
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 11/24] drm/i915: Preparation for plane split
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (9 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 10/24] drm/i915: Complete crtc hw/uapi split, v2 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 12/24] drm/i915: Split plane hw and uapi state Maarten Lankhorst
` (15 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
We split plane_state into hw and uapi, this will allow us to
make bigjoiner work without rewriting the entire atomic_check and
plane programming to be bigjoienr aware.
This results in a cleaner bigjoiner implementation than if we use
a separate plane_state.
The only exception is intel_legacy_cursor_update, but that uses
the drm_plane_state directly, correctly.
spatch and guidelines below, keep in mind get_crtc_from_states()
needs access to uapi, because plane_state is not copied yet.
struct drm_plane_state {
// derived state and fixed state, safe to use intel_plane_state->uapi:
struct drm_rect src, dst;
bool visible;
struct drm_plane *plane;
struct drm_crtc_commit *commit;
struct drm_atomic_state *state;
struct dma_fence fence;
// HW properties, must use intel_plane_state->hw
struct drm_crtc *crtc;
struct drm_framebuffer *fb;
u16 alpha;
uint16_t pixel_blend_mode;
unsigned int rotation;
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
};
@@
struct intel_plane_state *T;
@@
-T->base.src
+T->uapi.src
@@
struct intel_plane_state *T;
@@
-T->base.dst
+T->uapi.dst
@@
struct intel_plane_state *T;
@@
-T->base.visible
+T->uapi.visible
@@
struct intel_plane_state *T;
@@
-T->base.plane
+T->uapi.plane
@@
struct intel_plane_state *T;
@@
-T->base.commit
+T->uapi.commit
@@
struct intel_plane_state *T;
@@
-T->base.state
+T->uapi.state
@@
struct intel_plane_state *T;
@@
-T->base.fence
+T->uapi.fence
// HW members, properties
@@
struct intel_plane_state *T;
@@
-T->base.crtc
+T->hw.crtc
@@
struct intel_plane_state *T;
@@
-T->base.fb
+T->hw.fb
@@
struct intel_plane_state *T;
@@
-T->base.alpha
+T->hw.alpha
@@
struct intel_plane_state *T;
@@
-T->base.pixel_blend_mode
+T->hw.pixel_blend_mode
@@
struct intel_plane_state *T;
@@
-T->base.rotation
+T->hw.rotation
@@
struct intel_plane_state *T;
@@
-T->base.color_encoding
+T->hw.color_encoding
@@
struct intel_plane_state *T;
@@
-T->base.color_range
+T->hw.color_range
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 52 +--
drivers/gpu/drm/i915/display/intel_display.c | 378 +++++++++---------
.../drm/i915/display/intel_display_types.h | 7 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 20 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 190 ++++-----
drivers/gpu/drm/i915/intel_pm.c | 93 ++---
8 files changed, 379 insertions(+), 373 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 266d0ce9d03d..4783d7ff4fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -296,10 +296,10 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->is_yuv &&
- plane_state->base.fb->format->num_planes > 1) {
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ if (plane_state && plane_state->hw.fb &&
+ plane_state->hw.fb->format->is_yuv &&
+ plane_state->hw.fb->format->num_planes > 1) {
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index ca82167d4ce3..01937896d69c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
return ERR_PTR(-ENOMEM);
}
- __drm_atomic_helper_plane_reset(&plane->base, &plane_state->base);
+ __drm_atomic_helper_plane_reset(&plane->base, &plane_state->uapi);
plane_state->scaler_id = -1;
return plane;
@@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane *plane)
{
- struct drm_plane_state *state;
struct intel_plane_state *intel_state;
- intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
+ intel_state = to_intel_plane_state(plane->state);
+ intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
if (!intel_state)
return NULL;
- state = &intel_state->base;
-
- __drm_atomic_helper_plane_duplicate_state(plane, state);
+ __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
intel_state->vma = NULL;
intel_state->flags = 0;
- return state;
+ return &intel_state->uapi;
}
/**
@@ -110,18 +108,20 @@ void
intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
- WARN_ON(to_intel_plane_state(state)->vma);
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
- drm_atomic_helper_plane_destroy_state(plane, state);
+ __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
+ kfree(plane_state);
}
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
cpp = fb->format->cpp[0];
@@ -143,17 +143,17 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *new_plane_state)
{
- struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
- const struct drm_framebuffer *fb = new_plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
- if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+ if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
ret = plane->check_plane(new_crtc_state, new_plane_state);
@@ -161,18 +161,18 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
return ret;
/* FIXME pre-g4x don't work like this */
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
new_crtc_state->active_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
drm_format_info_is_yuv_semiplanar(fb->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
- if (new_plane_state->base.visible &&
+ if (new_plane_state->uapi.visible &&
fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
- if (new_plane_state->base.visible || old_plane_state->base.visible)
+ if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
new_crtc_state->update_planes |= BIT(plane->id);
new_crtc_state->data_rate[plane->id] =
@@ -186,11 +186,11 @@ static struct intel_crtc *
get_crtc_from_states(const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
- if (new_plane_state->base.crtc)
- return to_intel_crtc(new_plane_state->base.crtc);
+ if (new_plane_state->uapi.crtc)
+ return to_intel_crtc(new_plane_state->uapi.crtc);
- if (old_plane_state->base.crtc)
- return to_intel_crtc(old_plane_state->base.crtc);
+ if (old_plane_state->uapi.crtc)
+ return to_intel_crtc(old_plane_state->uapi.crtc);
return NULL;
}
@@ -210,7 +210,7 @@ static int intel_plane_atomic_check(struct drm_plane *_plane,
const struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
if (!crtc)
return 0;
@@ -319,7 +319,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->base.visible) {
+ if (new_plane_state->uapi.visible) {
intel_update_plane(plane, new_crtc_state, new_plane_state);
} else if (new_plane_state->planar_slave) {
struct intel_plane *master =
@@ -359,7 +359,7 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
!(update_mask & BIT(plane->id)))
continue;
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
intel_update_plane(plane, new_crtc_state, new_plane_state);
else
intel_disable_plane(plane, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c2debb402844..0ee542840c70 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2056,7 +2056,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
return INTEL_GEN(dev_priv) < 4 ||
@@ -2192,7 +2192,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
int color_plane)
{
- const struct drm_framebuffer *fb = state->base.fb;
+ const struct drm_framebuffer *fb = state->hw.fb;
unsigned int cpp = fb->format->cpp[color_plane];
unsigned int pitch = state->color_plane[color_plane].stride;
@@ -2293,8 +2293,8 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
int color_plane,
u32 old_offset, u32 new_offset)
{
- return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
- state->base.rotation,
+ return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
+ state->hw.rotation,
state->color_plane[color_plane].stride,
old_offset, new_offset);
}
@@ -2368,10 +2368,10 @@ static u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane)
{
- struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
+ struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
- const struct drm_framebuffer *fb = state->base.fb;
- unsigned int rotation = state->base.rotation;
+ const struct drm_framebuffer *fb = state->hw.fb;
+ unsigned int rotation = state->hw.rotation;
int pitch = state->color_plane[color_plane].stride;
u32 alignment;
@@ -2556,9 +2556,9 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int i;
/* We don't want to deal with remapping with cursors */
@@ -2596,16 +2596,16 @@ bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
u32 stride, max_stride;
/*
* No remapping for invisible planes since we don't have
* an actual source viewport to remap.
*/
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return false;
if (!intel_plane_can_remap(plane_state))
@@ -2791,11 +2791,11 @@ static void
intel_plane_remap_gtt(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- struct drm_framebuffer *fb = plane_state->base.fb;
+ to_i915(plane_state->uapi.plane->dev);
+ struct drm_framebuffer *fb = plane_state->hw.fb;
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
struct intel_rotation_info *info = &plane_state->view.rotated;
- unsigned int rotation = plane_state->base.rotation;
+ unsigned int rotation = plane_state->hw.rotation;
int i, num_planes = fb->format->num_planes;
unsigned int tile_size = intel_tile_size(dev_priv);
unsigned int src_x, src_y;
@@ -2806,20 +2806,20 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state)
plane_state->view.type = drm_rotation_90_or_270(rotation) ?
I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
- src_x = plane_state->base.src.x1 >> 16;
- src_y = plane_state->base.src.y1 >> 16;
- src_w = drm_rect_width(&plane_state->base.src) >> 16;
- src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
+ src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
WARN_ON(is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
- drm_rect_translate(&plane_state->base.src,
+ drm_rect_translate(&plane_state->uapi.src,
-(src_x << 16), -(src_y << 16));
/* Rotate src coordinates to match rotated GTT view */
if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
+ drm_rect_rotate(&plane_state->uapi.src,
src_w << 16, src_h << 16,
DRM_MODE_ROTATE_270);
@@ -2904,8 +2904,8 @@ static int
intel_plane_compute_gtt(struct intel_plane_state *plane_state)
{
const struct intel_framebuffer *fb =
- to_intel_framebuffer(plane_state->base.fb);
- unsigned int rotation = plane_state->base.rotation;
+ to_intel_framebuffer(plane_state->hw.fb);
+ unsigned int rotation = plane_state->hw.rotation;
int i, num_planes;
if (!fb)
@@ -2942,7 +2942,7 @@ intel_plane_compute_gtt(struct intel_plane_state *plane_state)
/* Rotate src coordinates to match rotated GTT view */
if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
+ drm_rect_rotate(&plane_state->uapi.src,
fb->base.width << 16, fb->base.height << 16,
DRM_MODE_ROTATE_270);
@@ -3110,9 +3110,9 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state,
bool visible)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- plane_state->base.visible = visible;
+ plane_state->uapi.visible = visible;
if (visible)
crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
@@ -3207,7 +3207,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
continue;
if (intel_plane_ggtt_offset(state) == plane_config->base) {
- fb = state->base.fb;
+ fb = state->hw.fb;
drm_framebuffer_get(fb);
goto valid_fb;
}
@@ -3225,11 +3225,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
return;
valid_fb:
- intel_state->base.rotation = plane_config->rotation;
+ intel_state->hw.rotation = plane_config->rotation;
intel_fill_fb_ggtt_view(&intel_state->view, fb,
- intel_state->base.rotation);
+ intel_state->hw.rotation);
intel_state->color_plane[0].stride =
- intel_fb_pitch(fb, 0, intel_state->base.rotation);
+ intel_fb_pitch(fb, 0, intel_state->hw.rotation);
mutex_lock(&dev->struct_mutex);
intel_state->vma =
@@ -3259,8 +3259,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
plane_state->crtc_w = fb->width;
plane_state->crtc_h = fb->height;
- intel_state->base.src = drm_plane_state_src(plane_state);
- intel_state->base.dst = drm_plane_state_dest(plane_state);
+ intel_state->uapi.src = drm_plane_state_src(plane_state);
+ intel_state->uapi.dst = drm_plane_state_dest(plane_state);
if (plane_config->tiling)
dev_priv->preserve_bios_swizzle = true;
@@ -3358,7 +3358,7 @@ static int icl_max_plane_height(void)
static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
int main_x, int main_y, u32 main_offset)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int hsub = fb->format->hsub;
int vsub = fb->format->vsub;
int aux_x = plane_state->color_plane[1].x;
@@ -3395,13 +3395,13 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
static int skl_check_main_surface(struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int x = plane_state->base.src.x1 >> 16;
- int y = plane_state->base.src.y1 >> 16;
- int w = drm_rect_width(&plane_state->base.src) >> 16;
- int h = drm_rect_height(&plane_state->base.src) >> 16;
+ struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
+ int x = plane_state->uapi.src.x1 >> 16;
+ int y = plane_state->uapi.src.y1 >> 16;
+ int w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ int h = drm_rect_height(&plane_state->uapi.src) >> 16;
int max_width;
int max_height;
u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
@@ -3484,23 +3484,23 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* Put the final coordinates back so that the src
* coordinate checks will see the right values.
*/
- drm_rect_translate(&plane_state->base.src,
- (x << 16) - plane_state->base.src.x1,
- (y << 16) - plane_state->base.src.y1);
+ drm_rect_translate(&plane_state->uapi.src,
+ (x << 16) - plane_state->uapi.src.x1,
+ (y << 16) - plane_state->uapi.src.y1);
return 0;
}
static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
int max_width = skl_max_plane_width(fb, 1, rotation);
int max_height = 4096;
- int x = plane_state->base.src.x1 >> 17;
- int y = plane_state->base.src.y1 >> 17;
- int w = drm_rect_width(&plane_state->base.src) >> 17;
- int h = drm_rect_height(&plane_state->base.src) >> 17;
+ int x = plane_state->uapi.src.x1 >> 17;
+ int y = plane_state->uapi.src.y1 >> 17;
+ int w = drm_rect_width(&plane_state->uapi.src) >> 17;
+ int h = drm_rect_height(&plane_state->uapi.src) >> 17;
u32 offset;
intel_add_fb_offsets(&x, &y, plane_state, 1);
@@ -3522,9 +3522,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- int src_x = plane_state->base.src.x1 >> 16;
- int src_y = plane_state->base.src.y1 >> 16;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int src_x = plane_state->uapi.src.x1 >> 16;
+ int src_y = plane_state->uapi.src.y1 >> 16;
int hsub = fb->format->hsub;
int vsub = fb->format->vsub;
int x = src_x / hsub;
@@ -3543,14 +3543,14 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
/*
@@ -3627,9 +3627,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
dspcntr = DISPLAY_PLANE_ENABLE;
@@ -3681,7 +3681,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
+ to_i915(plane_state->uapi.plane->dev);
int src_x, src_y;
u32 offset;
int ret;
@@ -3690,11 +3690,11 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
- src_x = plane_state->base.src.x1 >> 16;
- src_y = plane_state->base.src.y1 >> 16;
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
@@ -3708,15 +3708,15 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
* Put the final coordinates back so that the src
* coordinate checks will see the right values.
*/
- drm_rect_translate(&plane_state->base.src,
- (src_x << 16) - plane_state->base.src.x1,
- (src_y << 16) - plane_state->base.src.y1);
+ drm_rect_translate(&plane_state->uapi.src,
+ (src_x << 16) - plane_state->uapi.src.x1,
+ (src_y << 16) - plane_state->uapi.src.y1);
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
- unsigned int rotation = plane_state->base.rotation;
- int src_w = drm_rect_width(&plane_state->base.src) >> 16;
- int src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
if (rotation & DRM_MODE_ROTATE_180) {
src_x += src_w - 1;
@@ -3753,14 +3753,14 @@ static int
i9xx_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
int ret;
ret = chv_plane_check_rotation(plane_state);
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
&crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
@@ -3773,7 +3773,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
ret = intel_plane_check_src_coordinates(plane_state);
@@ -3794,10 +3794,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
u32 linear_offset;
int x = plane_state->color_plane[0].x;
int y = plane_state->color_plane[0].y;
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
- int crtc_w = drm_rect_width(&plane_state->base.dst);
- int crtc_h = drm_rect_height(&plane_state->base.dst);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ int crtc_h = drm_rect_height(&plane_state->uapi.dst);
unsigned long irqflags;
u32 dspaddr_offset;
u32 dspcntr;
@@ -3967,8 +3967,8 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
u32 skl_plane_stride(const struct intel_plane_state *plane_state,
int color_plane)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
u32 stride = plane_state->color_plane[color_plane].stride;
if (color_plane >= fb->format->num_planes)
@@ -4037,10 +4037,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
{
- if (!plane_state->base.fb->format->has_alpha)
+ if (!plane_state->hw.fb->format->has_alpha)
return PLANE_CTL_ALPHA_DISABLE;
- switch (plane_state->base.pixel_blend_mode) {
+ switch (plane_state->hw.pixel_blend_mode) {
case DRM_MODE_BLEND_PIXEL_NONE:
return PLANE_CTL_ALPHA_DISABLE;
case DRM_MODE_BLEND_PREMULTI:
@@ -4048,17 +4048,17 @@ static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
case DRM_MODE_BLEND_COVERAGE:
return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
default:
- MISSING_CASE(plane_state->base.pixel_blend_mode);
+ MISSING_CASE(plane_state->hw.pixel_blend_mode);
return PLANE_CTL_ALPHA_DISABLE;
}
}
static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
{
- if (!plane_state->base.fb->format->has_alpha)
+ if (!plane_state->hw.fb->format->has_alpha)
return PLANE_COLOR_ALPHA_DISABLE;
- switch (plane_state->base.pixel_blend_mode) {
+ switch (plane_state->hw.pixel_blend_mode) {
case DRM_MODE_BLEND_PIXEL_NONE:
return PLANE_COLOR_ALPHA_DISABLE;
case DRM_MODE_BLEND_PREMULTI:
@@ -4066,7 +4066,7 @@ static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state
case DRM_MODE_BLEND_COVERAGE:
return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
default:
- MISSING_CASE(plane_state->base.pixel_blend_mode);
+ MISSING_CASE(plane_state->hw.pixel_blend_mode);
return PLANE_COLOR_ALPHA_DISABLE;
}
}
@@ -4151,9 +4151,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 plane_ctl;
@@ -4163,10 +4163,10 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl |= skl_plane_ctl_alpha(plane_state);
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+ if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
}
@@ -4207,21 +4207,21 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
u32 plane_color_ctl = 0;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+ if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
else
plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
} else if (fb->format->is_yuv) {
plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
@@ -5504,11 +5504,11 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
struct intel_plane *intel_plane =
- to_intel_plane(plane_state->base.plane);
+ to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
- struct drm_framebuffer *fb = plane_state->base.fb;
+ struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
- bool force_detach = !fb || !plane_state->base.visible;
+ bool force_detach = !fb || !plane_state->uapi.visible;
bool need_scaler = false;
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
@@ -5519,10 +5519,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
ret = skl_update_scaler(crtc_state, force_detach,
drm_plane_index(&intel_plane->base),
&plane_state->scaler_id,
- drm_rect_width(&plane_state->base.src) >> 16,
- drm_rect_height(&plane_state->base.src) >> 16,
- drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst),
+ drm_rect_width(&plane_state->uapi.src) >> 16,
+ drm_rect_height(&plane_state->uapi.src) >> 16,
+ drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_height(&plane_state->uapi.dst),
fb ? fb->format : NULL, need_scaler);
if (ret || plane_state->scaler_id < 0)
@@ -5940,7 +5940,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* So disable underrun reporting before all the planes get disabled.
*/
if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
- (modeset || !new_primary_state->base.visible))
+ (modeset || !new_primary_state->uapi.visible))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
}
@@ -6027,7 +6027,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
intel_disable_plane(plane, new_crtc_state);
- if (old_plane_state->base.visible)
+ if (old_plane_state->uapi.visible)
fb_bits |= plane->frontbuffer_bit;
}
@@ -7025,7 +7025,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
- if (plane_state->base.visible)
+ if (plane_state->uapi.visible)
intel_plane_disable_noatomic(intel_crtc, plane);
}
@@ -10537,8 +10537,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
u32 base;
@@ -10551,17 +10551,17 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
/* ILK+ do this automagically */
if (HAS_GMCH(dev_priv) &&
- plane_state->base.rotation & DRM_MODE_ROTATE_180)
- base += (drm_rect_height(&plane_state->base.dst) *
- drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
+ plane_state->hw.rotation & DRM_MODE_ROTATE_180)
+ base += (drm_rect_height(&plane_state->uapi.dst) *
+ drm_rect_width(&plane_state->uapi.dst) - 1) * fb->format->cpp[0];
return base;
}
static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
{
- int x = plane_state->base.dst.x1;
- int y = plane_state->base.dst.y1;
+ int x = plane_state->uapi.dst.x1;
+ int y = plane_state->uapi.dst.y1;
u32 pos = 0;
if (x < 0) {
@@ -10582,9 +10582,9 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
{
const struct drm_mode_config *config =
- &plane_state->base.plane->dev->mode_config;
- int width = drm_rect_width(&plane_state->base.dst);
- int height = drm_rect_height(&plane_state->base.dst);
+ &plane_state->uapi.plane->dev->mode_config;
+ int width = drm_rect_width(&plane_state->uapi.dst);
+ int height = drm_rect_height(&plane_state->uapi.dst);
return width > 0 && width <= config->cursor_width &&
height > 0 && height <= config->cursor_height;
@@ -10600,11 +10600,11 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
- src_x = plane_state->base.src.x1 >> 16;
- src_y = plane_state->base.src.y1 >> 16;
+ src_x = plane_state->uapi.src.x1 >> 16;
+ src_y = plane_state->uapi.src.y1 >> 16;
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
@@ -10623,7 +10623,7 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
static int intel_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -10631,7 +10631,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
&crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
@@ -10640,14 +10640,14 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return ret;
/* Use the unclipped src/dst rectangles, which we program to hw */
- plane_state->base.src = drm_plane_state_src(&plane_state->base);
- plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
+ plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
+ plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
ret = intel_cursor_check_surface(plane_state);
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
ret = intel_plane_check_src_coordinates(plane_state);
@@ -10685,7 +10685,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
{
- int width = drm_rect_width(&plane_state->base.dst);
+ int width = drm_rect_width(&plane_state->uapi.dst);
/*
* 845g/865g are only limited by the width of their cursors,
@@ -10697,7 +10697,7 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
static int i845_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int ret;
ret = intel_check_cursor(crtc_state, plane_state);
@@ -10711,12 +10711,12 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
/* Check for which cursor types we support */
if (!i845_cursor_size_ok(plane_state)) {
DRM_DEBUG("Cursor dimension %dx%d not supported\n",
- drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_height(&plane_state->uapi.dst));
return -EINVAL;
}
- WARN_ON(plane_state->base.visible &&
+ WARN_ON(plane_state->uapi.visible &&
plane_state->color_plane[0].stride != fb->pitches[0]);
switch (fb->pitches[0]) {
@@ -10744,9 +10744,9 @@ static void i845_update_cursor(struct intel_plane *plane,
u32 cntl = 0, base = 0, pos = 0, size = 0;
unsigned long irqflags;
- if (plane_state && plane_state->base.visible) {
- unsigned int width = drm_rect_width(&plane_state->base.src);
- unsigned int height = drm_rect_height(&plane_state->base.dst);
+ if (plane_state && plane_state->uapi.visible) {
+ unsigned int width = drm_rect_width(&plane_state->uapi.src);
+ unsigned int height = drm_rect_height(&plane_state->uapi.dst);
cntl = plane_state->ctl |
i845_cursor_ctl_crtc(crtc_state);
@@ -10842,13 +10842,13 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
+ to_i915(plane_state->uapi.plane->dev);
u32 cntl = 0;
if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
- switch (drm_rect_width(&plane_state->base.dst)) {
+ switch (drm_rect_width(&plane_state->uapi.dst)) {
case 64:
cntl |= MCURSOR_MODE_64_ARGB_AX;
break;
@@ -10859,11 +10859,11 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
cntl |= MCURSOR_MODE_256_ARGB_AX;
break;
default:
- MISSING_CASE(drm_rect_width(&plane_state->base.dst));
+ MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
return 0;
}
- if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
+ if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
cntl |= MCURSOR_ROTATE_180;
return cntl;
@@ -10872,9 +10872,9 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- int width = drm_rect_width(&plane_state->base.dst);
- int height = drm_rect_height(&plane_state->base.dst);
+ to_i915(plane_state->uapi.plane->dev);
+ int width = drm_rect_width(&plane_state->uapi.dst);
+ int height = drm_rect_height(&plane_state->uapi.dst);
if (!intel_cursor_size_ok(plane_state))
return false;
@@ -10896,7 +10896,7 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
* cursors.
*/
if (HAS_CUR_FBC(dev_priv) &&
- plane_state->base.rotation & DRM_MODE_ROTATE_0) {
+ plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
if (height < 8 || height > width)
return false;
} else {
@@ -10910,9 +10910,9 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
int ret;
@@ -10927,19 +10927,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
/* Check for which cursor types we support */
if (!i9xx_cursor_size_ok(plane_state)) {
DRM_DEBUG("Cursor dimension %dx%d not supported\n",
- drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_width(&plane_state->uapi.dst),
+ drm_rect_height(&plane_state->uapi.dst));
return -EINVAL;
}
- WARN_ON(plane_state->base.visible &&
+ WARN_ON(plane_state->uapi.visible &&
plane_state->color_plane[0].stride != fb->pitches[0]);
if (fb->pitches[0] !=
- drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
+ drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
fb->pitches[0],
- drm_rect_width(&plane_state->base.dst));
+ drm_rect_width(&plane_state->uapi.dst));
return -EINVAL;
}
@@ -10954,7 +10954,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
* Refuse the put the cursor into that compromised position.
*/
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
- plane_state->base.visible && plane_state->base.dst.x1 < 0) {
+ plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
return -EINVAL;
}
@@ -10973,9 +10973,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
unsigned long irqflags;
- if (plane_state && plane_state->base.visible) {
- unsigned width = drm_rect_width(&plane_state->base.dst);
- unsigned height = drm_rect_height(&plane_state->base.dst);
+ if (plane_state && plane_state->uapi.visible) {
+ unsigned width = drm_rect_width(&plane_state->uapi.dst);
+ unsigned height = drm_rect_height(&plane_state->uapi.dst);
cntl = plane_state->ctl |
i9xx_cursor_ctl_crtc(crtc_state);
@@ -11513,18 +11513,18 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
struct intel_plane_state *new)
{
/* Update watermarks on tiling or size changes. */
- if (new->base.visible != cur->base.visible)
+ if (new->uapi.visible != cur->uapi.visible)
return true;
- if (!cur->base.fb || !new->base.fb)
+ if (!cur->hw.fb || !new->hw.fb)
return false;
- if (cur->base.fb->modifier != new->base.fb->modifier ||
- cur->base.rotation != new->base.rotation ||
- drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
- drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
- drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
- drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
+ if (cur->hw.fb->modifier != new->hw.fb->modifier ||
+ cur->hw.rotation != new->hw.rotation ||
+ drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
+ drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
+ drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
+ drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
return true;
return false;
@@ -11532,10 +11532,10 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
static bool needs_scaling(const struct intel_plane_state *state)
{
- int src_w = drm_rect_width(&state->base.src) >> 16;
- int src_h = drm_rect_height(&state->base.src) >> 16;
- int dst_w = drm_rect_width(&state->base.dst);
- int dst_h = drm_rect_height(&state->base.dst);
+ int src_w = drm_rect_width(&state->uapi.src) >> 16;
+ int src_h = drm_rect_height(&state->uapi.src) >> 16;
+ int dst_w = drm_rect_width(&state->uapi.dst);
+ int dst_h = drm_rect_height(&state->uapi.dst);
return (src_w != dst_w || src_h != dst_h);
}
@@ -11546,7 +11546,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
struct intel_plane_state *plane_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
bool mode_changed = needs_modeset(crtc_state);
bool was_crtc_enabled = old_crtc_state->hw.active;
@@ -11560,8 +11560,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
return ret;
}
- was_visible = old_plane_state->base.visible;
- visible = plane_state->base.visible;
+ was_visible = old_plane_state->uapi.visible;
+ visible = plane_state->uapi.visible;
if (!was_crtc_enabled && WARN_ON(was_visible))
was_visible = false;
@@ -11577,7 +11577,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
* only combine the results from all planes in the current place?
*/
if (!is_crtc_enabled) {
- plane_state->base.visible = visible = false;
+ plane_state->uapi.visible = visible = false;
crtc_state->active_planes &= ~BIT(plane->id);
crtc_state->data_rate[plane->id] = 0;
}
@@ -11736,7 +11736,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
continue;
plane_state->planar_linked_plane = NULL;
- if (plane_state->planar_slave && !plane_state->base.visible) {
+ if (plane_state->planar_slave && !plane_state->uapi.visible) {
crtc_state->active_planes &= ~BIT(plane->id);
crtc_state->update_planes |= BIT(plane->id);
}
@@ -12075,14 +12075,14 @@ static const char *output_formats(enum intel_output_format format)
static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
struct drm_format_name_buf format_name;
if (!fb) {
DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
plane->base.base.id, plane->base.name,
- yesno(plane_state->base.visible));
+ yesno(plane_state->uapi.visible));
return;
}
@@ -12090,13 +12090,13 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
plane->base.base.id, plane->base.name,
fb->base.id, fb->width, fb->height,
drm_get_format_name(fb->format->format, &format_name),
- yesno(plane_state->base.visible));
+ yesno(plane_state->uapi.visible));
DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
- plane_state->base.rotation, plane_state->scaler_id);
- if (plane_state->base.visible)
+ plane_state->hw.rotation, plane_state->scaler_id);
+ if (plane_state->uapi.visible)
DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
- DRM_RECT_FP_ARG(&plane_state->base.src),
- DRM_RECT_ARG(&plane_state->base.dst));
+ DRM_RECT_FP_ARG(&plane_state->uapi.src),
+ DRM_RECT_ARG(&plane_state->uapi.dst));
}
static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
@@ -13253,7 +13253,7 @@ intel_verify_planes(struct intel_atomic_state *state)
for_each_new_intel_plane_in_state(state, plane,
plane_state, i)
assert_plane(plane, plane_state->planar_slave ||
- plane_state->base.visible);
+ plane_state->uapi.visible);
}
static void
@@ -14247,8 +14247,8 @@ static void intel_atomic_track_fbs(struct intel_atomic_state *state)
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i)
- intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
- to_intel_frontbuffer(new_plane_state->base.fb),
+ intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
+ to_intel_frontbuffer(new_plane_state->hw.fb),
plane->frontbuffer_bit);
}
@@ -14405,9 +14405,9 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct drm_framebuffer *fb = plane_state->base.fb;
+ struct drm_framebuffer *fb = plane_state->hw.fb;
struct i915_vma *vma;
if (plane->id == PLANE_CURSOR &&
@@ -14472,9 +14472,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(new_plane_state->base.state);
+ to_intel_atomic_state(new_plane_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(plane->dev);
- struct drm_framebuffer *fb = new_plane_state->base.fb;
+ struct drm_framebuffer *fb = new_plane_state->hw.fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
int ret;
@@ -14505,9 +14505,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
}
- if (new_plane_state->base.fence) { /* explicit fencing */
+ if (new_plane_state->uapi.fence) { /* explicit fencing */
ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
- new_plane_state->base.fence,
+ new_plane_state->uapi.fence,
I915_FENCE_TIMEOUT,
GFP_KERNEL);
if (ret < 0)
@@ -14537,7 +14537,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
fb_obj_bump_render_priority(obj);
intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
- if (!new_plane_state->base.fence) { /* implicit fencing */
+ if (!new_plane_state->uapi.fence) { /* implicit fencing */
struct dma_fence *fence;
ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
@@ -14549,11 +14549,13 @@ intel_prepare_plane_fb(struct drm_plane *plane,
fence = dma_resv_get_excl_rcu(obj->base.resv);
if (fence) {
- add_rps_boost_after_vblank(new_plane_state->base.crtc, fence);
+ add_rps_boost_after_vblank(new_plane_state->hw.crtc,
+ fence);
dma_fence_put(fence);
}
} else {
- add_rps_boost_after_vblank(new_plane_state->base.crtc, new_plane_state->base.fence);
+ add_rps_boost_after_vblank(new_plane_state->hw.crtc,
+ new_plane_state->uapi.fence);
}
/*
@@ -14588,7 +14590,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
struct intel_plane_state *old_plane_state =
to_intel_plane_state(_old_plane_state);
struct intel_atomic_state *intel_state =
- to_intel_atomic_state(old_plane_state->base.state);
+ to_intel_atomic_state(old_plane_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(plane->dev);
if (intel_state->rps_interactive) {
@@ -16531,7 +16533,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
- if (plane_state->base.visible &&
+ if (plane_state->uapi.visible &&
plane->base.type != DRM_PLANE_TYPE_PRIMARY)
intel_plane_disable_noatomic(crtc, plane);
}
@@ -16873,7 +16875,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
* FIXME don't have the fb yet, so can't
* use intel_plane_data_rate() :(
*/
- if (plane_state->base.visible)
+ if (plane_state->uapi.visible)
crtc_state->data_rate[plane->id] =
4 * crtc_state->pixel_rate;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9401915bc93a..c6c49aa8c172 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -515,7 +515,10 @@ struct intel_atomic_state {
};
struct intel_plane_state {
- struct drm_plane_state base;
+ union {
+ struct drm_plane_state uapi;
+ struct drm_plane_state hw;
+ };
struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
@@ -1124,7 +1127,7 @@ struct cxsr_latency {
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
-#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
+#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
struct intel_hdmi {
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c6cc3775f3b8..92c7eb243559 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -430,7 +430,7 @@ static bool multiple_pipes_ok(struct intel_crtc *crtc,
if (!no_fbc_on_multiple_pipes(dev_priv))
return true;
- if (plane_state->base.visible)
+ if (plane_state->uapi.visible)
fbc->visible_pipes_mask |= (1 << pipe);
else
fbc->visible_pipes_mask &= ~(1 << pipe);
@@ -662,7 +662,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
- struct drm_framebuffer *fb = plane_state->base.fb;
+ struct drm_framebuffer *fb = plane_state->hw.fb;
cache->vma = NULL;
cache->flags = 0;
@@ -671,20 +671,20 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
- cache->plane.rotation = plane_state->base.rotation;
+ cache->plane.rotation = plane_state->hw.rotation;
/*
* Src coordinates are already rotated by 270 degrees for
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
- cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
- cache->plane.visible = plane_state->base.visible;
+ cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+ cache->plane.visible = plane_state->uapi.visible;
cache->plane.adjusted_x = plane_state->color_plane[0].x;
cache->plane.adjusted_y = plane_state->color_plane[0].y;
- cache->plane.y = plane_state->base.src.y1 >> 16;
+ cache->plane.y = plane_state->uapi.src.y1 >> 16;
- cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
+ cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
if (!cache->plane.visible)
return;
@@ -1047,12 +1047,12 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
* to pipe or plane A. */
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
if (!plane->has_fbc)
continue;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
continue;
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 5efef9babadb..b27a1e8a83f9 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -669,8 +669,8 @@ static void update_colorkey(struct intel_overlay *overlay,
if (overlay->color_key_enabled)
flags |= DST_KEY_ENABLE;
- if (state->base.visible)
- format = state->base.fb->format->format;
+ if (state->uapi.visible)
+ format = state->hw.fb->format->format;
switch (format) {
case DRM_FORMAT_C8:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 526a9366b682..ce193367b96b 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -240,9 +240,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
int intel_plane_check_stride(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
u32 stride, max_stride;
/*
@@ -252,7 +252,7 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
* kick in due the plane being invisible.
*/
if (intel_plane_can_remap(plane_state) &&
- !plane_state->base.visible)
+ !plane_state->uapi.visible)
return 0;
/* FIXME other color planes? */
@@ -272,10 +272,10 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- struct drm_rect *src = &plane_state->base.src;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
u32 src_x, src_y, src_w, src_h, hsub, vsub;
- bool rotated = drm_rotation_90_or_270(plane_state->base.rotation);
+ bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
/*
* Hardware doesn't handle subpixel coordinates.
@@ -349,24 +349,24 @@ skl_program_scaler(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
int scaler_id = plane_state->scaler_id;
const struct intel_scaler *scaler =
&crtc_state->scaler_state.scalers[scaler_id];
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
- u32 crtc_w = drm_rect_width(&plane_state->base.dst);
- u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
u16 y_hphase, uv_rgb_hphase;
u16 y_vphase, uv_rgb_vphase;
int hscale, vscale;
- hscale = drm_rect_calc_hscale(&plane_state->base.src,
- &plane_state->base.dst,
+ hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
+ &plane_state->uapi.dst,
0, INT_MAX);
- vscale = drm_rect_calc_vscale(&plane_state->base.src,
- &plane_state->base.dst,
+ vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
+ &plane_state->uapi.dst,
0, INT_MAX);
/* TODO: handle sub-pixel coordinates */
@@ -495,10 +495,10 @@ icl_program_input_csc(struct intel_plane *plane,
};
const u16 *csc;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
- csc = input_csc_matrix[plane_state->base.color_encoding];
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ csc = input_csc_matrix[plane_state->hw.color_encoding];
else
- csc = input_csc_matrix_lr[plane_state->base.color_encoding];
+ csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
GOFF(csc[1]));
@@ -512,7 +512,7 @@ icl_program_input_csc(struct intel_plane *plane,
I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
PREOFF_YUV_TO_RGB_HI);
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
else
I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
@@ -537,15 +537,15 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
u32 aux_stride = skl_plane_stride(plane_state, 1);
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
u32 x = plane_state->color_plane[color_plane].x;
u32 y = plane_state->color_plane[color_plane].y;
- u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
- u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
struct intel_plane *linked = plane_state->planar_linked_plane;
- const struct drm_framebuffer *fb = plane_state->base.fb;
- u8 alpha = plane_state->base.alpha >> 8;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
@@ -719,9 +719,9 @@ static void i9xx_plane_linear_gamma(u16 gamma[8])
static void
chv_update_csc(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
/*
* |r| | c0 c1 c2 | |cr|
@@ -747,7 +747,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
0, 4096, 7601,
},
};
- const s16 *csc = csc_matrix[plane_state->base.color_encoding];
+ const s16 *csc = csc_matrix[plane_state->hw.color_encoding];
/* Seems RGB data bypasses the CSC always */
if (!fb->format->is_yuv)
@@ -778,15 +778,15 @@ chv_update_csc(const struct intel_plane_state *plane_state)
static void
vlv_update_clrc(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
int contrast, brightness, sh_scale, sh_sin, sh_cos;
if (fb->format->is_yuv &&
- plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
+ plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
/*
* Expand limited range to full range:
* Contrast is applied first and is used to expand Y range.
@@ -827,8 +827,8 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 sprctl;
@@ -873,7 +873,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
return 0;
}
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+ if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SP_YUV_FORMAT_BT709;
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -893,9 +893,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void vlv_update_gamma(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
u16 gamma[8];
@@ -927,10 +927,10 @@ vlv_update_plane(struct intel_plane *plane,
u32 sprsurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
- u32 crtc_w = drm_rect_width(&plane_state->base.dst);
- u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
u32 x = plane_state->color_plane[0].x;
u32 y = plane_state->color_plane[0].y;
unsigned long irqflags;
@@ -1037,9 +1037,9 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 sprctl;
@@ -1074,10 +1074,10 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
sprctl |= SPRITE_INT_GAMMA_DISABLE;
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+ if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -1107,7 +1107,7 @@ static void ivb_sprite_linear_gamma(u16 gamma[18])
static void ivb_update_gamma(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
u16 gamma[18];
@@ -1143,14 +1143,14 @@ ivb_update_plane(struct intel_plane *plane,
u32 sprsurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
- u32 crtc_w = drm_rect_width(&plane_state->base.dst);
- u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
u32 x = plane_state->color_plane[0].x;
u32 y = plane_state->color_plane[0].y;
- u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
- u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
u32 sprctl, sprscale = 0;
unsigned long irqflags;
@@ -1271,9 +1271,9 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 dvscntr;
@@ -1306,10 +1306,10 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
return 0;
}
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+ if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
dvscntr |= DVS_YUV_FORMAT_BT709;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -1328,9 +1328,9 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void g4x_update_gamma(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[8];
int i;
@@ -1360,9 +1360,9 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
static void ilk_update_gamma(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[17];
int i;
@@ -1396,14 +1396,14 @@ g4x_update_plane(struct intel_plane *plane,
u32 dvssurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- int crtc_x = plane_state->base.dst.x1;
- int crtc_y = plane_state->base.dst.y1;
- u32 crtc_w = drm_rect_width(&plane_state->base.dst);
- u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+ u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
u32 x = plane_state->color_plane[0].x;
u32 y = plane_state->color_plane[0].y;
- u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
- u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+ u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
u32 dvscntr, dvsscale = 0;
unsigned long irqflags;
@@ -1511,9 +1511,9 @@ static int
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- const struct drm_rect *src = &plane_state->base.src;
- const struct drm_rect *dst = &plane_state->base.dst;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_rect *src = &plane_state->uapi.src;
+ const struct drm_rect *dst = &plane_state->uapi.dst;
int src_x, src_w, src_h, crtc_w, crtc_h;
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -1572,13 +1572,13 @@ static int
g4x_sprite_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
int min_scale = DRM_PLANE_HELPER_NO_SCALING;
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
- if (intel_fb_scalable(plane_state->base.fb)) {
+ if (intel_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
@@ -1588,7 +1588,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
}
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
&crtc_state->uapi,
min_scale, max_scale,
true, true);
@@ -1599,7 +1599,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
ret = intel_plane_check_src_coordinates(plane_state);
@@ -1620,9 +1620,9 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- unsigned int rotation = plane_state->base.rotation;
+ unsigned int rotation = plane_state->hw.rotation;
/* CHV ignores the mirror bit when the rotate bit is set :( */
if (IS_CHERRYVIEW(dev_priv) &&
@@ -1645,7 +1645,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
&crtc_state->uapi,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
@@ -1657,7 +1657,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
ret = intel_plane_check_src_coordinates(plane_state);
@@ -1672,10 +1672,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
struct drm_format_name_buf format_name;
if (!fb)
@@ -1747,9 +1747,9 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
- int crtc_x = plane_state->base.dst.x1;
- int crtc_w = drm_rect_width(&plane_state->base.dst);
+ to_i915(plane_state->uapi.plane->dev);
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_w = drm_rect_width(&plane_state->uapi.dst);
int pipe_src_w = crtc_state->pipe_src_w;
/*
@@ -1775,9 +1775,9 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
+ int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
/* Display WA #1106 */
if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3 &&
@@ -1793,9 +1793,9 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
static int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int min_scale = DRM_PLANE_HELPER_NO_SCALING;
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
@@ -1810,7 +1810,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
max_scale = skl_max_scale(crtc_state, fb->format);
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
&crtc_state->uapi,
min_scale, max_scale,
true, true);
@@ -1821,7 +1821,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
@@ -1837,8 +1837,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
return ret;
/* HW only has 8 bits pixel precision, disable plane if invisible */
- if (!(plane_state->base.alpha >> 8))
- plane_state->base.visible = false;
+ if (!(plane_state->hw.alpha >> 8))
+ plane_state->uapi.visible = false;
plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
@@ -1857,7 +1857,7 @@ static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
const struct drm_intel_sprite_colorkey *set)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c9359981c24..33d8fc4a60aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -795,7 +795,7 @@ static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
/* FIXME check the 'enable' instead */
if (!crtc_state->hw.active)
@@ -810,9 +810,9 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
* around this problem with the watermark code.
*/
if (plane->id == PLANE_CURSOR)
- return plane_state->base.fb != NULL;
+ return plane_state->hw.fb != NULL;
else
- return plane_state->base.visible;
+ return plane_state->uapi.visible;
}
static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
@@ -1084,7 +1084,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int level)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -1097,7 +1097,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
/*
* Not 100% sure which way ELK should go here as the
@@ -1117,7 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
- width = drm_rect_width(&plane_state->base.dst);
+ width = drm_rect_width(&plane_state->uapi.dst);
if (plane->id == PLANE_CURSOR) {
wm = intel_wm_method2(clock, htotal, width, cpp, latency);
@@ -1183,7 +1183,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
enum plane_id plane_id = plane->id;
bool dirty = false;
@@ -1317,8 +1317,8 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for_each_oldnew_intel_plane_in_state(state, plane,
old_plane_state,
new_plane_state, i) {
- if (new_plane_state->base.crtc != &crtc->base &&
- old_plane_state->base.crtc != &crtc->base)
+ if (new_plane_state->hw.crtc != &crtc->base &&
+ old_plane_state->hw.crtc != &crtc->base)
continue;
if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
@@ -1590,7 +1590,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int level)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -1602,7 +1602,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
width = crtc_state->pipe_src_w;
@@ -1760,7 +1760,7 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
enum plane_id plane_id = plane->id;
int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
int level;
@@ -1838,8 +1838,8 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for_each_oldnew_intel_plane_in_state(state, plane,
old_plane_state,
new_plane_state, i) {
- if (new_plane_state->base.crtc != &crtc->base &&
- old_plane_state->base.crtc != &crtc->base)
+ if (new_plane_state->hw.crtc != &crtc->base &&
+ old_plane_state->hw.crtc != &crtc->base)
continue;
if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
@@ -2484,7 +2484,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
@@ -2493,7 +2493,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.adjusted_mode.crtc_htotal,
- drm_rect_width(&plane_state->base.dst),
+ drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
return min(method1, method2);
@@ -2516,12 +2516,12 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
method2 = ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.adjusted_mode.crtc_htotal,
- drm_rect_width(&plane_state->base.dst),
+ drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
return min(method1, method2);
}
@@ -2542,11 +2542,11 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
return ilk_wm_method2(crtc_state->pixel_rate,
crtc_state->hw.adjusted_mode.crtc_htotal,
- drm_rect_width(&plane_state->base.dst),
+ drm_rect_width(&plane_state->uapi.dst),
cpp, mem_value);
}
@@ -2560,9 +2560,10 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
- cpp = plane_state->base.fb->format->cpp[0];
+ cpp = plane_state->hw.fb->format->cpp[0];
- return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
+ return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
+ cpp);
}
static unsigned int
@@ -3106,10 +3107,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
pipe_wm->pipe_enabled = crtc_state->hw.active;
if (sprstate) {
- pipe_wm->sprites_enabled = sprstate->base.visible;
- pipe_wm->sprites_scaled = sprstate->base.visible &&
- (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
- drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
+ pipe_wm->sprites_enabled = sprstate->uapi.visible;
+ pipe_wm->sprites_scaled = sprstate->uapi.visible &&
+ (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
+ drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
}
usable_level = max_level;
@@ -4056,10 +4057,10 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
*
* n.b., src is 16.16 fixed point, dst is whole integer.
*/
- src_w = drm_rect_width(&plane_state->base.src) >> 16;
- src_h = drm_rect_height(&plane_state->base.src) >> 16;
- dst_w = drm_rect_width(&plane_state->base.dst);
- dst_h = drm_rect_height(&plane_state->base.dst);
+ src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+ dst_w = drm_rect_width(&plane_state->uapi.dst);
+ dst_h = drm_rect_height(&plane_state->uapi.dst);
fp_w_ratio = div_fixed16(src_w, dst_w);
fp_h_ratio = div_fixed16(src_h, dst_h);
@@ -4125,11 +4126,11 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
if (!intel_wm_plane_visible(crtc_state, plane_state))
continue;
- if (WARN_ON(!plane_state->base.fb))
+ if (WARN_ON(!plane_state->hw.fb))
return -EINVAL;
plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
- bpp = plane_state->base.fb->format->cpp[0] * 8;
+ bpp = plane_state->hw.fb->format->cpp[0] * 8;
if (bpp == 64)
plane_downscale = mul_fixed16(plane_downscale,
fp_9_div_8);
@@ -4161,14 +4162,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int color_plane)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
u32 data_rate;
u32 width = 0, height = 0;
uint_fixed_16_16_t down_scale_amount;
u64 rate;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
if (plane->id == PLANE_CURSOR)
@@ -4183,8 +4184,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- width = drm_rect_width(&plane_state->base.src) >> 16;
- height = drm_rect_height(&plane_state->base.src) >> 16;
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
+ height = drm_rect_height(&plane_state->uapi.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
if (color_plane == 1) {
@@ -4683,7 +4684,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
struct skl_wm_params *wp, int color_plane)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
int width;
/*
@@ -4691,11 +4692,11 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- width = drm_rect_width(&plane_state->base.src) >> 16;
+ width = drm_rect_width(&plane_state->uapi.src) >> 16;
return skl_compute_wm_params(crtc_state, width,
fb->format, fb->modifier,
- plane_state->base.rotation,
+ plane_state->hw.rotation,
skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
wp, color_plane);
}
@@ -4973,8 +4974,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
int ret;
@@ -4999,7 +5000,7 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
+ enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
int ret;
/* Watermarks calculated in master */
@@ -5007,7 +5008,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
return 0;
if (plane_state->planar_linked_plane) {
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
@@ -6032,7 +6033,7 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
enum plane_id plane_id = plane->id;
int level;
- if (plane_state->base.visible)
+ if (plane_state->uapi.visible)
continue;
for (level = 0; level < 3; level++) {
@@ -6187,7 +6188,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
enum plane_id plane_id = plane->id;
int level;
- if (plane_state->base.visible)
+ if (plane_state->uapi.visible)
continue;
for (level = 0; level < wm_state->num_levels; level++) {
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (10 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 11/24] drm/i915: Preparation for plane split Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-08 17:42 ` Ville Syrjälä
2019-10-04 11:35 ` [PATCH 13/24] drm/i915: Stop using drm_atomic_helper_check_planes() Maarten Lankhorst
` (14 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at plane_state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h | 22 +++++++++--
4 files changed, 57 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 01937896d69c..cc154cfa3381 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
intel_state->vma = NULL;
intel_state->flags = 0;
+ /* will be set in intel_plane_atomic_check_with_state() */
+ memset(&intel_state->hw, 0, sizeof(intel_state->hw));
+
return &intel_state->uapi;
}
@@ -112,6 +115,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
WARN_ON(plane_state->vma);
__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
kfree(plane_state);
}
@@ -138,15 +143,34 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state)
+{
+ plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ plane_state->hw.fb = from_plane_state->uapi.fb;
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+
+ plane_state->hw.alpha = from_plane_state->uapi.alpha;
+ plane_state->hw.pixel_blend_mode =
+ from_plane_state->uapi.pixel_blend_mode;
+ plane_state->hw.rotation = from_plane_state->uapi.rotation;
+ plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
+ plane_state->hw.color_range = from_plane_state->uapi.color_range;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
- const struct drm_framebuffer *fb = new_plane_state->hw.fb;
+ const struct drm_framebuffer *fb;
int ret;
+ intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ fb = new_plane_state->hw.fb;
+
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
@@ -373,6 +397,7 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
{
struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
+ const struct intel_plane_state *old_plane_state;
if (plane_state)
return plane_state;
@@ -381,6 +406,16 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
if (IS_ERR(plane_state))
return plane_state;
+ old_plane_state = intel_atomic_get_old_plane_state(state, plane);
+
+ /*
+ * copy HW parameters since they're zero'd on duplication, to prevent
+ * accidentally using stale state.
+ */
+ plane_state->hw = old_plane_state->hw;
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+
new_crtc_state->update_planes |= BIT(plane->id);
return plane_state;
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index cb7ef4f9eafd..fd4b96013454 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state *from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ee542840c70..ffde4b8b8be9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3267,6 +3267,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
plane_state->fb = fb;
plane_state->crtc = &intel_crtc->base;
+ intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
atomic_or(to_intel_plane(primary)->frontbuffer_bit,
&to_intel_frontbuffer(fb)->bits);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c6c49aa8c172..67644818efd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -515,10 +515,24 @@ struct intel_atomic_state {
};
struct intel_plane_state {
- union {
- struct drm_plane_state uapi;
- struct drm_plane_state hw;
- };
+ struct drm_plane_state uapi;
+
+ /*
+ * actual hardware state, the state we program to the hardware.
+ * The following members are used to verify the hardware state:
+ * During initial hw readout, they need to be copied from uapi.
+ */
+ struct {
+ struct drm_crtc *crtc;
+ struct drm_framebuffer *fb;
+
+ u16 alpha;
+ uint16_t pixel_blend_mode;
+ unsigned int rotation;
+ enum drm_color_encoding color_encoding;
+ enum drm_color_range color_range;
+ } hw;
+
struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-04 11:35 ` [PATCH 12/24] drm/i915: Split plane hw and uapi state Maarten Lankhorst
@ 2019-10-08 17:42 ` Ville Syrjälä
2019-10-09 12:13 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-08 17:42 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
> Splitting plane state is easier than splitting crtc_state,
> before plane check we copy the drm properties to hw so we can
> do the same in bigjoiner later on.
>
> We copy the state after we did all the modeset handling, but fortunately
> i915 seems to be split correctly and nothing during modeset looks
> at plane_state.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
> 4 files changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 01937896d69c..cc154cfa3381 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> intel_state->vma = NULL;
> intel_state->flags = 0;
>
> + /* will be set in intel_plane_atomic_check_with_state() */
> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
That seems wrong for the case where we add the plane after the
plane check has already been done.
I think we should maintain the current state unless the plane check
will overwrite it.
> +
> return &intel_state->uapi;
> }
>
> @@ -112,6 +115,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
> WARN_ON(plane_state->vma);
>
> __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> + if (plane_state->hw.fb)
> + drm_framebuffer_put(plane_state->hw.fb);
> kfree(plane_state);
> }
>
> @@ -138,15 +143,34 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> return cpp * crtc_state->pixel_rate;
> }
>
> +void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> + const struct intel_plane_state *from_plane_state)
> +{
> + plane_state->hw.crtc = from_plane_state->uapi.crtc;
> + plane_state->hw.fb = from_plane_state->uapi.fb;
> + if (plane_state->hw.fb)
> + drm_framebuffer_get(plane_state->hw.fb);
> +
> + plane_state->hw.alpha = from_plane_state->uapi.alpha;
> + plane_state->hw.pixel_blend_mode =
> + from_plane_state->uapi.pixel_blend_mode;
> + plane_state->hw.rotation = from_plane_state->uapi.rotation;
> + plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
> + plane_state->hw.color_range = from_plane_state->uapi.color_range;
> +}
> +
> int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state *old_plane_state,
> struct intel_plane_state *new_plane_state)
> {
> struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
> - const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> + const struct drm_framebuffer *fb;
> int ret;
>
> + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
> + fb = new_plane_state->hw.fb;
> +
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> new_crtc_state->c8_planes &= ~BIT(plane->id);
> @@ -373,6 +397,7 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> {
> struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> + const struct intel_plane_state *old_plane_state;
>
> if (plane_state)
> return plane_state;
> @@ -381,6 +406,16 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
> if (IS_ERR(plane_state))
> return plane_state;
>
> + old_plane_state = intel_atomic_get_old_plane_state(state, plane);
> +
> + /*
> + * copy HW parameters since they're zero'd on duplication, to prevent
> + * accidentally using stale state.
> + */
> + plane_state->hw = old_plane_state->hw;
> + if (plane_state->hw.fb)
> + drm_framebuffer_get(plane_state->hw.fb);
> +
> new_crtc_state->update_planes |= BIT(plane->id);
> return plane_state;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index cb7ef4f9eafd..fd4b96013454 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
>
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> +void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> + const struct intel_plane_state *from_plane_state);
> void intel_update_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ee542840c70..ffde4b8b8be9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3267,6 +3267,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
>
> plane_state->fb = fb;
> plane_state->crtc = &intel_crtc->base;
> + intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
>
> atomic_or(to_intel_plane(primary)->frontbuffer_bit,
> &to_intel_frontbuffer(fb)->bits);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c6c49aa8c172..67644818efd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -515,10 +515,24 @@ struct intel_atomic_state {
> };
>
> struct intel_plane_state {
> - union {
> - struct drm_plane_state uapi;
> - struct drm_plane_state hw;
> - };
> + struct drm_plane_state uapi;
> +
> + /*
> + * actual hardware state, the state we program to the hardware.
> + * The following members are used to verify the hardware state:
> + * During initial hw readout, they need to be copied from uapi.
> + */
> + struct {
> + struct drm_crtc *crtc;
> + struct drm_framebuffer *fb;
> +
> + u16 alpha;
> + uint16_t pixel_blend_mode;
> + unsigned int rotation;
> + enum drm_color_encoding color_encoding;
> + enum drm_color_range color_range;
> + } hw;
> +
> struct i915_ggtt_view view;
> struct i915_vma *vma;
> unsigned long flags;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-08 17:42 ` Ville Syrjälä
@ 2019-10-09 12:13 ` Maarten Lankhorst
2019-10-09 12:23 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-09 12:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 08-10-2019 om 19:42 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
>> Splitting plane state is easier than splitting crtc_state,
>> before plane check we copy the drm properties to hw so we can
>> do the same in bigjoiner later on.
>>
>> We copy the state after we did all the modeset handling, but fortunately
>> i915 seems to be split correctly and nothing during modeset looks
>> at plane_state.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
>> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
>> 4 files changed, 57 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 01937896d69c..cc154cfa3381 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
>> intel_state->vma = NULL;
>> intel_state->flags = 0;
>>
>> + /* will be set in intel_plane_atomic_check_with_state() */
>> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
> That seems wrong for the case where we add the plane after the
> plane check has already been done.
>
> I think we should maintain the current state unless the plane check
> will overwrite it.
Have you seen
intel_atomic_get_plane_state_after_check()?
>> +
>> return &intel_state->uapi;
>> }
>>
>> @@ -112,6 +115,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
>> WARN_ON(plane_state->vma);
>>
>> __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
>> + if (plane_state->hw.fb)
>> + drm_framebuffer_put(plane_state->hw.fb);
>> kfree(plane_state);
>> }
>>
>> @@ -138,15 +143,34 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
>> return cpp * crtc_state->pixel_rate;
>> }
>>
>> +void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>> + const struct intel_plane_state *from_plane_state)
>> +{
>> + plane_state->hw.crtc = from_plane_state->uapi.crtc;
>> + plane_state->hw.fb = from_plane_state->uapi.fb;
>> + if (plane_state->hw.fb)
>> + drm_framebuffer_get(plane_state->hw.fb);
>> +
>> + plane_state->hw.alpha = from_plane_state->uapi.alpha;
>> + plane_state->hw.pixel_blend_mode =
>> + from_plane_state->uapi.pixel_blend_mode;
>> + plane_state->hw.rotation = from_plane_state->uapi.rotation;
>> + plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
>> + plane_state->hw.color_range = from_plane_state->uapi.color_range;
>> +}
>> +
>> int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
>> struct intel_crtc_state *new_crtc_state,
>> const struct intel_plane_state *old_plane_state,
>> struct intel_plane_state *new_plane_state)
>> {
>> struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
>> - const struct drm_framebuffer *fb = new_plane_state->hw.fb;
>> + const struct drm_framebuffer *fb;
>> int ret;
>>
>> + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
>> + fb = new_plane_state->hw.fb;
>> +
>> new_crtc_state->active_planes &= ~BIT(plane->id);
>> new_crtc_state->nv12_planes &= ~BIT(plane->id);
>> new_crtc_state->c8_planes &= ~BIT(plane->id);
>> @@ -373,6 +397,7 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>> {
>> struct intel_plane_state *plane_state =
>> intel_atomic_get_new_plane_state(state, plane);
>> + const struct intel_plane_state *old_plane_state;
>>
>> if (plane_state)
>> return plane_state;
>> @@ -381,6 +406,16 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
>> if (IS_ERR(plane_state))
>> return plane_state;
>>
>> + old_plane_state = intel_atomic_get_old_plane_state(state, plane);
>> +
>> + /*
>> + * copy HW parameters since they're zero'd on duplication, to prevent
>> + * accidentally using stale state.
>> + */
>> + plane_state->hw = old_plane_state->hw;
>> + if (plane_state->hw.fb)
>> + drm_framebuffer_get(plane_state->hw.fb);
>> +
>> new_crtc_state->update_planes |= BIT(plane->id);
>> return plane_state;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
>> index cb7ef4f9eafd..fd4b96013454 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
>> @@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
>>
>> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state);
>> +void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>> + const struct intel_plane_state *from_plane_state);
>> void intel_update_plane(struct intel_plane *plane,
>> const struct intel_crtc_state *crtc_state,
>> const struct intel_plane_state *plane_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 0ee542840c70..ffde4b8b8be9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3267,6 +3267,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
>>
>> plane_state->fb = fb;
>> plane_state->crtc = &intel_crtc->base;
>> + intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
>>
>> atomic_or(to_intel_plane(primary)->frontbuffer_bit,
>> &to_intel_frontbuffer(fb)->bits);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index c6c49aa8c172..67644818efd2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -515,10 +515,24 @@ struct intel_atomic_state {
>> };
>>
>> struct intel_plane_state {
>> - union {
>> - struct drm_plane_state uapi;
>> - struct drm_plane_state hw;
>> - };
>> + struct drm_plane_state uapi;
>> +
>> + /*
>> + * actual hardware state, the state we program to the hardware.
>> + * The following members are used to verify the hardware state:
>> + * During initial hw readout, they need to be copied from uapi.
>> + */
>> + struct {
>> + struct drm_crtc *crtc;
>> + struct drm_framebuffer *fb;
>> +
>> + u16 alpha;
>> + uint16_t pixel_blend_mode;
>> + unsigned int rotation;
>> + enum drm_color_encoding color_encoding;
>> + enum drm_color_range color_range;
>> + } hw;
>> +
>> struct i915_ggtt_view view;
>> struct i915_vma *vma;
>> unsigned long flags;
>> --
>> 2.23.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-09 12:13 ` Maarten Lankhorst
@ 2019-10-09 12:23 ` Ville Syrjälä
2019-10-09 12:31 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-09 12:23 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Wed, Oct 09, 2019 at 02:13:55PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:42 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
> >> Splitting plane state is easier than splitting crtc_state,
> >> before plane check we copy the drm properties to hw so we can
> >> do the same in bigjoiner later on.
> >>
> >> We copy the state after we did all the modeset handling, but fortunately
> >> i915 seems to be split correctly and nothing during modeset looks
> >> at plane_state.
> >>
> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >> ---
> >> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
> >> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
> >> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> >> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
> >> 4 files changed, 57 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> index 01937896d69c..cc154cfa3381 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> >> intel_state->vma = NULL;
> >> intel_state->flags = 0;
> >>
> >> + /* will be set in intel_plane_atomic_check_with_state() */
> >> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
> > That seems wrong for the case where we add the plane after the
> > plane check has already been done.
> >
> > I think we should maintain the current state unless the plane check
> > will overwrite it.
> Have you seen
>
> intel_atomic_get_plane_state_after_check()?
Yes, but I don't like it.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-09 12:23 ` Ville Syrjälä
@ 2019-10-09 12:31 ` Maarten Lankhorst
2019-10-09 12:41 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-09 12:31 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 09-10-2019 om 14:23 schreef Ville Syrjälä:
> On Wed, Oct 09, 2019 at 02:13:55PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:42 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
>>>> Splitting plane state is easier than splitting crtc_state,
>>>> before plane check we copy the drm properties to hw so we can
>>>> do the same in bigjoiner later on.
>>>>
>>>> We copy the state after we did all the modeset handling, but fortunately
>>>> i915 seems to be split correctly and nothing during modeset looks
>>>> at plane_state.
>>>>
>>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>>> ---
>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
>>>> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
>>>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>>>> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
>>>> 4 files changed, 57 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> index 01937896d69c..cc154cfa3381 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
>>>> intel_state->vma = NULL;
>>>> intel_state->flags = 0;
>>>>
>>>> + /* will be set in intel_plane_atomic_check_with_state() */
>>>> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
>>> That seems wrong for the case where we add the plane after the
>>> plane check has already been done.
>>>
>>> I think we should maintain the current state unless the plane check
>>> will overwrite it.
>> Have you seen
>>
>> intel_atomic_get_plane_state_after_check()?
> Yes, but I don't like it.
This is however required because of the split. We should not look at the old plane_state contents before atomic_check and to prevent that I think it's better to zero out plane_state->hw,
in which case bugs are at least consistent. :)
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-09 12:31 ` Maarten Lankhorst
@ 2019-10-09 12:41 ` Ville Syrjälä
2019-10-09 12:58 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-09 12:41 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Wed, Oct 09, 2019 at 02:31:58PM +0200, Maarten Lankhorst wrote:
> Op 09-10-2019 om 14:23 schreef Ville Syrjälä:
> > On Wed, Oct 09, 2019 at 02:13:55PM +0200, Maarten Lankhorst wrote:
> >> Op 08-10-2019 om 19:42 schreef Ville Syrjälä:
> >>> On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
> >>>> Splitting plane state is easier than splitting crtc_state,
> >>>> before plane check we copy the drm properties to hw so we can
> >>>> do the same in bigjoiner later on.
> >>>>
> >>>> We copy the state after we did all the modeset handling, but fortunately
> >>>> i915 seems to be split correctly and nothing during modeset looks
> >>>> at plane_state.
> >>>>
> >>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >>>> ---
> >>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
> >>>> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
> >>>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> >>>> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
> >>>> 4 files changed, 57 insertions(+), 5 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> index 01937896d69c..cc154cfa3381 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> >>>> intel_state->vma = NULL;
> >>>> intel_state->flags = 0;
> >>>>
> >>>> + /* will be set in intel_plane_atomic_check_with_state() */
> >>>> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
> >>> That seems wrong for the case where we add the plane after the
> >>> plane check has already been done.
> >>>
> >>> I think we should maintain the current state unless the plane check
> >>> will overwrite it.
> >> Have you seen
> >>
> >> intel_atomic_get_plane_state_after_check()?
> > Yes, but I don't like it.
>
> This is however required because of the split. We should not look at the old plane_state contents before atomic_check and to prevent that I think it's better to zero out plane_state->hw,
>
> in which case bugs are at least consistent. :)
I don't like leaking this special case all over. IMO it's not really any
different to the current rule that you can't look at any of the derived
state before plane check(). We're just extending the concept of the
derived state a bit.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH 12/24] drm/i915: Split plane hw and uapi state
2019-10-09 12:41 ` Ville Syrjälä
@ 2019-10-09 12:58 ` Maarten Lankhorst
0 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-09 12:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 09-10-2019 om 14:41 schreef Ville Syrjälä:
> On Wed, Oct 09, 2019 at 02:31:58PM +0200, Maarten Lankhorst wrote:
>> Op 09-10-2019 om 14:23 schreef Ville Syrjälä:
>>> On Wed, Oct 09, 2019 at 02:13:55PM +0200, Maarten Lankhorst wrote:
>>>> Op 08-10-2019 om 19:42 schreef Ville Syrjälä:
>>>>> On Fri, Oct 04, 2019 at 01:35:02PM +0200, Maarten Lankhorst wrote:
>>>>>> Splitting plane state is easier than splitting crtc_state,
>>>>>> before plane check we copy the drm properties to hw so we can
>>>>>> do the same in bigjoiner later on.
>>>>>>
>>>>>> We copy the state after we did all the modeset handling, but fortunately
>>>>>> i915 seems to be split correctly and nothing during modeset looks
>>>>>> at plane_state.
>>>>>>
>>>>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>>>>> ---
>>>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
>>>>>> .../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
>>>>>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>>>>>> .../drm/i915/display/intel_display_types.h | 22 +++++++++--
>>>>>> 4 files changed, 57 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> index 01937896d69c..cc154cfa3381 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> @@ -93,6 +93,9 @@ intel_plane_duplicate_state(struct drm_plane *plane)
>>>>>> intel_state->vma = NULL;
>>>>>> intel_state->flags = 0;
>>>>>>
>>>>>> + /* will be set in intel_plane_atomic_check_with_state() */
>>>>>> + memset(&intel_state->hw, 0, sizeof(intel_state->hw));
>>>>> That seems wrong for the case where we add the plane after the
>>>>> plane check has already been done.
>>>>>
>>>>> I think we should maintain the current state unless the plane check
>>>>> will overwrite it.
>>>> Have you seen
>>>>
>>>> intel_atomic_get_plane_state_after_check()?
>>> Yes, but I don't like it.
>> This is however required because of the split. We should not look at the old plane_state contents before atomic_check and to prevent that I think it's better to zero out plane_state->hw,
>>
>> in which case bugs are at least consistent. :)
> I don't like leaking this special case all over. IMO it's not really any
> different to the current rule that you can't look at any of the derived
> state before plane check(). We're just extending the concept of the
> derived state a bit.
>
I'm ok with that..
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 13/24] drm/i915: Stop using drm_atomic_helper_check_planes()
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (11 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 12/24] drm/i915: Split plane hw and uapi state Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2 Maarten Lankhorst
` (13 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We need to insert stuff between the plane and crtc .atomic_check()
drm_atomic_helper_check_planes() doesn't allow us to do that so
stop using it and hand roll the loops instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 10 +---
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 57 +++++++++++++++----
3 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cc154cfa3381..ce75cf1dc65c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -219,14 +219,11 @@ get_crtc_from_states(const struct intel_plane_state *old_plane_state,
return NULL;
}
-static int intel_plane_atomic_check(struct drm_plane *_plane,
- struct drm_plane_state *_new_plane_state)
+int intel_plane_atomic_check(struct intel_atomic_state *state,
+ struct intel_plane *plane)
{
- struct intel_plane *plane = to_intel_plane(_plane);
- struct intel_atomic_state *state =
- to_intel_atomic_state(_new_plane_state->state);
struct intel_plane_state *new_plane_state =
- to_intel_plane_state(_new_plane_state);
+ intel_atomic_get_new_plane_state(state, plane);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
struct intel_crtc *crtc =
@@ -423,5 +420,4 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
- .atomic_check = intel_plane_atomic_check,
};
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index fd4b96013454..123404a9cf23 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -43,6 +43,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *intel_state);
+int intel_plane_atomic_check(struct intel_atomic_state *state,
+ struct intel_plane *plane);
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ffde4b8b8be9..caab8cfddcbd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11799,15 +11799,14 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
-static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
- struct drm_crtc_state *_crtc_state)
+static int intel_crtc_atomic_check(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(_crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(_crtc_state);
- int ret;
+ intel_atomic_get_new_crtc_state(state, crtc);
bool mode_changed = needs_modeset(crtc_state);
+ int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
mode_changed && !crtc_state->hw.active)
@@ -11879,10 +11878,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
return ret;
}
-static const struct drm_crtc_helper_funcs intel_helper_funcs = {
- .atomic_check = intel_crtc_atomic_check,
-};
-
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
{
struct intel_connector *connector;
@@ -13581,6 +13576,42 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
new_crtc_state->has_drrs = old_crtc_state->has_drrs;
}
+static int intel_atomic_check_planes(struct intel_atomic_state *state)
+{
+ struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i, ret;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ ret = intel_plane_atomic_check(state, plane);
+ if (ret) {
+ DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n",
+ plane->base.base.id, plane->base.name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int ret = intel_crtc_atomic_check(state, crtc);
+ if (ret) {
+ DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n",
+ crtc->base.base.id, crtc->base.name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -13650,7 +13681,11 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- ret = drm_atomic_helper_check_planes(dev, &state->base);
+ ret = intel_atomic_check_planes(state);
+ if (ret)
+ goto fail;
+
+ ret = intel_atomic_check_crtcs(state);
if (ret)
goto fail;
@@ -15241,8 +15276,6 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
}
- drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
-
intel_color_init(intel_crtc);
WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (12 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 13/24] drm/i915: Stop using drm_atomic_helper_check_planes() Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-08 17:50 ` Ville Syrjälä
2019-10-04 11:35 ` [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2 Maarten Lankhorst
` (12 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
eDP does not support bigjoiner, so do not expose bigjoiner only
modes on the eDP port.
Changes since v1:
- Disallow bigjoiner on eDP.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 92 +++++++++++++++++++------
1 file changed, 72 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4297738655c6..5c7323af08b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -244,7 +244,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
}
static int
-intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &intel_dig_port->base;
@@ -254,6 +254,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+ if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
+ max_dotclk *= 2;
+
if (type != DP_DS_PORT_TYPE_VGA)
return max_dotclk;
@@ -506,7 +509,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -524,6 +528,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
mode_hdisplay;
+
+ if (bigjoiner)
+ max_bpp_small_joiner_ram *= 2;
+
DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
/*
@@ -532,6 +540,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
*/
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ if (bigjoiner) {
+ u32 max_bpp_bigjoiner =
+ i915->max_cdclk_freq * 48 /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+ }
+
/* Error out if the max bpp is less than smallest allowed valid bpp */
if (bits_per_pixel < valid_dsc_bpp[0]) {
DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
@@ -554,7 +571,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
}
static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay)
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
u8 min_slice_count, i;
int max_slice_width;
@@ -579,12 +597,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
/* Find the closest match to the valid slice count values */
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
- if (valid_dsc_slicecount[i] >
- drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
- false))
+ u8 test_slice_count = bigjoiner ?
+ 2 * valid_dsc_slicecount[i] :
+ valid_dsc_slicecount[i];
+
+ if (test_slice_count >
+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
break;
- if (min_slice_count <= valid_dsc_slicecount[i])
- return valid_dsc_slicecount[i];
+
+ /* big joiner needs small joiner to be enabled */
+ if (bigjoiner && test_slice_count < 4)
+ continue;
+
+ if (min_slice_count <= test_slice_count)
+ return test_slice_count;
}
DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
@@ -604,11 +630,15 @@ intel_dp_mode_valid(struct drm_connector *connector,
int max_dotclk;
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
+ bool dsc = false, bigjoiner = false;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
- max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_H_ILLEGAL;
+
+ max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, false);
if (intel_dp_is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
@@ -620,6 +650,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
+ if (mode->clock < 10000)
+ return MODE_CLOCK_LOW;
+
+ if (target_clock > max_dotclk) {
+ if (intel_dp_is_edp(intel_dp))
+ return MODE_CLOCK_HIGH;
+
+ max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, true);
+
+ if (target_clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+
+ bigjoiner = true;
+ }
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
@@ -644,23 +689,28 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_link_clock,
max_lanes,
target_clock,
- mode->hdisplay) >> 4;
+ mode->hdisplay,
+ bigjoiner) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
- mode->hdisplay);
+ mode->hdisplay,
+ bigjoiner);
}
+
+ dsc = dsc_max_output_bpp && dsc_slice_count;
}
- if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
- target_clock > max_dotclk)
+ /* big joiner configuration needs DSC */
+ if (bigjoiner && !dsc) {
+ DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
return MODE_CLOCK_HIGH;
+ }
- if (mode->clock < 10000)
- return MODE_CLOCK_LOW;
-
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return MODE_H_ILLEGAL;
+ if (mode_rate > max_rate && !dsc) {
+ DRM_DEBUG_KMS("Cannot drive without DSC\n");
+ return MODE_CLOCK_HIGH;
+ }
return intel_mode_valid_max_plane_size(dev_priv, mode);
}
@@ -2072,11 +2122,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay);
+ adjusted_mode->crtc_hdisplay,
+ false);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
return -EINVAL;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2.
2019-10-04 11:35 ` [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2 Maarten Lankhorst
@ 2019-10-08 17:50 ` Ville Syrjälä
0 siblings, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-08 17:50 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:35:04PM +0200, Maarten Lankhorst wrote:
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> eDP does not support bigjoiner, so do not expose bigjoiner only
> modes on the eDP port.
>
> Changes since v1:
> - Disallow bigjoiner on eDP.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 92 +++++++++++++++++++------
> 1 file changed, 72 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4297738655c6..5c7323af08b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -244,7 +244,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> }
>
> static int
> -intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
> +intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool allow_bigjoiner)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &intel_dig_port->base;
> @@ -254,6 +254,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
>
> int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
>
> + if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
> + max_dotclk *= 2;
> +
This code is now rather confusing. OK, this function is already misnamed
because it checks both the source and downstream dotclock limits.
I suspect this should all look a bit more like:
source_max_dotclock()
{
if (port_can_do_bigjoiner && dsc_supported)
return 2*max_dotclock;
else
return max_dotclock;
}
max_dotclock = source_max_dotclock();
ds_max_dotclock = ds_max_dotclock()
if (ds_max_dotclock)
max_dotclock = min(max_dotclock, ds_max_dotclock);
> if (type != DP_DS_PORT_TYPE_VGA)
> return max_dotclk;
>
> @@ -506,7 +509,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
>
> static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> u32 link_clock, u32 lane_count,
> - u32 mode_clock, u32 mode_hdisplay)
> + u32 mode_clock, u32 mode_hdisplay,
> + bool bigjoiner)
> {
> u32 bits_per_pixel, max_bpp_small_joiner_ram;
> int i;
> @@ -524,6 +528,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
> max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
> mode_hdisplay;
> +
> + if (bigjoiner)
> + max_bpp_small_joiner_ram *= 2;
> +
> DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
>
> /*
> @@ -532,6 +540,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> */
> bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>
> + if (bigjoiner) {
> + u32 max_bpp_bigjoiner =
> + i915->max_cdclk_freq * 48 /
> + intel_dp_mode_to_fec_clock(mode_clock);
> +
> + DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> + bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> + }
> +
> /* Error out if the max bpp is less than smallest allowed valid bpp */
> if (bits_per_pixel < valid_dsc_bpp[0]) {
> DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
> @@ -554,7 +571,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
> }
>
> static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> - int mode_clock, int mode_hdisplay)
> + int mode_clock, int mode_hdisplay,
> + bool bigjoiner)
> {
> u8 min_slice_count, i;
> int max_slice_width;
> @@ -579,12 +597,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>
> /* Find the closest match to the valid slice count values */
> for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> - if (valid_dsc_slicecount[i] >
> - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> - false))
> + u8 test_slice_count = bigjoiner ?
> + 2 * valid_dsc_slicecount[i] :
> + valid_dsc_slicecount[i];
> +
> + if (test_slice_count >
> + drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
> break;
> - if (min_slice_count <= valid_dsc_slicecount[i])
> - return valid_dsc_slicecount[i];
> +
> + /* big joiner needs small joiner to be enabled */
> + if (bigjoiner && test_slice_count < 4)
> + continue;
> +
> + if (min_slice_count <= test_slice_count)
> + return test_slice_count;
> }
>
> DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
> @@ -604,11 +630,15 @@ intel_dp_mode_valid(struct drm_connector *connector,
> int max_dotclk;
> u16 dsc_max_output_bpp = 0;
> u8 dsc_slice_count = 0;
> + bool dsc = false, bigjoiner = false;
>
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return MODE_NO_DBLESCAN;
>
> - max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
> + if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> + return MODE_H_ILLEGAL;
> +
> + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, false);
>
> if (intel_dp_is_edp(intel_dp) && fixed_mode) {
> if (mode->hdisplay > fixed_mode->hdisplay)
> @@ -620,6 +650,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
> target_clock = fixed_mode->clock;
> }
>
> + if (mode->clock < 10000)
> + return MODE_CLOCK_LOW;
> +
> + if (target_clock > max_dotclk) {
> + if (intel_dp_is_edp(intel_dp))
> + return MODE_CLOCK_HIGH;
> +
> + max_dotclk = intel_dp_downstream_max_dotclock(intel_dp, true);
> +
> + if (target_clock > max_dotclk)
> + return MODE_CLOCK_HIGH;
> +
> + bigjoiner = true;
> + }
> +
> max_link_clock = intel_dp_max_link_rate(intel_dp);
> max_lanes = intel_dp_max_lane_count(intel_dp);
>
> @@ -644,23 +689,28 @@ intel_dp_mode_valid(struct drm_connector *connector,
> max_link_clock,
> max_lanes,
> target_clock,
> - mode->hdisplay) >> 4;
> + mode->hdisplay,
> + bigjoiner) >> 4;
> dsc_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> target_clock,
> - mode->hdisplay);
> + mode->hdisplay,
> + bigjoiner);
> }
> +
> + dsc = dsc_max_output_bpp && dsc_slice_count;
> }
>
> - if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> - target_clock > max_dotclk)
> + /* big joiner configuration needs DSC */
> + if (bigjoiner && !dsc) {
> + DRM_DEBUG_KMS("Link clock needs bigjoiner, but DSC or FEC not available\n");
> return MODE_CLOCK_HIGH;
> + }
>
> - if (mode->clock < 10000)
> - return MODE_CLOCK_LOW;
> -
> - if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> - return MODE_H_ILLEGAL;
> + if (mode_rate > max_rate && !dsc) {
> + DRM_DEBUG_KMS("Cannot drive without DSC\n");
> + return MODE_CLOCK_HIGH;
> + }
>
> return intel_mode_valid_max_plane_size(dev_priv, mode);
> }
> @@ -2072,11 +2122,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->port_clock,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> dsc_dp_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> adjusted_mode->crtc_clock,
> - adjusted_mode->crtc_hdisplay);
> + adjusted_mode->crtc_hdisplay,
> + false);
> if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
> return -EINVAL;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (13 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 14/24] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v2 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-08 19:40 ` Ville Syrjälä
2019-10-04 11:35 ` [PATCH 16/24] drm/i915: Enable big joiner support in enable and disable sequences Maarten Lankhorst
` (11 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so it doesn't depend at commit time on the other
crtc_state.
Changes since v1:
- Rename pipe timings to transcoder timings, as they are now different.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 218 ++++++++++++++++--
.../drm/i915/display/intel_display_types.h | 11 +-
drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
5 files changed, 234 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 4783d7ff4fcf..a5b11bd9da68 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
intel_crtc_put_color_blobs(crtc_state);
}
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
{
intel_crtc_put_color_blobs(crtc_state);
- if (crtc_state->uapi.degamma_lut)
+ if (from_crtc_state->uapi.degamma_lut)
crtc_state->hw.degamma_lut =
- drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
else
crtc_state->hw.degamma_lut = NULL;
- if (crtc_state->uapi.gamma_lut)
+ if (from_crtc_state->uapi.gamma_lut)
crtc_state->hw.gamma_lut =
- drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
else
crtc_state->hw.gamma_lut = NULL;
- if (crtc_state->uapi.ctm)
+ if (from_crtc_state->uapi.ctm)
crtc_state->hw.ctm =
- drm_property_blob_get(crtc_state->uapi.ctm);
+ drm_property_blob_get(from_crtc_state->uapi.ctm);
else
crtc_state->hw.ctm = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 42be91e0772a..8da84d64aa04 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index caab8cfddcbd..c2b3c7b6f39b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -123,7 +123,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
static int intel_framebuffer_init(struct intel_framebuffer *ifb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd);
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n,
@@ -6308,7 +6308,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
- intel_set_pipe_timings(pipe_config);
+ intel_set_transcoder_timings(pipe_config);
intel_set_pipe_src_size(pipe_config);
if (pipe_config->has_pch_encoder) {
@@ -6435,7 +6435,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_dp_set_m_n(pipe_config, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(pipe_config);
+ intel_set_transcoder_timings(pipe_config);
intel_set_pipe_src_size(pipe_config);
@@ -6838,7 +6838,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
- intel_set_pipe_timings(pipe_config);
+ intel_set_transcoder_timings(pipe_config);
intel_set_pipe_src_size(pipe_config);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -6906,7 +6906,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
- intel_set_pipe_timings(pipe_config);
+ intel_set_transcoder_timings(pipe_config);
intel_set_pipe_src_size(pipe_config);
i9xx_set_pipeconf(pipe_config);
@@ -7396,7 +7396,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int clock_limit = dev_priv->max_dotclk_freq;
if (INTEL_GEN(dev_priv) < 4) {
@@ -7413,6 +7413,25 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
}
}
+ /*
+ * copy hw mode to transcoder mode.
+ * This matters mostly for big joiner, which splits the mode in half.
+ */
+ pipe_config->hw.transcoder_mode = pipe_config->hw.adjusted_mode;
+ if (pipe_config->bigjoiner) {
+ /* Make sure the crtc config is halved horizontally */
+ adjusted_mode->crtc_clock /= 2;
+ adjusted_mode->crtc_hdisplay /= 2;
+ adjusted_mode->crtc_hblank_start /= 2;
+ adjusted_mode->crtc_hblank_end /= 2;
+ adjusted_mode->crtc_hsync_start /= 2;
+ adjusted_mode->crtc_hsync_end /= 2;
+ adjusted_mode->crtc_htotal /= 2;
+ adjusted_mode->crtc_hskew /= 2;
+
+ pipe_config->pipe_src_w /= 2;
+ }
+
if (adjusted_mode->crtc_clock > clock_limit) {
DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
adjusted_mode->crtc_clock, clock_limit,
@@ -8114,13 +8133,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.dpll = dpll;
}
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.transcoder_mode;
u32 crtc_vtotal, crtc_vblank_end;
int vsyncshift = 0;
@@ -8205,8 +8224,8 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
}
-static void intel_get_pipe_timings(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void intel_get_transcoder_timings(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -8809,7 +8828,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
i9xx_get_pfit_config(crtc, pipe_config);
@@ -10045,7 +10064,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
ironlake_get_pfit_config(crtc, pipe_config);
@@ -10445,7 +10464,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) {
haswell_get_ddi_port_state(crtc, pipe_config);
- intel_get_pipe_timings(crtc, pipe_config);
+ intel_get_transcoder_timings(crtc, pipe_config);
}
intel_get_pipe_src_size(crtc, pipe_config);
@@ -11814,6 +11833,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
if (mode_changed && crtc_state->hw.enable &&
dev_priv->display.crtc_compute_clock &&
+ !crtc_state->bigjoiner_slave &&
!WARN_ON(crtc_state->shared_dpll)) {
ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
@@ -12278,7 +12298,7 @@ static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
crtc_state->hw.active = crtc_state->uapi.active;
crtc_state->hw.mode = crtc_state->uapi.mode;
crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
- intel_crtc_copy_color_blobs(crtc_state);
+ intel_crtc_copy_color_blobs(crtc_state, crtc_state);
}
static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
@@ -12286,7 +12306,48 @@ static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
crtc_state->uapi.enable = crtc_state->hw.enable;
crtc_state->uapi.active = crtc_state->hw.active;
crtc_state->uapi.mode = crtc_state->hw.mode;
- crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+ crtc_state->uapi.adjusted_mode = crtc_state->hw.transcoder_mode;
+}
+
+static int
+copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
+ const struct intel_crtc_state *from_crtc_state)
+{
+ struct intel_crtc_state *saved_state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
+ if (!saved_state)
+ return -ENOMEM;
+
+ saved_state->uapi = crtc_state->uapi;
+ saved_state->scaler_state = crtc_state->scaler_state;
+ saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
+
+ intel_crtc_free_hw_state(crtc_state);
+ memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+ kfree(saved_state);
+
+ /* Re-init hw state */
+ memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
+ crtc_state->hw.enable = from_crtc_state->hw.enable;
+ crtc_state->hw.active = from_crtc_state->hw.active;
+ crtc_state->hw.mode = from_crtc_state->hw.mode;
+ crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+
+ /* Some fixups */
+ crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
+ crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
+ crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
+ crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
+ crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
+ crtc_state->bigjoiner_slave = true;
+ crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
+ crtc_state->has_audio = false;
+
+ return 0;
}
static int
@@ -12459,7 +12520,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
/* uapi wants a copy of the adjusted_mode for vblank bookkeeping */
- pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
+ pipe_config->uapi.adjusted_mode = pipe_config->hw.transcoder_mode;
return 0;
}
@@ -13612,6 +13673,109 @@ static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
return 0;
}
+static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state, *slave_crtc_state, *master_crtc_state;
+ struct intel_crtc *crtc, *slave, *master;
+ int i, ret = 0;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (!old_crtc_state->bigjoiner_slave)
+ continue;
+
+ if (crtc->pipe == PIPE_A) {
+ DRM_ERROR("Bigjoiner slave on pipe A?\n");
+ return -EINVAL;
+ }
+
+ /* crtc staying in slave mode? */
+ if (!new_crtc_state->uapi.enable)
+ continue;
+
+ if (needs_modeset(new_crtc_state) || new_crtc_state->update_pipe) {
+ master = old_crtc_state->bigjoiner_linked_crtc;
+ master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
+ if (IS_ERR(master_crtc_state))
+ return PTR_ERR(master_crtc_state);
+
+ /*
+ * Force modeset on master, to recalculate bigjoiner
+ * state.
+ *
+ * If master_crtc_state was not part of the atomic commit,
+ * we will fail because the master was not deconfigured,
+ * but at least fail below to unify the checks.
+ */
+ master_crtc_state->uapi.mode_changed = true;
+
+ ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+
+ ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+ }
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (!new_crtc_state->uapi.enable || !new_crtc_state->bigjoiner) {
+ if (!old_crtc_state->bigjoiner)
+ continue;
+ }
+
+ if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
+ continue;
+
+ if (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave) {
+ if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
+ DRM_DEBUG_KMS("Big joiner configuration requires CRTC + 1 to be used, doesn't exist\n");
+ return -EINVAL;
+ }
+
+ slave = new_crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
+ if (IS_ERR(slave_crtc_state))
+ return PTR_ERR(slave_crtc_state);
+
+ if (slave_crtc_state->uapi.enable) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires this CRTC to be unconfigured\n",
+ slave->base.base.id, slave->base.name);
+ return -EINVAL;
+ } else {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
+ slave->base.base.id, slave->base.name);
+ ret = copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
+ }
+ } else {
+ master = new_crtc_state->bigjoiner_linked_crtc;
+ if (!master)
+ continue;
+
+ master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
+ if (IS_ERR(master_crtc_state))
+ return PTR_ERR(master_crtc_state);
+
+ if (!master_crtc_state->uapi.enable && !new_crtc_state->uapi.enable) {
+ DRM_DEBUG_KMS("[CRTC:%d:%s] Disabling slave from big joiner\n",
+ crtc->base.base.id, crtc->base.name);
+ ret = clear_intel_crtc_state(new_crtc_state);
+ }
+ }
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -13642,16 +13806,19 @@ static int intel_atomic_check(struct drm_device *dev,
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
- if (new_crtc_state->uapi.color_mgmt_changed)
- intel_crtc_copy_color_blobs(new_crtc_state);
+ if (new_crtc_state->uapi.color_mgmt_changed &&
+ !new_crtc_state->bigjoiner_slave)
+ intel_crtc_copy_color_blobs(new_crtc_state, new_crtc_state);
continue;
}
if (!new_crtc_state->uapi.enable) {
any_ms = true;
- intel_crtc_free_hw_state(new_crtc_state);
- memset(&new_crtc_state->hw, 0,
- sizeof(new_crtc_state->hw));
+ if (!new_crtc_state->bigjoiner_slave) {
+ intel_crtc_free_hw_state(new_crtc_state);
+ memset(&new_crtc_state->hw, 0,
+ sizeof(new_crtc_state->hw));
+ }
continue;
}
@@ -13665,6 +13832,10 @@ static int intel_atomic_check(struct drm_device *dev,
any_ms = true;
}
+ ret = intel_atomic_check_bigjoiner(state);
+ if (ret)
+ return ret;
+
ret = drm_dp_mst_atomic_check(&state->base);
if (ret)
goto fail;
@@ -13860,7 +14031,9 @@ static void intel_update_crtc(struct intel_crtc *crtc,
commit_pipe_config(state, old_crtc_state, new_crtc_state);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (new_crtc_state->bigjoiner)
+ {/* Not supported yet */}
+ else if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
@@ -16915,7 +17088,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
}
intel_bw_crtc_update(bw_state, crtc_state);
-
copy_hw_to_uapi_state(crtc_state);
intel_pipe_config_sanity_check(dev_priv, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 67644818efd2..6ce823943a69 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -791,7 +791,7 @@ struct intel_crtc_state {
struct {
bool active, enable;
struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
- struct drm_display_mode mode, adjusted_mode;
+ struct drm_display_mode mode, adjusted_mode, transcoder_mode;
} hw;
/**
@@ -1022,6 +1022,15 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* enable pipe big joiner? */
+ bool bigjoiner;
+
+ /* big joiner slave crtc? */
+ bool bigjoiner_slave;
+
+ /* linked crtc for bigjoiner, either slave or master */
+ struct intel_crtc *bigjoiner_linked_crtc;
+
/* Display Stream compression state */
struct {
bool compression_enable;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c7323af08b3..637ee7d0656a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2106,6 +2106,19 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
pipe_config->lane_count = limits->max_lane_count;
+ if (adjusted_mode->crtc_clock > intel_dp_downstream_max_dotclock(intel_dp, false)) {
+ if (adjusted_mode->crtc_clock > intel_dp_downstream_max_dotclock(intel_dp, true)) {
+ DRM_DEBUG_KMS("Clock rate too high for big joiner\n");
+ return -EINVAL;
+ }
+ if (intel_dp_is_edp(intel_dp)) {
+ DRM_DEBUG_KMS("Cannot split eDP stream in bigjoiner configuration.\n");
+ return -EINVAL;
+ }
+ pipe_config->bigjoiner = true;
+ DRM_DEBUG_KMS("Using bigjoiner configuration\n");
+ }
+
if (intel_dp_is_edp(intel_dp)) {
pipe_config->dsc_params.compressed_bpp =
min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
@@ -2123,12 +2136,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- false);
+ pipe_config->bigjoiner);
if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
return -EINVAL;
@@ -2143,13 +2156,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
- if (pipe_config->dsc_params.slice_count > 1) {
- pipe_config->dsc_params.dsc_split = true;
- } else {
+ if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || pipe_config->bigjoiner) {
+ if (pipe_config->dsc_params.slice_count < 2) {
DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
return -EINVAL;
}
+
+ pipe_config->dsc_params.dsc_split = true;
}
ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2.
2019-10-04 11:35 ` [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2 Maarten Lankhorst
@ 2019-10-08 19:40 ` Ville Syrjälä
2019-10-10 12:42 ` Maarten Lankhorst
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2019-10-08 19:40 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
> When the clock is higher than the dotclock, try with 2 pipes enabled.
> If we can enable 2, then we will go into big joiner mode, and steal
> the adjacent crtc.
>
> This only links the crtc's in software, no hardware or plane
> programming is done yet. Blobs are also copied from the master's
> crtc_state, so it doesn't depend at commit time on the other
> crtc_state.
>
> Changes since v1:
> - Rename pipe timings to transcoder timings, as they are now different.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 218 ++++++++++++++++--
> .../drm/i915/display/intel_display_types.h | 11 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
> 5 files changed, 234 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 4783d7ff4fcf..a5b11bd9da68 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> intel_crtc_put_color_blobs(crtc_state);
> }
>
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> {
> intel_crtc_put_color_blobs(crtc_state);
>
> - if (crtc_state->uapi.degamma_lut)
> + if (from_crtc_state->uapi.degamma_lut)
> crtc_state->hw.degamma_lut =
> - drm_property_blob_get(crtc_state->uapi.degamma_lut);
> + drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
> else
> crtc_state->hw.degamma_lut = NULL;
>
> - if (crtc_state->uapi.gamma_lut)
> + if (from_crtc_state->uapi.gamma_lut)
> crtc_state->hw.gamma_lut =
> - drm_property_blob_get(crtc_state->uapi.gamma_lut);
> + drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
> else
> crtc_state->hw.gamma_lut = NULL;
>
> - if (crtc_state->uapi.ctm)
> + if (from_crtc_state->uapi.ctm)
> crtc_state->hw.ctm =
> - drm_property_blob_get(crtc_state->uapi.ctm);
> + drm_property_blob_get(from_crtc_state->uapi.ctm);
> else
> crtc_state->hw.ctm = NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 42be91e0772a..8da84d64aa04 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index caab8cfddcbd..c2b3c7b6f39b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -123,7 +123,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd);
> -static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> const struct intel_link_m_n *m_n,
> @@ -6308,7 +6308,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> + intel_set_transcoder_timings(pipe_config);
> intel_set_pipe_src_size(pipe_config);
>
> if (pipe_config->has_pch_encoder) {
> @@ -6435,7 +6435,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_dp_set_m_n(pipe_config, M1_N1);
>
> if (!transcoder_is_dsi(cpu_transcoder))
> - intel_set_pipe_timings(pipe_config);
> + intel_set_transcoder_timings(pipe_config);
>
> intel_set_pipe_src_size(pipe_config);
>
> @@ -6838,7 +6838,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> + intel_set_transcoder_timings(pipe_config);
> intel_set_pipe_src_size(pipe_config);
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> @@ -6906,7 +6906,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> if (intel_crtc_has_dp_encoder(pipe_config))
> intel_dp_set_m_n(pipe_config, M1_N1);
>
> - intel_set_pipe_timings(pipe_config);
> + intel_set_transcoder_timings(pipe_config);
> intel_set_pipe_src_size(pipe_config);
>
> i9xx_set_pipeconf(pipe_config);
> @@ -7396,7 +7396,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int clock_limit = dev_priv->max_dotclk_freq;
>
> if (INTEL_GEN(dev_priv) < 4) {
> @@ -7413,6 +7413,25 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> }
> }
>
> + /*
> + * copy hw mode to transcoder mode.
> + * This matters mostly for big joiner, which splits the mode in half.
> + */
> + pipe_config->hw.transcoder_mode = pipe_config->hw.adjusted_mode;
> + if (pipe_config->bigjoiner) {
> + /* Make sure the crtc config is halved horizontally */
> + adjusted_mode->crtc_clock /= 2;
> + adjusted_mode->crtc_hdisplay /= 2;
> + adjusted_mode->crtc_hblank_start /= 2;
> + adjusted_mode->crtc_hblank_end /= 2;
> + adjusted_mode->crtc_hsync_start /= 2;
> + adjusted_mode->crtc_hsync_end /= 2;
> + adjusted_mode->crtc_htotal /= 2;
> + adjusted_mode->crtc_hskew /= 2;
> +
> + pipe_config->pipe_src_w /= 2;
> + }
Hmm. Oh right, we still need to keep the full timings since
the joiner is between the pipe and transcoder :/
We probably need a check to make sure the non-halved horiz
timings are even.
hskew we don't use so don't need to frob that.
I wonder if there are other places that need the full values. Quick
glance only really reveals encoder and audio code. Most encoder code
I guess doesn't really matter since bigjoiner is DP only. And the DP
code itself looks fine since this halving happens after
.compute_confog(). And the audio code only uses crtc_clock on HDMI
(not sure it should use it there either, but that's a separate issue).
> +
> if (adjusted_mode->crtc_clock > clock_limit) {
> DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> adjusted_mode->crtc_clock, clock_limit,
> @@ -8114,13 +8133,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
> crtc_state->dpll_hw_state.dpll = dpll;
> }
>
> -static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.transcoder_mode;
> u32 crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> @@ -8205,8 +8224,8 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
> }
>
> -static void intel_get_pipe_timings(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> +static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
Missing the transcoder_mode readout + adjusted_mode/2 here?
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -8809,7 +8828,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> if (INTEL_GEN(dev_priv) < 4)
> pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>
> - intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
>
> i9xx_get_pfit_config(crtc, pipe_config);
> @@ -10045,7 +10064,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> - intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
>
> ironlake_get_pfit_config(crtc, pipe_config);
> @@ -10445,7 +10464,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> INTEL_GEN(dev_priv) >= 11) {
> haswell_get_ddi_port_state(crtc, pipe_config);
> - intel_get_pipe_timings(crtc, pipe_config);
> + intel_get_transcoder_timings(crtc, pipe_config);
> }
>
> intel_get_pipe_src_size(crtc, pipe_config);
> @@ -11814,6 +11833,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>
> if (mode_changed && crtc_state->hw.enable &&
> dev_priv->display.crtc_compute_clock &&
> + !crtc_state->bigjoiner_slave &&
> !WARN_ON(crtc_state->shared_dpll)) {
> ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> if (ret)
> @@ -12278,7 +12298,7 @@ static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> crtc_state->hw.active = crtc_state->uapi.active;
> crtc_state->hw.mode = crtc_state->uapi.mode;
> crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> - intel_crtc_copy_color_blobs(crtc_state);
> + intel_crtc_copy_color_blobs(crtc_state, crtc_state);
> }
>
> static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> @@ -12286,7 +12306,48 @@ static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> crtc_state->uapi.enable = crtc_state->hw.enable;
> crtc_state->uapi.active = crtc_state->hw.active;
> crtc_state->uapi.mode = crtc_state->hw.mode;
> - crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> + crtc_state->uapi.adjusted_mode = crtc_state->hw.transcoder_mode;
> +}
> +
> +static int
> +copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
> + const struct intel_crtc_state *from_crtc_state)
> +{
> + struct intel_crtc_state *saved_state;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
> + if (!saved_state)
> + return -ENOMEM;
> +
> + saved_state->uapi = crtc_state->uapi;
> + saved_state->scaler_state = crtc_state->scaler_state;
> + saved_state->shared_dpll = crtc_state->shared_dpll;
> + saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> + saved_state->crc_enabled = crtc_state->crc_enabled;
> +
> + intel_crtc_free_hw_state(crtc_state);
> + memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> + kfree(saved_state);
> +
> + /* Re-init hw state */
> + memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
> + crtc_state->hw.enable = from_crtc_state->hw.enable;
> + crtc_state->hw.active = from_crtc_state->hw.active;
> + crtc_state->hw.mode = from_crtc_state->hw.mode;
> + crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
> +
> + /* Some fixups */
> + crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
> + crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
> + crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
> + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
> + crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
> + crtc_state->bigjoiner_slave = true;
> + crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
> + crtc_state->has_audio = false;
> +
> + return 0;
> }
>
> static int
> @@ -12459,7 +12520,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
>
> /* uapi wants a copy of the adjusted_mode for vblank bookkeeping */
> - pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
> + pipe_config->uapi.adjusted_mode = pipe_config->hw.transcoder_mode;
>
> return 0;
> }
> @@ -13612,6 +13673,109 @@ static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
> return 0;
> }
>
> +static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *old_crtc_state, *new_crtc_state, *slave_crtc_state, *master_crtc_state;
> + struct intel_crtc *crtc, *slave, *master;
> + int i, ret = 0;
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (!old_crtc_state->bigjoiner_slave)
I keep thinking that points at the slave. "is_bigjoiner_slave" would be
a less confusing name perhaps.
> + continue;
> +
> + if (crtc->pipe == PIPE_A) {
> + DRM_ERROR("Bigjoiner slave on pipe A?\n");
> + return -EINVAL;
> + }
Dead code?
> +
> + /* crtc staying in slave mode? */
> + if (!new_crtc_state->uapi.enable)
> + continue;
> +
> + if (needs_modeset(new_crtc_state) || new_crtc_state->update_pipe) {
Are these checks even needed? We've already determined we were a
slave and the uapi crtc is now enabled, so we have to give the
pipe back to the uapi user no matter what.
> + master = old_crtc_state->bigjoiner_linked_crtc;
> + master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
> + if (IS_ERR(master_crtc_state))
> + return PTR_ERR(master_crtc_state);
> +
> + /*
> + * Force modeset on master, to recalculate bigjoiner
> + * state.
> + *
> + * If master_crtc_state was not part of the atomic commit,
> + * we will fail because the master was not deconfigured,
> + * but at least fail below to unify the checks.
> + */
> + master_crtc_state->uapi.mode_changed = true;
> +
> + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> + if (ret)
> + return ret;
> +
> + ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
> + if (ret)
> + return ret;
This whole thing feels a bit late to be doing it. Can't we just do this
stuff before .compute_config()? Then at least in theory the master could
have a chance to reconfigure itself to not use the bigjoiner? I suppose
there is nothing it really can do to make the configuration work, but
I think it would still feel like the more natural order of things.
> + }
> + }
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (!new_crtc_state->uapi.enable || !new_crtc_state->bigjoiner) {
> + if (!old_crtc_state->bigjoiner)
> + continue;
I'm having a hard time decoding that. What are we trying to do?
> + }
> +
> + if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
> + continue;
> +
> + if (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave) {
> + if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
> + DRM_DEBUG_KMS("Big joiner configuration requires CRTC + 1 to be used, doesn't exist\n");
> + return -EINVAL;
> + }
I think we should be able to reject such a configuration already
when we decided that we need to use the bigjoiner. Should probably
write it with bitmasks to be future proof.
> +
> + slave = new_crtc_state->bigjoiner_linked_crtc =
> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
> + if (IS_ERR(slave_crtc_state))
> + return PTR_ERR(slave_crtc_state);
> +
> + if (slave_crtc_state->uapi.enable) {
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires this CRTC to be unconfigured\n",
> + slave->base.base.id, slave->base.name);
> + return -EINVAL;
> + } else {
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
> + slave->base.base.id, slave->base.name);
> + ret = copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
> + }
> + } else {
I guess this means we're always looking to associate the bigjoiner
master with the uapi crtc? I think in theory we should be able to
handle the case where the slave is the uapi crtc as well. But maybe
it doesn't matter so much as userspace probably picks crtcs in order
anyway. Hmm, maybe it would even be hard to deal with that...
> + master = new_crtc_state->bigjoiner_linked_crtc;
> + if (!master)
> + continue;
> +
> + master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
> + if (IS_ERR(master_crtc_state))
> + return PTR_ERR(master_crtc_state);
> +
> + if (!master_crtc_state->uapi.enable && !new_crtc_state->uapi.enable) {
> + DRM_DEBUG_KMS("[CRTC:%d:%s] Disabling slave from big joiner\n",
> + crtc->base.base.id, crtc->base.name);
> + ret = clear_intel_crtc_state(new_crtc_state);
> + }
This too feels like it could be done before we've compute anything.
Something like this is what I was thinking earlier:
detach_joiner() {
master.bigjoiner = {};
slave.bigjoiner = {};
}
setup_state_thing() {
if (new_crtc_state->uapi.enable) {
if (is_slave) {
assert(needs_modeset(new_crtc_state));
master = get_linked();
master.modeset = true;
detach_joiner();
} else if (is_master) {
slave = get_linked();
if (needs_modeset(new_crtc_state)) {
slave.modeset = true;
detach_joiner();
}
}
copy_uapi_to_hw(new_crtc_state);
} else {
if (is_master) {
assert(needs_modeset(new_crtc_state));
slave = get_linked();
slave.modeset = true;
detach_joiner();
}
if (!is_slave && needs_modeset(new_crtc_state))
copy_uapi_to_hw(new_crtc_state);
}
}
drm_atomic_helper_check_modeset();
+ setup_state_thing();
> + }
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -13642,16 +13806,19 @@ static int intel_atomic_check(struct drm_device *dev,
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state)) {
> - if (new_crtc_state->uapi.color_mgmt_changed)
> - intel_crtc_copy_color_blobs(new_crtc_state);
> + if (new_crtc_state->uapi.color_mgmt_changed &&
> + !new_crtc_state->bigjoiner_slave)
> + intel_crtc_copy_color_blobs(new_crtc_state, new_crtc_state);
> continue;
> }
>
> if (!new_crtc_state->uapi.enable) {
> any_ms = true;
> - intel_crtc_free_hw_state(new_crtc_state);
> - memset(&new_crtc_state->hw, 0,
> - sizeof(new_crtc_state->hw));
> + if (!new_crtc_state->bigjoiner_slave) {
> + intel_crtc_free_hw_state(new_crtc_state);
> + memset(&new_crtc_state->hw, 0,
> + sizeof(new_crtc_state->hw));
> + }
> continue;
> }
>
> @@ -13665,6 +13832,10 @@ static int intel_atomic_check(struct drm_device *dev,
> any_ms = true;
> }
>
> + ret = intel_atomic_check_bigjoiner(state);
> + if (ret)
> + return ret;
> +
> ret = drm_dp_mst_atomic_check(&state->base);
> if (ret)
> goto fail;
> @@ -13860,7 +14031,9 @@ static void intel_update_crtc(struct intel_crtc *crtc,
>
> commit_pipe_config(state, old_crtc_state, new_crtc_state);
>
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (new_crtc_state->bigjoiner)
> + {/* Not supported yet */}
> + else if (INTEL_GEN(dev_priv) >= 9)
> skl_update_planes_on_crtc(state, crtc);
> else
> i9xx_update_planes_on_crtc(state, crtc);
> @@ -16915,7 +17088,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> }
>
> intel_bw_crtc_update(bw_state, crtc_state);
> -
> copy_hw_to_uapi_state(crtc_state);
> intel_pipe_config_sanity_check(dev_priv, crtc_state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 67644818efd2..6ce823943a69 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -791,7 +791,7 @@ struct intel_crtc_state {
> struct {
> bool active, enable;
> struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> - struct drm_display_mode mode, adjusted_mode;
> + struct drm_display_mode mode, adjusted_mode, transcoder_mode;
> } hw;
>
> /**
> @@ -1022,6 +1022,15 @@ struct intel_crtc_state {
> /* enable pipe csc? */
> bool csc_enable;
>
> + /* enable pipe big joiner? */
> + bool bigjoiner;
> +
> + /* big joiner slave crtc? */
> + bool bigjoiner_slave;
> +
> + /* linked crtc for bigjoiner, either slave or master */
> + struct intel_crtc *bigjoiner_linked_crtc;
> +
> /* Display Stream compression state */
> struct {
> bool compression_enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5c7323af08b3..637ee7d0656a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2106,6 +2106,19 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
> pipe_config->lane_count = limits->max_lane_count;
>
> + if (adjusted_mode->crtc_clock > intel_dp_downstream_max_dotclock(intel_dp, false)) {
> + if (adjusted_mode->crtc_clock > intel_dp_downstream_max_dotclock(intel_dp, true)) {
> + DRM_DEBUG_KMS("Clock rate too high for big joiner\n");
> + return -EINVAL;
> + }
> + if (intel_dp_is_edp(intel_dp)) {
> + DRM_DEBUG_KMS("Cannot split eDP stream in bigjoiner configuration.\n");
> + return -EINVAL;
> + }
> + pipe_config->bigjoiner = true;
> + DRM_DEBUG_KMS("Using bigjoiner configuration\n");
> + }
> +
> if (intel_dp_is_edp(intel_dp)) {
> pipe_config->dsc_params.compressed_bpp =
> min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
> @@ -2123,12 +2136,12 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_config->lane_count,
> adjusted_mode->crtc_clock,
> adjusted_mode->crtc_hdisplay,
> - false);
> + pipe_config->bigjoiner);
> dsc_dp_slice_count =
> intel_dp_dsc_get_slice_count(intel_dp,
> adjusted_mode->crtc_clock,
> adjusted_mode->crtc_hdisplay,
> - false);
> + pipe_config->bigjoiner);
> if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
> DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
> return -EINVAL;
> @@ -2143,13 +2156,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> * is greater than the maximum Cdclock and if slice count is even
> * then we need to use 2 VDSC instances.
> */
> - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> - if (pipe_config->dsc_params.slice_count > 1) {
> - pipe_config->dsc_params.dsc_split = true;
> - } else {
> + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || pipe_config->bigjoiner) {
> + if (pipe_config->dsc_params.slice_count < 2) {
> DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
> return -EINVAL;
> }
> +
> + pipe_config->dsc_params.dsc_split = true;
> }
>
> ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2.
2019-10-08 19:40 ` Ville Syrjälä
@ 2019-10-10 12:42 ` Maarten Lankhorst
0 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-10 12:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 08-10-2019 om 21:40 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
>> When the clock is higher than the dotclock, try with 2 pipes enabled.
>> If we can enable 2, then we will go into big joiner mode, and steal
>> the adjacent crtc.
>>
>> This only links the crtc's in software, no hardware or plane
>> programming is done yet. Blobs are also copied from the master's
>> crtc_state, so it doesn't depend at commit time on the other
>> crtc_state.
>>
>> Changes since v1:
>> - Rename pipe timings to transcoder timings, as they are now different.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
>> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 218 ++++++++++++++++--
>> .../drm/i915/display/intel_display_types.h | 11 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
>> 5 files changed, 234 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index 4783d7ff4fcf..a5b11bd9da68 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
>> intel_crtc_put_color_blobs(crtc_state);
>> }
>>
>> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
>> + const struct intel_crtc_state *from_crtc_state)
>> {
>> intel_crtc_put_color_blobs(crtc_state);
>>
>> - if (crtc_state->uapi.degamma_lut)
>> + if (from_crtc_state->uapi.degamma_lut)
>> crtc_state->hw.degamma_lut =
>> - drm_property_blob_get(crtc_state->uapi.degamma_lut);
>> + drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
>> else
>> crtc_state->hw.degamma_lut = NULL;
>>
>> - if (crtc_state->uapi.gamma_lut)
>> + if (from_crtc_state->uapi.gamma_lut)
>> crtc_state->hw.gamma_lut =
>> - drm_property_blob_get(crtc_state->uapi.gamma_lut);
>> + drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
>> else
>> crtc_state->hw.gamma_lut = NULL;
>>
>> - if (crtc_state->uapi.ctm)
>> + if (from_crtc_state->uapi.ctm)
>> crtc_state->hw.ctm =
>> - drm_property_blob_get(crtc_state->uapi.ctm);
>> + drm_property_blob_get(from_crtc_state->uapi.ctm);
>> else
>> crtc_state->hw.ctm = NULL;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
>> index 42be91e0772a..8da84d64aa04 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
>> @@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
>> void intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct drm_crtc_state *state);
>> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
>> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
>> + const struct intel_crtc_state *from_crtc_state);
>> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>> void intel_atomic_state_clear(struct drm_atomic_state *state);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index caab8cfddcbd..c2b3c7b6f39b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -123,7 +123,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
>> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
>> struct drm_i915_gem_object *obj,
>> struct drm_mode_fb_cmd2 *mode_cmd);
>> -static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
>> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
>> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
>> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
>> const struct intel_link_m_n *m_n,
>> @@ -6308,7 +6308,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>> if (intel_crtc_has_dp_encoder(pipe_config))
>> intel_dp_set_m_n(pipe_config, M1_N1);
>>
>> - intel_set_pipe_timings(pipe_config);
>> + intel_set_transcoder_timings(pipe_config);
>> intel_set_pipe_src_size(pipe_config);
>>
>> if (pipe_config->has_pch_encoder) {
>> @@ -6435,7 +6435,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>> intel_dp_set_m_n(pipe_config, M1_N1);
>>
>> if (!transcoder_is_dsi(cpu_transcoder))
>> - intel_set_pipe_timings(pipe_config);
>> + intel_set_transcoder_timings(pipe_config);
>>
>> intel_set_pipe_src_size(pipe_config);
>>
>> @@ -6838,7 +6838,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>> if (intel_crtc_has_dp_encoder(pipe_config))
>> intel_dp_set_m_n(pipe_config, M1_N1);
>>
>> - intel_set_pipe_timings(pipe_config);
>> + intel_set_transcoder_timings(pipe_config);
>> intel_set_pipe_src_size(pipe_config);
>>
>> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>> @@ -6906,7 +6906,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>> if (intel_crtc_has_dp_encoder(pipe_config))
>> intel_dp_set_m_n(pipe_config, M1_N1);
>>
>> - intel_set_pipe_timings(pipe_config);
>> + intel_set_transcoder_timings(pipe_config);
>> intel_set_pipe_src_size(pipe_config);
>>
>> i9xx_set_pipeconf(pipe_config);
>> @@ -7396,7 +7396,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>> struct intel_crtc_state *pipe_config)
>> {
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>> int clock_limit = dev_priv->max_dotclk_freq;
>>
>> if (INTEL_GEN(dev_priv) < 4) {
>> @@ -7413,6 +7413,25 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>> }
>> }
>>
>> + /*
>> + * copy hw mode to transcoder mode.
>> + * This matters mostly for big joiner, which splits the mode in half.
>> + */
>> + pipe_config->hw.transcoder_mode = pipe_config->hw.adjusted_mode;
>> + if (pipe_config->bigjoiner) {
>> + /* Make sure the crtc config is halved horizontally */
>> + adjusted_mode->crtc_clock /= 2;
>> + adjusted_mode->crtc_hdisplay /= 2;
>> + adjusted_mode->crtc_hblank_start /= 2;
>> + adjusted_mode->crtc_hblank_end /= 2;
>> + adjusted_mode->crtc_hsync_start /= 2;
>> + adjusted_mode->crtc_hsync_end /= 2;
>> + adjusted_mode->crtc_htotal /= 2;
>> + adjusted_mode->crtc_hskew /= 2;
>> +
>> + pipe_config->pipe_src_w /= 2;
>> + }
> Hmm. Oh right, we still need to keep the full timings since
> the joiner is between the pipe and transcoder :/
>
> We probably need a check to make sure the non-halved horiz
> timings are even.
>
> hskew we don't use so don't need to frob that.
>
> I wonder if there are other places that need the full values. Quick
> glance only really reveals encoder and audio code. Most encoder code
> I guess doesn't really matter since bigjoiner is DP only. And the DP
> code itself looks fine since this halving happens after
> .compute_confog(). And the audio code only uses crtc_clock on HDMI
> (not sure it should use it there either, but that's a separate issue).
>
>> +
>> if (adjusted_mode->crtc_clock > clock_limit) {
>> DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
>> adjusted_mode->crtc_clock, clock_limit,
>> @@ -8114,13 +8133,13 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>> crtc_state->dpll_hw_state.dpll = dpll;
>> }
>>
>> -static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>> +static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> enum pipe pipe = crtc->pipe;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.transcoder_mode;
>> u32 crtc_vtotal, crtc_vblank_end;
>> int vsyncshift = 0;
>>
>> @@ -8205,8 +8224,8 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
>> return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
>> }
>>
>> -static void intel_get_pipe_timings(struct intel_crtc *crtc,
>> - struct intel_crtc_state *pipe_config)
>> +static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>> + struct intel_crtc_state *pipe_config)
> Missing the transcoder_mode readout + adjusted_mode/2 here?
>
>> {
>> struct drm_device *dev = crtc->base.dev;
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> @@ -8809,7 +8828,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>> if (INTEL_GEN(dev_priv) < 4)
>> pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>>
>> - intel_get_pipe_timings(crtc, pipe_config);
>> + intel_get_transcoder_timings(crtc, pipe_config);
>> intel_get_pipe_src_size(crtc, pipe_config);
>>
>> i9xx_get_pfit_config(crtc, pipe_config);
>> @@ -10045,7 +10064,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>> pipe_config->pixel_multiplier = 1;
>> }
>>
>> - intel_get_pipe_timings(crtc, pipe_config);
>> + intel_get_transcoder_timings(crtc, pipe_config);
>> intel_get_pipe_src_size(crtc, pipe_config);
>>
>> ironlake_get_pfit_config(crtc, pipe_config);
>> @@ -10445,7 +10464,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
>> INTEL_GEN(dev_priv) >= 11) {
>> haswell_get_ddi_port_state(crtc, pipe_config);
>> - intel_get_pipe_timings(crtc, pipe_config);
>> + intel_get_transcoder_timings(crtc, pipe_config);
>> }
>>
>> intel_get_pipe_src_size(crtc, pipe_config);
>> @@ -11814,6 +11833,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>>
>> if (mode_changed && crtc_state->hw.enable &&
>> dev_priv->display.crtc_compute_clock &&
>> + !crtc_state->bigjoiner_slave &&
>> !WARN_ON(crtc_state->shared_dpll)) {
>> ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
>> if (ret)
>> @@ -12278,7 +12298,7 @@ static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
>> crtc_state->hw.active = crtc_state->uapi.active;
>> crtc_state->hw.mode = crtc_state->uapi.mode;
>> crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
>> - intel_crtc_copy_color_blobs(crtc_state);
>> + intel_crtc_copy_color_blobs(crtc_state, crtc_state);
>> }
>>
>> static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
>> @@ -12286,7 +12306,48 @@ static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
>> crtc_state->uapi.enable = crtc_state->hw.enable;
>> crtc_state->uapi.active = crtc_state->hw.active;
>> crtc_state->uapi.mode = crtc_state->hw.mode;
>> - crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
>> + crtc_state->uapi.adjusted_mode = crtc_state->hw.transcoder_mode;
>> +}
>> +
>> +static int
>> +copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
>> + const struct intel_crtc_state *from_crtc_state)
>> +{
>> + struct intel_crtc_state *saved_state;
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> +
>> + saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
>> + if (!saved_state)
>> + return -ENOMEM;
>> +
>> + saved_state->uapi = crtc_state->uapi;
>> + saved_state->scaler_state = crtc_state->scaler_state;
>> + saved_state->shared_dpll = crtc_state->shared_dpll;
>> + saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
>> + saved_state->crc_enabled = crtc_state->crc_enabled;
>> +
>> + intel_crtc_free_hw_state(crtc_state);
>> + memcpy(crtc_state, saved_state, sizeof(*crtc_state));
>> + kfree(saved_state);
>> +
>> + /* Re-init hw state */
>> + memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
>> + crtc_state->hw.enable = from_crtc_state->hw.enable;
>> + crtc_state->hw.active = from_crtc_state->hw.active;
>> + crtc_state->hw.mode = from_crtc_state->hw.mode;
>> + crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
>> +
>> + /* Some fixups */
>> + crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
>> + crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
>> + crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
>> + crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
>> + crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
>> + crtc_state->bigjoiner_slave = true;
>> + crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
>> + crtc_state->has_audio = false;
>> +
>> + return 0;
>> }
>>
>> static int
>> @@ -12459,7 +12520,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>> base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
>>
>> /* uapi wants a copy of the adjusted_mode for vblank bookkeeping */
>> - pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
>> + pipe_config->uapi.adjusted_mode = pipe_config->hw.transcoder_mode;
>>
>> return 0;
>> }
>> @@ -13612,6 +13673,109 @@ static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
>> return 0;
>> }
>>
>> +static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> + struct intel_crtc_state *old_crtc_state, *new_crtc_state, *slave_crtc_state, *master_crtc_state;
>> + struct intel_crtc *crtc, *slave, *master;
>> + int i, ret = 0;
>> +
>> + if (INTEL_GEN(dev_priv) < 11)
>> + return 0;
>> +
>> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> + new_crtc_state, i) {
>> + if (!old_crtc_state->bigjoiner_slave)
> I keep thinking that points at the slave. "is_bigjoiner_slave" would be
> a less confusing name perhaps.
>
>> + continue;
>> +
>> + if (crtc->pipe == PIPE_A) {
>> + DRM_ERROR("Bigjoiner slave on pipe A?\n");
>> + return -EINVAL;
>> + }
> Dead code?
>
>> +
>> + /* crtc staying in slave mode? */
>> + if (!new_crtc_state->uapi.enable)
>> + continue;
>> +
>> + if (needs_modeset(new_crtc_state) || new_crtc_state->update_pipe) {
> Are these checks even needed? We've already determined we were a
> slave and the uapi crtc is now enabled, so we have to give the
> pipe back to the uapi user no matter what.
>
>> + master = old_crtc_state->bigjoiner_linked_crtc;
>> + master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
>> + if (IS_ERR(master_crtc_state))
>> + return PTR_ERR(master_crtc_state);
>> +
>> + /*
>> + * Force modeset on master, to recalculate bigjoiner
>> + * state.
>> + *
>> + * If master_crtc_state was not part of the atomic commit,
>> + * we will fail because the master was not deconfigured,
>> + * but at least fail below to unify the checks.
>> + */
>> + master_crtc_state->uapi.mode_changed = true;
>> +
>> + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>> + if (ret)
>> + return ret;
>> +
>> + ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
>> + if (ret)
>> + return ret;
> This whole thing feels a bit late to be doing it. Can't we just do this
> stuff before .compute_config()? Then at least in theory the master could
> have a chance to reconfigure itself to not use the bigjoiner? I suppose
> there is nothing it really can do to make the configuration work, but
> I think it would still feel like the more natural order of things.
>
>> + }
>> + }
>> +
>> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> + new_crtc_state, i) {
>> + if (!new_crtc_state->uapi.enable || !new_crtc_state->bigjoiner) {
>> + if (!old_crtc_state->bigjoiner)
>> + continue;
> I'm having a hard time decoding that. What are we trying to do?
Break and merge the bigjoiner slave configs. Although I guess we can probably do this inside the pipe check now. I may have made it too complicated before. :)
>
>> + }
>> +
>> + if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
>> + continue;
>> +
>> + if (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave) {
>> + if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
>> + DRM_DEBUG_KMS("Big joiner configuration requires CRTC + 1 to be used, doesn't exist\n");
>> + return -EINVAL;
>> + }
> I think we should be able to reject such a configuration already
> when we decided that we need to use the bigjoiner. Should probably
> write it with bitmasks to be future proof.
Yeah, see above. I think not future proofing is fine for now. :)
>> +
>> + slave = new_crtc_state->bigjoiner_linked_crtc =
>> + intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
>> + slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
>> + if (IS_ERR(slave_crtc_state))
>> + return PTR_ERR(slave_crtc_state);
>> +
>> + if (slave_crtc_state->uapi.enable) {
>> + DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires this CRTC to be unconfigured\n",
>> + slave->base.base.id, slave->base.name);
>> + return -EINVAL;
>> + } else {
>> + DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
>> + slave->base.base.id, slave->base.name);
>> + ret = copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
>> + }
>> + } else {
> I guess this means we're always looking to associate the bigjoiner
> master with the uapi crtc? I think in theory we should be able to
> handle the case where the slave is the uapi crtc as well. But maybe
> it doesn't matter so much as userspace probably picks crtcs in order
> anyway. Hmm, maybe it would even be hard to deal with that...
I think just doing the easy thing first makes it less likely to mess up. In theory we can do this, but I think it's not worth handling this special case.
>> + master = new_crtc_state->bigjoiner_linked_crtc;
>> + if (!master)
>> + continue;
>> +
>> + master_crtc_state = intel_atomic_get_crtc_state(&state->base, master);
>> + if (IS_ERR(master_crtc_state))
>> + return PTR_ERR(master_crtc_state);
>> +
>> + if (!master_crtc_state->uapi.enable && !new_crtc_state->uapi.enable) {
>> + DRM_DEBUG_KMS("[CRTC:%d:%s] Disabling slave from big joiner\n",
>> + crtc->base.base.id, crtc->base.name);
>> + ret = clear_intel_crtc_state(new_crtc_state);
>> + }
> This too feels like it could be done before we've compute anything.
>
> Something like this is what I was thinking earlier:
>
> detach_joiner() {
> master.bigjoiner = {};
> slave.bigjoiner = {};
> }
>
> setup_state_thing() {
> if (new_crtc_state->uapi.enable) {
> if (is_slave) {
> assert(needs_modeset(new_crtc_state));
> master = get_linked();
> master.modeset = true;
> detach_joiner();
> } else if (is_master) {
> slave = get_linked();
> if (needs_modeset(new_crtc_state)) {
> slave.modeset = true;
> detach_joiner();
> }
> }
> copy_uapi_to_hw(new_crtc_state);
> } else {
> if (is_master) {
> assert(needs_modeset(new_crtc_state));
> slave = get_linked();
> slave.modeset = true;
> detach_joiner();
> }
> if (!is_slave && needs_modeset(new_crtc_state))
> copy_uapi_to_hw(new_crtc_state);
> }
> }
>
> drm_atomic_helper_check_modeset();
> + setup_state_thing();
Yeah, can do it immediately after in intel_crtc_check_fastset(), will fix the series. :)
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^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH 16/24] drm/i915: Enable big joiner support in enable and disable sequences.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (14 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 17/24] drm/i915: Make hardware readout work on i915 Maarten Lankhorst
` (10 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
Also update timestamping constants, because slave crtc's are not
updated in drm_atomic_helper_update_legacy_modeset_state().
This should be enough to bring up CRTC's in a big joiner configuration,
without any plane configuration on the second pipe yet.
HOWEVER, we bring up the crtc's in the wrong order. We need to make
sure that the master crtc is brought up after the slave crtc, we
don't do that yet. This is done correctly later in this series.
The next steps are to add atomic commit, and make sure we enable and
update both master and slave in the correct order.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 55 ++-
drivers/gpu/drm/i915/display/intel_display.c | 402 ++++++++++++------
.../drm/i915/display/intel_display_types.h | 17 +
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 122 ++++--
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
6 files changed, 418 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 052caf2372d0..5ce11ebd88da 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1738,6 +1738,13 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
skl_ddi_clock_get(encoder, pipe_config);
else if (INTEL_GEN(dev_priv) <= 8)
hsw_ddi_clock_get(encoder, pipe_config);
+
+ if (pipe_config->bigjoiner) {
+ pipe_config->hw.transcoder_mode.crtc_clock =
+ pipe_config->hw.adjusted_mode.crtc_clock;
+
+ pipe_config->hw.adjusted_mode.crtc_clock /= 2;
+ }
}
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
@@ -2226,13 +2233,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
-
- /*
- * VDSC power is needed when DSC is enabled
- */
- if (crtc_state->dsc_params.compression_enable)
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
}
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -3428,7 +3428,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
/* 7.l */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3499,7 +3500,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -4113,19 +4115,18 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
crtc_state->min_voltage_level = 2;
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
- /* XXX: DSI transcoder paranoia */
- if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ if (!(temp & TRANS_DDI_FUNC_ENABLE))
return;
- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
else
@@ -4211,6 +4212,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
default:
break;
}
+}
+
+void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+
+ /* XXX: DSI transcoder paranoia */
+ if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ return;
+
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ if (pipe_config->bigjoiner_slave) {
+ /* read out pipe settings from master */
+ enum transcoder save = pipe_config->cpu_transcoder;
+
+ /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
+ WARN_ON(pipe_config->output_types);
+ pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ pipe_config->cpu_transcoder = save;
+ }
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -4235,7 +4259,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
}
- intel_ddi_clock_get(encoder, pipe_config);
+ if (!pipe_config->bigjoiner_slave)
+ intel_ddi_clock_get(encoder, pipe_config);
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c2b3c7b6f39b..fc6eb790c66b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6411,6 +6411,45 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_crtc_state *master_crtc_state;
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_encoder *encoder = NULL;
+ int i;
+
+ if (crtc_state->bigjoiner_slave)
+ master = crtc_state->bigjoiner_linked_crtc;
+
+ master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc != &master->base)
+ continue;
+
+ encoder = to_intel_encoder(conn_state->best_encoder);
+ break;
+ }
+
+ if (!crtc_state->bigjoiner_slave) {
+ /* need to enable VDSC, which we skipped in pre-enable */
+ intel_dsc_enable(encoder, crtc_state);
+ } else {
+ /*
+ * Enable sequence steps 1-7 on bigjoiner master
+ */
+ intel_encoders_pre_pll_enable(master, master_crtc_state, state);
+ intel_enable_shared_dpll(master_crtc_state);
+ intel_encoders_pre_enable(master, master_crtc_state, state);
+
+ /* and DSC on slave */
+ intel_dsc_enable(NULL, crtc_state);
+ }
+}
+
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
@@ -6424,37 +6463,38 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ if (!pipe_config->bigjoiner) {
+ intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
- if (pipe_config->shared_dpll)
- intel_enable_shared_dpll(pipe_config);
+ if (pipe_config->shared_dpll)
+ intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ } else {
+ icl_ddi_bigjoiner_pre_enable(state, pipe_config);
+ }
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ intel_set_pipe_src_size(pipe_config);
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(pipe_config);
- if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_transcoder_timings(pipe_config);
+ if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
+ if (intel_crtc_has_dp_encoder(pipe_config))
+ intel_dp_set_m_n(pipe_config, M1_N1);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_transcoder_timings(pipe_config);
- if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder)) {
- I915_WRITE(PIPE_MULT(cpu_transcoder),
- pipe_config->pixel_multiplier - 1);
- }
+ if (cpu_transcoder != TRANSCODER_EDP)
+ I915_WRITE(PIPE_MULT(cpu_transcoder),
+ pipe_config->pixel_multiplier - 1);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (pipe_config->has_pch_encoder) {
+ intel_cpu_transcoder_set_m_n(pipe_config,
+ &pipe_config->fdi_m_n, NULL);
+ }
- if (!transcoder_is_dsi(cpu_transcoder))
haswell_set_pipeconf(pipe_config);
-
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(pipe_config);
+ }
intel_crtc->active = true;
@@ -6482,9 +6522,11 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(intel_crtc);
- intel_ddi_set_pipe_settings(pipe_config);
- if (!transcoder_is_dsi(cpu_transcoder))
+ if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
+ intel_ddi_set_pipe_settings(pipe_config);
+
intel_ddi_enable_transcoder_func(pipe_config);
+ }
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(state, pipe_config);
@@ -6493,8 +6535,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
icl_pipe_mbus_enable(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
- if (!transcoder_is_dsi(cpu_transcoder))
+ if (!pipe_config->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder))
intel_enable_pipe(pipe_config);
+ else
+ trace_intel_pipe_enable(intel_crtc);
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
@@ -6625,9 +6669,27 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ if (old_crtc_state->bigjoiner) {
+ struct intel_crtc *master;
+ struct intel_crtc_state *master_crtc_state;
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ /* ports are disabled from the slave, after it deconfigures */
+ if (!old_crtc_state->bigjoiner_slave)
+ return;
+
+ master = old_crtc_state->bigjoiner_linked_crtc;
+ master_crtc_state = intel_atomic_get_old_crtc_state(state, master);
+
+ intel_ddi_disable_pipe_clock(old_crtc_state);
+
+ /* disable ports on the master crtc */
+ intel_encoders_post_disable(master, master_crtc_state, state);
+ intel_encoders_post_pll_disable(master, master_crtc_state, state);
+ } else {
+ intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+
+ intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ }
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -6791,6 +6853,9 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ if (crtc_state->dsc_params.compression_enable)
+ mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
+
return mask;
}
@@ -7379,6 +7444,19 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
return pixel_rate;
}
+static void intel_encoder_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ encoder->get_config(encoder, crtc_state);
+
+ crtc_state->hw.transcoder_mode.flags = crtc_state->hw.adjusted_mode.flags;
+
+ /* if transcoder clock is not set, assume same as adjusted_mode clock */
+ if (!crtc_state->hw.transcoder_mode.crtc_clock)
+ crtc_state->hw.transcoder_mode.crtc_clock =
+ crtc_state->hw.adjusted_mode.crtc_clock;
+}
+
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -8267,6 +8345,24 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
}
+
+ pipe_config->hw.transcoder_mode = pipe_config->hw.adjusted_mode;
+ if (pipe_config->bigjoiner) {
+ struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+
+ /*
+ * transcoder is programmed to the full mode,
+ * but pipje timings are half of the transcoder mode
+ */
+ adjusted_mode->crtc_hdisplay /= 2;
+ adjusted_mode->crtc_hblank_start /= 2;
+ adjusted_mode->crtc_hblank_end /= 2;
+ adjusted_mode->crtc_hsync_start /= 2;
+ adjusted_mode->crtc_hsync_end /= 2;
+ adjusted_mode->crtc_htotal /= 2;
+ adjusted_mode->crtc_hskew /= 2;
+ }
}
static void intel_get_pipe_src_size(struct intel_crtc *crtc,
@@ -8287,20 +8383,22 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config)
{
- mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
- mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
- mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
- mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
+ struct drm_display_mode *hw_mode = &pipe_config->hw.transcoder_mode;
- mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
- mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
- mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
- mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
+ mode->hdisplay = hw_mode->crtc_hdisplay;
+ mode->htotal = hw_mode->crtc_htotal;
+ mode->hsync_start = hw_mode->crtc_hsync_start;
+ mode->hsync_end = hw_mode->crtc_hsync_end;
- mode->flags = pipe_config->hw.adjusted_mode.flags;
+ mode->vdisplay = hw_mode->crtc_vdisplay;
+ mode->vtotal = hw_mode->crtc_vtotal;
+ mode->vsync_start = hw_mode->crtc_vsync_start;
+ mode->vsync_end = hw_mode->crtc_vsync_end;
+
+ mode->flags = hw_mode->flags;
mode->type = DRM_MODE_TYPE_DRIVER;
- mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
+ mode->clock = hw_mode->crtc_clock;
mode->hsync = drm_mode_hsync(mode);
mode->vrefresh = drm_mode_vrefresh(mode);
@@ -10387,6 +10485,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
u32 tmp;
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
+ if (!(tmp & TRANS_DDI_FUNC_ENABLE))
+ return;
if (INTEL_GEN(dev_priv) >= 12)
port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
@@ -10457,11 +10557,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
WARN_ON(active);
active = true;
}
+ intel_dsc_get_config(pipe_config);
- if (!active)
- goto out;
+ if (!active) {
+ /* bigjoiner slave doesn't enable transcoder */
+ if (!pipe_config->bigjoiner_slave)
+ goto out;
+
+ active = true;
+ pipe_config->pixel_multiplier = 1;
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+ /* we cannot read out most state, so don't bother.. */
+ pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
+ } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) {
haswell_get_ddi_port_state(crtc, pipe_config);
intel_get_transcoder_timings(crtc, pipe_config);
@@ -10538,7 +10646,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
}
}
- if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
+ if (pipe_config->bigjoiner_slave) {
+ /* Cannot be read out as a slave, set to 0. */
+ pipe_config->pixel_multiplier = 0;
+ } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
@@ -11502,7 +11613,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
return NULL;
}
- encoder->get_config(encoder, crtc_state);
+ intel_encoder_get_config(encoder, crtc_state);
intel_mode_from_pipe_config(mode, crtc_state);
@@ -12303,9 +12414,11 @@ static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
{
- crtc_state->uapi.enable = crtc_state->hw.enable;
- crtc_state->uapi.active = crtc_state->hw.active;
- crtc_state->uapi.mode = crtc_state->hw.mode;
+ if (!crtc_state->bigjoiner_slave) {
+ crtc_state->uapi.enable = crtc_state->hw.enable;
+ crtc_state->uapi.active = crtc_state->hw.active;
+ crtc_state->uapi.mode = crtc_state->hw.mode;
+ }
crtc_state->uapi.adjusted_mode = crtc_state->hw.transcoder_mode;
}
@@ -12336,6 +12449,7 @@ copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
crtc_state->hw.active = from_crtc_state->hw.active;
crtc_state->hw.mode = from_crtc_state->hw.mode;
crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
+ crtc_state->hw.transcoder_mode = from_crtc_state->hw.transcoder_mode;
/* Some fixups */
crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
@@ -12851,19 +12965,41 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
-
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ /* bigjoiner mode = transcoder mode / 2, for calculations */
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_hsync_end);
+
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.transcoder_mode.crtc_vsync_end);
+
+ PIPE_CONF_CHECK_FLAGS(hw.transcoder_mode.flags,
+ DRM_MODE_FLAG_INTERLACE);
+
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
+ PIPE_CONF_CHECK_FLAGS(hw.transcoder_mode.flags,
+ DRM_MODE_FLAG_PHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.transcoder_mode.flags,
+ DRM_MODE_FLAG_NHSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.transcoder_mode.flags,
+ DRM_MODE_FLAG_PVSYNC);
+ PIPE_CONF_CHECK_FLAGS(hw.transcoder_mode.flags,
+ DRM_MODE_FLAG_NVSYNC);
+ }
+ }
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -12875,24 +13011,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_BOOL(has_infoframe);
- PIPE_CONF_CHECK_BOOL(fec_enable);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_BOOL(fec_enable);
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_INTERLACE);
-
- if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
- DRM_MODE_FLAG_NVSYNC);
- }
-
PIPE_CONF_CHECK_X(gmch_pfit.control);
/* pfit ratios are autocomputed by the hw on gen4+ */
if (INTEL_GEN(dev_priv) < 4)
@@ -12916,7 +13039,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
- PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
+ PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
PIPE_CONF_CHECK_X(gamma_mode);
if (IS_CHERRYVIEW(dev_priv))
@@ -12935,48 +13059,50 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
PIPE_CONF_CHECK_P(shared_dpll);
+ if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
- PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
- PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
- PIPE_CONF_CHECK_X(dpll_hw_state.spll);
- PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
- PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
- PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
- PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
- PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
- PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
-
- PIPE_CONF_CHECK_X(dsi_pll.ctrl);
- PIPE_CONF_CHECK_X(dsi_pll.div);
-
- if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
- PIPE_CONF_CHECK_I(pipe_bpp);
-
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
-
- PIPE_CONF_CHECK_I(min_voltage_level);
+ PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.spll);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
+ PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+
+ PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+ PIPE_CONF_CHECK_X(dsi_pll.div);
+
+ if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+ PIPE_CONF_CHECK_I(pipe_bpp);
+
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+
+ PIPE_CONF_CHECK_I(min_voltage_level);
+ }
PIPE_CONF_CHECK_X(infoframes.enable);
PIPE_CONF_CHECK_X(infoframes.gcp);
@@ -12985,6 +13111,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_BOOL(bigjoiner);
+ PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
+ PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
+ PIPE_CONF_CHECK_BOOL(dsc_params.compression_enable);
+ PIPE_CONF_CHECK_BOOL(dsc_params.dsc_split);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
@@ -13239,6 +13371,7 @@ verify_crtc_state(struct intel_crtc *crtc,
struct intel_encoder *encoder;
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
+ struct intel_crtc *master = crtc;
bool active;
state = old_crtc_state->uapi.state;
@@ -13268,7 +13401,10 @@ verify_crtc_state(struct intel_crtc *crtc,
"(expected %i, found %i)\n",
new_crtc_state->hw.active, crtc->active);
- for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ if (new_crtc_state->bigjoiner_slave)
+ master = new_crtc_state->bigjoiner_linked_crtc;
+
+ for_each_encoder_on_crtc(dev, &master->base, encoder) {
enum pipe pipe;
active = encoder->get_hw_state(encoder, &pipe);
@@ -13277,12 +13413,12 @@ verify_crtc_state(struct intel_crtc *crtc,
encoder->base.base.id, active,
new_crtc_state->hw.active);
- I915_STATE_WARN(active && crtc->pipe != pipe,
+ I915_STATE_WARN(active && master->pipe != pipe,
"Encoder connected to wrong pipe %c\n",
pipe_name(pipe));
if (active)
- encoder->get_config(encoder, pipe_config);
+ intel_encoder_get_config(encoder, pipe_config);
}
intel_crtc_compute_pixel_rate(pipe_config);
@@ -14010,6 +14146,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
if (modeset) {
update_scanline_offset(new_crtc_state);
+ drm_calc_timestamping_constants(&crtc->base, &new_crtc_state->hw.transcoder_mode);
dev_priv->display.crtc_enable(new_crtc_state, state);
/* vblanks work again, re-enable pipe CRC. */
@@ -14100,7 +14237,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
*/
for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (!needs_modeset(new_crtc_state))
+ if (!needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner_slave)
continue;
intel_pre_plane_update(old_crtc_state, new_crtc_state);
@@ -14110,6 +14247,19 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
old_crtc_state,
new_crtc_state,
crtc);
+
+ if (old_crtc_state->bigjoiner) {
+ struct intel_crtc *slave = old_crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, slave);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, slave);
+
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave);
+ }
}
}
@@ -16527,7 +16677,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
for_each_intel_crtc(dev, crtc) {
struct intel_initial_plane_config plane_config = {};
- if (!crtc->active)
+ if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
/*
@@ -16983,7 +17133,17 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc_state = to_intel_crtc_state(crtc->base.state);
encoder->base.crtc = &crtc->base;
- encoder->get_config(encoder, crtc_state);
+ intel_encoder_get_config(encoder, crtc_state);
+
+ /* read out to slave crtc as well for bigjoiner */
+ if (crtc_state->bigjoiner) {
+ /* encoder should read be linked to bigjoiner master */
+ WARN_ON(crtc_state->bigjoiner_slave);
+
+ crtc = crtc_state->bigjoiner_linked_crtc;
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+ intel_encoder_get_config(encoder, crtc_state);
+ }
} else {
encoder->base.crtc = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6ce823943a69..a659dab8137a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -803,6 +803,7 @@ struct intel_crtc_state {
* accordingly.
*/
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
+#define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
unsigned long quirks;
unsigned fb_bits; /* framebuffers to flip */
@@ -1593,6 +1594,22 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
return i915_ggtt_offset(state->vma);
}
+static inline bool
+intel_crtc_supports_dsc(const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
+
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A)
+ return true;
+
+ return false;
+}
+
/* intel_atomic_plane.c */
struct intel_plane_state *
intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 637ee7d0656a..0e4b12ebc35f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1910,29 +1910,13 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
drm_dp_sink_supports_fec(intel_dp->fec_capable);
}
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- /* On TGL, DSC is supported on all Pipes */
- if (INTEL_GEN(dev_priv) >= 12)
- return true;
-
- if (INTEL_GEN(dev_priv) >= 10 &&
- pipe_config->cpu_transcoder != TRANSCODER_A)
- return true;
-
- return false;
-}
-
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
return false;
- return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
+ return intel_crtc_supports_dsc(pipe_config) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 38c181499505..11d4da9734a0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -480,11 +480,10 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
}
-static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_configure_pps_for_dsc_encoder(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -494,6 +493,9 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
int i = 0;
+ if (crtc_state->bigjoiner)
+ num_vdsc_instances *= 2;
+
/* Populate PICTURE_PARAMETER_SET_0 registers */
pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
DSC_VER_MIN_SHIFT |
@@ -899,74 +901,104 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
sizeof(dp_dsc_pps_sdp));
}
+static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL1;
+
+ return ICL_PIPE_DSS_CTL1(pipe);
+}
+
+static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
+{
+ enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+
+ if (crtc_state->cpu_transcoder == TRANSCODER_EDP)
+ return DSS_CTL2;
+
+ return ICL_PIPE_DSS_CTL2(pipe);
+}
+
void intel_dsc_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dss_ctl1_val = 0;
u32 dss_ctl2_val = 0;
if (!crtc_state->dsc_params.compression_enable)
return;
- /* Enable Power wells for VDSC/joining */
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
+ intel_configure_pps_for_dsc_encoder(crtc_state);
- intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
+ if (!crtc_state->bigjoiner_slave)
+ intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
- intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
-
- if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
- }
dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
if (crtc_state->dsc_params.dsc_split) {
dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
dss_ctl1_val |= JOINER_ENABLE;
}
- I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
- I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
+ if (crtc_state->bigjoiner) {
+ dss_ctl1_val |= BIG_JOINER_ENABLE;
+ if (!crtc_state->bigjoiner_slave)
+ dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
+ }
+ I915_WRITE(dss_ctl1_reg(crtc_state), dss_ctl1_val);
+ I915_WRITE(dss_ctl2_reg(crtc_state), dss_ctl2_val);
}
void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
- u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
if (!old_crtc_state->dsc_params.compression_enable)
return;
- if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
- dss_ctl1_reg = DSS_CTL1;
- dss_ctl2_reg = DSS_CTL2;
- } else {
- dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
- dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
+ I915_WRITE(dss_ctl1_reg(old_crtc_state), 0);
+ I915_WRITE(dss_ctl2_reg(old_crtc_state), 0);
+}
+
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 dss_ctl1_val, dss_ctl2_val;
+ intel_wakeref_t wakeref;
+
+ if (!intel_crtc_supports_dsc(crtc_state))
+ return;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv, intel_dsc_power_domain(crtc_state));
+ if (!wakeref)
+ return;
+
+ dss_ctl1_val = I915_READ(dss_ctl1_reg(crtc_state));
+ dss_ctl2_val = I915_READ(dss_ctl2_reg(crtc_state));
+ if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE)
+ crtc_state->dsc_params.compression_enable = true;
+
+ if ((dss_ctl1_val & JOINER_ENABLE) && (dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE))
+ crtc_state->dsc_params.dsc_split = true;
+
+ if (dss_ctl1_val & BIG_JOINER_ENABLE) {
+ crtc_state->bigjoiner = true;
+
+ if (!(dss_ctl1_val & MASTER_BIG_JOINER_ENABLE)) {
+ crtc_state->bigjoiner_slave = true;
+ if (!WARN_ON(crtc->pipe == PIPE_A))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
+ } else {
+ if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
+ crtc_state->bigjoiner_linked_crtc =
+ intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
+ }
}
- dss_ctl1_val = I915_READ(dss_ctl1_reg);
- if (dss_ctl1_val & JOINER_ENABLE)
- dss_ctl1_val &= ~JOINER_ENABLE;
- I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
-
- dss_ctl2_val = I915_READ(dss_ctl2_reg);
- if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
- dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
- dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
- RIGHT_BRANCH_VDSC_ENABLE);
- I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
-
- /* Disable Power wells for VDSC/joining */
- intel_display_power_put_unchecked(dev_priv,
- intel_dsc_power_domain(old_crtc_state));
+
+ intel_display_power_put(dev_priv, intel_dsc_power_domain(crtc_state), wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 90d3f6017fcb..569cf17402ba 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -15,6 +15,8 @@ void intel_dsc_enable(struct intel_encoder *encoder,
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config);
+void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
+
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
--
2.23.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 17/24] drm/i915: Make hardware readout work on i915.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (15 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 16/24] drm/i915: Enable big joiner support in enable and disable sequences Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 18/24] drm/i915: Remove special case slave handling during hw programming Maarten Lankhorst
` (9 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Unfortunately I have no way to test this, but it should be correct
if the bios sets up bigjoiner in a sane way.
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 65 +++++++++++++++++++-
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fc6eb790c66b..9add1197737c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3177,6 +3177,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(intel_crtc->base.state);
struct drm_framebuffer *fb;
if (!plane_config->fb)
@@ -3199,7 +3201,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
if (c == &intel_crtc->base)
continue;
- if (!to_intel_crtc(c)->active)
+ if (!to_intel_crtc_state(c->state)->uapi.active)
continue;
state = to_intel_plane_state(c->primary->state);
@@ -3221,6 +3223,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
* pretend the BIOS never had it enabled.
*/
intel_plane_disable_noatomic(intel_crtc, intel_plane);
+ if (crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ crtc_state->bigjoiner_linked_crtc;
+
+ intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
+ }
return;
@@ -9911,6 +9919,7 @@ static void
skylake_get_initial_plane_config(struct intel_crtc *crtc,
struct intel_initial_plane_config *plane_config)
{
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
@@ -10014,6 +10023,18 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->height = ((val >> 16) & 0xffff) + 1;
fb->width = ((val >> 0) & 0xffff) + 1;
+ /* add bigjoiner slave as well, if the fb stretches both */
+ if (crtc_state->bigjoiner) {
+ enum pipe bigjoiner_pipe = crtc_state->bigjoiner_linked_crtc->pipe;
+
+ if (fb->width == crtc_state->pipe_src_w &&
+ (I915_READ(PLANE_SURF(bigjoiner_pipe, plane_id)) & 0xfffff000) == plane_config->base) {
+ val = I915_READ(PLANE_SIZE(crtc_state->bigjoiner_linked_crtc->pipe, plane_id));
+ fb->height += ((val >> 16) & 0xfff) + 1;
+ fb->width += ((val >> 0) & 0x1fff) + 1;
+ }
+ }
+
val = I915_READ(PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
@@ -16907,7 +16928,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
- if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+ !crtc_state->bigjoiner_slave)
intel_crtc_disable_noatomic(&crtc->base, ctx);
if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
@@ -17196,6 +17218,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_plane *plane;
int min_cdclk = 0;
+ if (crtc_state->bigjoiner_slave)
+ continue;
+
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
if (crtc_state->hw.active) {
intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
@@ -17204,7 +17229,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
crtc_state);
crtc_state->hw.mode = crtc->base.mode;
- WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
+ if (!crtc_state->bigjoiner_slave)
+ WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
/*
* The initial mode needs to be set in order to keep
@@ -17250,6 +17276,39 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_bw_crtc_update(bw_state, crtc_state);
copy_hw_to_uapi_state(crtc_state);
intel_pipe_config_sanity_check(dev_priv, crtc_state);
+
+ /* discard our incomplete slave state, copy it from master */
+ if (crtc_state->bigjoiner && crtc_state->hw.active) {
+ struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *slave_crtc_state =
+ to_intel_crtc_state(slave->base.state);
+
+ copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
+ slave->base.mode = crtc->base.mode;
+
+ dev_priv->min_cdclk[slave->pipe] = min_cdclk;
+ dev_priv->min_voltage_level[slave->pipe] =
+ crtc_state->min_voltage_level;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ /*
+ * FIXME don't have the fb yet, so can't
+ * use intel_plane_data_rate() :(
+ */
+ if (plane_state->uapi.visible)
+ crtc_state->data_rate[plane->id] =
+ 4 * crtc_state->pixel_rate;
+ else
+ crtc_state->data_rate[plane->id] = 0;
+ }
+
+ intel_bw_crtc_update(bw_state, slave_crtc_state);
+ drm_calc_timestamping_constants(&slave->base,
+ &slave_crtc_state->hw.adjusted_mode);
+ }
}
}
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 18/24] drm/i915: Remove special case slave handling during hw programming
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (16 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 17/24] drm/i915: Make hardware readout work on i915 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 19/24] drm/i915: Link planes in a bigjoiner configuration, v2 Maarten Lankhorst
` (8 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 +---------
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 -
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 55 ++++++-------------
5 files changed, 39 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index ce75cf1dc65c..9947c08afb77 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -298,16 +298,6 @@ void intel_update_plane(struct intel_plane *plane,
plane->update_plane(plane, crtc_state, plane_state);
}
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- trace_intel_update_plane(&plane->base, crtc);
- plane->update_slave(plane, crtc_state, plane_state);
-}
-
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -340,25 +330,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.visible) {
+ if (new_plane_state->uapi.visible ||
+ new_plane_state->planar_slave) {
intel_update_plane(plane, new_crtc_state, new_plane_state);
- } else if (new_plane_state->planar_slave) {
- struct intel_plane *master =
- new_plane_state->planar_linked_plane;
-
- /*
- * We update the slave plane from this function because
- * programming it from the master plane's update_plane
- * callback runs into issues when the Y plane is
- * reassigned, disabled or used by a different plane.
- *
- * The slave plane is updated with the master plane's
- * plane_state.
- */
- new_plane_state =
- intel_atomic_get_new_plane_state(state, master);
-
- intel_update_slave(plane, new_crtc_state, new_plane_state);
} else {
intel_disable_plane(plane, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 123404a9cf23..726ececd6abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9add1197737c..d71fd7842849 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11934,6 +11934,24 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
crtc_state->active_planes |= BIT(linked->id);
crtc_state->update_planes |= BIT(linked->id);
DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
+
+ /* Copy parameters to slave plane */
+ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+ linked_state->color_ctl = plane_state->color_ctl;
+ linked_state->color_plane[0] = plane_state->color_plane[0];
+
+ linked_state->uapi.src = plane_state->uapi.src;
+ linked_state->uapi.dst = plane_state->uapi.dst;
+ intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+
+ if (icl_is_hdr_plane(dev_priv, plane->id)) {
+ if (linked->id == PLANE_SPRITE5)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
+ else if (linked->id == PLANE_SPRITE4)
+ plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+ else
+ MISSING_CASE(linked->id);
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a659dab8137a..0a9ea40f85e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -555,6 +555,9 @@ struct intel_plane_state {
/* plane color control register */
u32 color_ctl;
+ /* chroma upsampler control register */
+ u32 cus_ctl;
+
/*
* scaler_id
* = -1 : not using a scaler
@@ -1115,9 +1118,6 @@ struct intel_plane {
void (*update_plane)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
- void (*update_slave)(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void (*disable_plane)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index ce193367b96b..7515c373fdc8 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -528,7 +528,7 @@ static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- int color_plane, bool slave, u32 plane_ctl)
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
@@ -543,12 +543,12 @@ skl_program_plane(struct intel_plane *plane,
u32 y = plane_state->color_plane[color_plane].y;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- struct intel_plane *linked = plane_state->planar_linked_plane;
const struct drm_framebuffer *fb = plane_state->hw.fb;
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0;
unsigned long irqflags;
u32 keymsk, keymax;
+ u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -580,26 +580,8 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
(plane_state->color_plane[1].offset - surf_addr) | aux_stride);
- if (icl_is_hdr_plane(dev_priv, plane_id)) {
- u32 cus_ctl = 0;
-
- if (linked) {
- /* Enable and use MPEG-2 chroma siting */
- cus_ctl = PLANE_CUS_ENABLE |
- PLANE_CUS_HPHASE_0 |
- PLANE_CUS_VPHASE_SIGN_NEGATIVE |
- PLANE_CUS_VPHASE_0_25;
-
- if (linked->id == PLANE_SPRITE5)
- cus_ctl |= PLANE_CUS_PLANE_7;
- else if (linked->id == PLANE_SPRITE4)
- cus_ctl |= PLANE_CUS_PLANE_6;
- else
- MISSING_CASE(linked->id);
- }
-
- I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
- }
+ if (icl_is_hdr_plane(dev_priv, plane_id))
+ I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
@@ -629,7 +611,7 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + surf_addr);
- if (!slave && plane_state->scaler_id >= 0)
+ if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -642,24 +624,13 @@ skl_update_plane(struct intel_plane *plane,
{
int color_plane = 0;
- if (plane_state->planar_linked_plane) {
+ if (drm_format_info_is_yuv_semiplanar(plane_state->hw.fb->format) &&
+ !plane_state->planar_slave)
/* Program the UV plane */
color_plane = 1;
- }
- skl_program_plane(plane, crtc_state, plane_state,
- color_plane, false, plane_state->ctl);
+ skl_program_plane(plane, crtc_state, plane_state, color_plane);
}
-
-static void
-icl_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- skl_program_plane(plane, crtc_state, plane_state, 0, true,
- plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
-}
-
static void
skl_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
@@ -1846,6 +1817,14 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
plane_state);
+ if (icl_is_hdr_plane(dev_priv, plane->id) && fb->format->is_yuv)
+ /* Enable and use MPEG-2 chroma siting */
+ plane_state->cus_ctl = PLANE_CUS_ENABLE |
+ PLANE_CUS_HPHASE_0 |
+ PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
+ else
+ plane_state->cus_ctl = 0;
+
return 0;
}
@@ -2514,8 +2493,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->disable_plane = skl_disable_plane;
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
- if (icl_is_nv12_y_plane(plane_id))
- plane->update_slave = icl_update_slave;
if (INTEL_GEN(dev_priv) >= 11)
formats = icl_get_plane_formats(dev_priv, pipe,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 19/24] drm/i915: Link planes in a bigjoiner configuration, v2.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (17 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 18/24] drm/i915: Remove special case slave handling during hw programming Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 20/24] drm/i915: Add bigjoiner aware plane clipping checks Maarten Lankhorst
` (7 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, we may end up adding a lot of planes, so we have to keep
iterating until we no longer add any planes.
Also fix the atomic intel plane iterator, so things watermarks start
working automagically.
Changes since v1:
- Rebase on top of plane_state split, cleaning up the code a lot.
- Make intel_atomic_crtc_state_for_each_plane_state() bigjoiner capable.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 47 +++++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 158 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 16 +-
.../drm/i915/display/intel_display_types.h | 11 ++
5 files changed, 211 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 9947c08afb77..08860be6d9ac 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -143,10 +143,15 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
-void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state)
{
- plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ if (from_plane_state->uapi.crtc)
+ plane_state->hw.crtc = crtc_state->uapi.crtc;
+ else
+ plane_state->hw.crtc = NULL;
+
plane_state->hw.fb = from_plane_state->uapi.fb;
if (plane_state->hw.fb)
drm_framebuffer_get(plane_state->hw.fb);
@@ -165,10 +170,20 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
struct intel_plane_state *new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+ struct intel_plane_state *new_master_plane_state = new_plane_state;
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_plane_state->uapi.state);
const struct drm_framebuffer *fb;
int ret;
- intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ if (new_plane_state->bigjoiner_slave)
+ new_master_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ new_plane_state->bigjoiner_plane);
+
+ intel_plane_copy_uapi_to_hw_state(new_crtc_state,
+ new_plane_state,
+ new_master_plane_state);
fb = new_plane_state->hw.fb;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -207,15 +222,36 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
}
static struct intel_crtc *
-get_crtc_from_states(const struct intel_plane_state *old_plane_state,
+get_crtc_from_states(struct intel_atomic_state *state,
+ const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
+
if (new_plane_state->uapi.crtc)
return to_intel_crtc(new_plane_state->uapi.crtc);
if (old_plane_state->uapi.crtc)
return to_intel_crtc(old_plane_state->uapi.crtc);
+ if (new_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *new_master_plane_state =
+ intel_atomic_get_new_plane_state(state, new_plane_state->bigjoiner_plane);
+
+ /* need to use uapi here, new_master_plane_state might not be copied to hw yet */
+ if (new_master_plane_state->uapi.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
+ if (old_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *old_master_plane_state =
+ intel_atomic_get_old_plane_state(state, old_plane_state->bigjoiner_plane);
+
+ if (old_master_plane_state->uapi.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
return NULL;
}
@@ -227,7 +263,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
struct intel_crtc *crtc =
- get_crtc_from_states(old_plane_state, new_plane_state);
+ get_crtc_from_states(state, old_plane_state,
+ new_plane_state);
const struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 726ececd6abd..e40d6e4e913b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,7 +20,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
const struct intel_plane_state *from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d71fd7842849..b88cd8f99a32 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3275,7 +3275,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
plane_state->fb = fb;
plane_state->crtc = &intel_crtc->base;
- intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
+ intel_plane_copy_uapi_to_hw_state(crtc_state, intel_state, intel_state);
atomic_or(to_intel_plane(primary)->frontbuffer_bit,
&to_intel_frontbuffer(fb)->bits);
@@ -11844,24 +11844,101 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
return true;
}
+static int icl_add_dependent_planes(struct intel_atomic_state *state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane_state *new_plane_state;
+ struct intel_plane *plane;
+ int ret = 0;
+
+ plane = plane_state->bigjoiner_plane;
+ if (plane && !intel_atomic_get_new_plane_state(state, plane)) {
+ new_plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(new_plane_state))
+ return PTR_ERR(new_plane_state);
+
+ ret = 1;
+ }
+
+ plane = plane_state->planar_linked_plane;
+ if (plane && !intel_atomic_get_new_plane_state(state, plane)) {
+ new_plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(new_plane_state))
+ return PTR_ERR(new_plane_state);
+
+ ret = 1;
+ }
+
+ return ret;
+}
+
static int icl_add_linked_planes(struct intel_atomic_state *state)
{
- struct intel_plane *plane, *linked;
- struct intel_plane_state *plane_state, *linked_plane_state;
+ struct intel_plane *plane;
+ struct intel_plane_state *old_plane_state, *new_plane_state;
+ struct intel_crtc *crtc, *linked_crtc;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state, *linked_crtc_state;
+ bool added;
int i;
- for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- linked = plane_state->planar_linked_plane;
+ /*
+ * Iteratively add plane_state->linked_plane and plane_state->bigjoiner_plane
+ *
+ * This needs to be done repeatedly, because of is a funny interaction;
+ * the Y-plane may be assigned differently on the other bigjoiner crtc,
+ * and we could end up with the following evil recursion, when only adding a
+ * single plane to state:
+ *
+ * XRGB8888 master plane 6 adds NV12 slave Y-plane 6, which adds slave UV plane 0,
+ * which adds master UV plane 0, which adds master Y-plane 7, which adds XRGB8888
+ * slave plane 7.
+ *
+ * We could pull in even more because of old_plane_state vs new_plane_state.
+ *
+ * Max depth = 5 (or 7 for evil case) in this case.
+ * Number of passes will be less, because newly added planes show up in the
+ * same iteration round when added_plane->index > plane->index.
+ */
+ do {
+ added = false;
- if (!linked)
- continue;
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
+ int ret, ret2;
- linked_plane_state = intel_atomic_get_plane_state(state, linked);
- if (IS_ERR(linked_plane_state))
- return PTR_ERR(linked_plane_state);
+ ret = icl_add_dependent_planes(state, old_plane_state);
+ if (ret < 0)
+ return ret;
+
+ ret2 = icl_add_dependent_planes(state, new_plane_state);
+ if (ret2 < 0)
+ return ret2;
+
+ added |= ret || ret2;
+ }
+ } while (added);
- WARN_ON(linked_plane_state->planar_linked_plane != plane);
- WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
+ /*
+ * Make sure bigjoiner slave crtc's are also pulled in. This is not done automatically
+ * when adding slave planes, because plane_state->crtc is null.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ linked_crtc = old_crtc_state->bigjoiner_linked_crtc;
+ if (linked_crtc) {
+ linked_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, linked_crtc);
+
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
+
+ linked_crtc = new_crtc_state->bigjoiner_linked_crtc;
+ if (linked_crtc && linked_crtc != old_crtc_state->bigjoiner_linked_crtc) {
+ linked_crtc_state =
+ intel_atomic_get_crtc_state(&state->base, linked_crtc);
+
+ if (IS_ERR(linked_crtc_state))
+ return PTR_ERR(linked_crtc_state);
+ }
}
return 0;
@@ -11901,6 +11978,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct intel_plane_state *linked_state = NULL;
+ struct intel_plane_state *master_plane_state;
if (plane->pipe != crtc->pipe ||
!(crtc_state->nv12_planes & BIT(plane->id)))
@@ -11940,9 +12018,16 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
linked_state->color_ctl = plane_state->color_ctl;
linked_state->color_plane[0] = plane_state->color_plane[0];
- linked_state->uapi.src = plane_state->uapi.src;
- linked_state->uapi.dst = plane_state->uapi.dst;
- intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+ master_plane_state = plane_state;
+ if (plane_state->bigjoiner_slave)
+ master_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ plane_state->bigjoiner_plane);
+
+ linked_state->uapi.src = master_plane_state->uapi.src;
+ linked_state->uapi.dst = master_plane_state->uapi.dst;
+ intel_plane_copy_uapi_to_hw_state(crtc_state, linked_state,
+ master_plane_state);
if (icl_is_hdr_plane(dev_priv, plane->id)) {
if (linked->id == PLANE_SPRITE5)
@@ -13853,6 +13938,7 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state, *new_crtc_state, *slave_crtc_state, *master_crtc_state;
struct intel_crtc *crtc, *slave, *master;
+ struct intel_plane *plane;
int i, ret = 0;
if (INTEL_GEN(dev_priv) < 11)
@@ -13948,6 +14034,48 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state)
return ret;
}
+ /*
+ * Setup and teardown the new bigjoiner plane mappings.
+ */
+ for_each_intel_plane(&dev_priv->drm, plane) {
+ struct intel_plane_state *plane_state;
+ struct intel_plane *other_plane = NULL;
+
+ crtc = intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!new_crtc_state || !needs_modeset(new_crtc_state))
+ continue;
+
+ if (new_crtc_state->bigjoiner) {
+ struct intel_crtc *other_crtc =
+ new_crtc_state->bigjoiner_linked_crtc;
+ bool found = false;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, other_crtc, other_plane) {
+ if (other_plane->id != plane->id)
+ continue;
+
+ found = true;
+ break;
+ }
+
+ /* All pipes should have identical planes. */
+ if (WARN_ON(!found))
+ return -EINVAL;
+ } else if (!old_crtc_state->bigjoiner) {
+ continue;
+ }
+
+ plane_state = intel_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+
+ plane_state->bigjoiner_plane = other_plane;
+ plane_state->bigjoiner_slave = new_crtc_state->bigjoiner_slave;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 44a1c331d6b9..505d6fd1377e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -444,9 +444,19 @@ enum phy_fia {
plane, plane_state, \
crtc_state) \
for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
- ((crtc_state)->uapi.plane_mask)) \
- for_each_if ((plane_state = \
- to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
+ (((crtc_state)->bigjoiner_slave ? \
+ intel_atomic_get_new_crtc_state( \
+ to_intel_atomic_state((crtc_state)->uapi.state), \
+ (crtc_state)->bigjoiner_linked_crtc) : \
+ (crtc_state))->uapi.plane_mask)) \
+ for_each_if ((((plane_state) = \
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))), \
+ ((plane) = (plane_state)->bigjoiner_slave ? \
+ (plane_state)->bigjoiner_plane : \
+ (plane)), \
+ ((plane_state) = (plane_state)->bigjoiner_slave ? \
+ to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)) : \
+ (plane_state))))
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0a9ea40f85e1..32849ad176c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -588,6 +588,17 @@ struct intel_plane_state {
*/
struct intel_plane *planar_linked_plane;
+ /*
+ * bigjoiner_plane:
+ *
+ * When 2 pipes are joined in a bigjoiner configuration,
+ * points to the same plane on the other pipe.
+ *
+ * bigjoiner_slave is set on the slave pipe.
+ */
+ struct intel_plane *bigjoiner_plane;
+ u32 bigjoiner_slave;
+
/*
* planar_slave:
* If set don't update use the linked plane's state for updating
--
2.23.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 20/24] drm/i915: Add bigjoiner aware plane clipping checks
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (18 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 19/24] drm/i915: Link planes in a bigjoiner configuration, v2 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 21/24] drm/i915: Ensure color blobs are copied to slave before planes are checked Maarten Lankhorst
` (6 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++++++++++++++++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
drivers/gpu/drm/i915/display/intel_display.c | 19 +++---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 +++----
4 files changed, 80 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 08860be6d9ac..26bbea262e57 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -162,6 +162,9 @@ void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state *crtc_state
plane_state->hw.rotation = from_plane_state->uapi.rotation;
plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
plane_state->hw.color_range = from_plane_state->uapi.color_range;
+
+ plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
+ plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
}
int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
@@ -428,6 +431,63 @@ intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
return plane_state;
}
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position)
+{
+ struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
+ struct drm_rect *dst = &plane_state->uapi.dst;
+ unsigned int rotation = plane_state->uapi.rotation;
+ struct drm_rect clip = {};
+ int hscale, vscale;
+
+ if (!fb) {
+ plane_state->uapi.visible = false;
+ return 0;
+ }
+
+ drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
+
+ /* Check scaling */
+ hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
+ vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
+ if (hscale < 0 || vscale < 0) {
+ DRM_DEBUG_KMS("Invalid scaling of plane\n");
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+ return -ERANGE;
+ }
+
+ if (crtc_state->hw.enable) {
+ clip.x2 = crtc_state->pipe_src_w;
+ clip.y2 = crtc_state->pipe_src_h;
+ }
+
+ /* right side of the image is on the slave crtc, adjust dst to match */
+ if (crtc_state->bigjoiner_slave)
+ drm_rect_translate(dst, -crtc_state->pipe_src_w, 0);
+
+ /*
+ * FIXME: This might need further adjustment for seamless scaling
+ * with phase information, for the 2p2 and 2p1 scenarios.
+ */
+ plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, &clip);
+
+ drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
+
+ if (!can_position && plane_state->uapi.visible &&
+ !drm_rect_equals(dst, &clip)) {
+ DRM_DEBUG_KMS("Plane must cover entire CRTC\n");
+ drm_rect_debug_print("dst: ", dst, false);
+ drm_rect_debug_print("clip: ", &clip, false);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index e40d6e4e913b..16e1fb4ae596 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -47,5 +47,9 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state *old_plane_state,
struct intel_plane_state *plane_state);
+int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
+ struct intel_crtc_state *crtc_state,
+ int min_scale, int max_scale,
+ bool can_position);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b88cd8f99a32..66d7eaedcea3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3769,12 +3769,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- i9xx_plane_has_windowing(plane),
- true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ i9xx_plane_has_windowing(plane));
if (ret)
return ret;
@@ -10783,11 +10781,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7515c373fdc8..3213ea0bd838 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1559,10 +1559,8 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
}
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
@@ -1616,11 +1614,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true);
if (ret)
return ret;
@@ -1781,10 +1778,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
max_scale = skl_max_scale(crtc_state, fb->format);
}
- ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
- &crtc_state->uapi,
- min_scale, max_scale,
- true, true);
+ ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
+ min_scale, max_scale, true);
if (ret)
return ret;
--
2.23.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 21/24] drm/i915: Ensure color blobs are copied to slave before planes are checked
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (19 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 20/24] drm/i915: Add bigjoiner aware plane clipping checks Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 22/24] drm/i915: Add intel_update_bigjoiner handling Maarten Lankhorst
` (5 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
This is required to ensure property blobs are correctly copied on bigjoiner
slaves. Only at this point we are sure that the slave crtc is part of the state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 66d7eaedcea3..0d9d4e2d61c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11935,6 +11935,16 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
if (IS_ERR(linked_crtc_state))
return PTR_ERR(linked_crtc_state);
+
+ if (needs_modeset(new_crtc_state) || new_crtc_state->update_pipe ||
+ new_crtc_state->uapi.color_mgmt_changed) {
+ if (new_crtc_state->bigjoiner_slave)
+ intel_crtc_copy_color_blobs(new_crtc_state,
+ linked_crtc_state);
+ else
+ intel_crtc_copy_color_blobs(linked_crtc_state,
+ new_crtc_state);
+ }
}
}
--
2.23.0
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^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 22/24] drm/i915: Add intel_update_bigjoiner handling.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (20 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 21/24] drm/i915: Ensure color blobs are copied to slave before planes are checked Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 23/24] drm/i915: Add debugfs dumping for bigjoiner, v2 Maarten Lankhorst
` (4 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
Enabling is done in a special sequence and to be fair, so should
plane updates be. Ideally the end user never notices the second
pipe is used, so use the vblank evasion to cover both pipes.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
The disable sequence still needs some love, but otherwise bigjoiner
is close to ready now.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 22 +++-
drivers/gpu/drm/i915/display/intel_sprite.h | 3 +-
3 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0d9d4e2d61c6..46e3e8296251 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14349,7 +14349,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
else
i9xx_update_planes_on_crtc(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(new_crtc_state, NULL);
/*
* We usually enable FIFO underrun interrupts as part of the
@@ -14437,6 +14437,56 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
}
}
+static void intel_update_bigjoiner(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ bool modeset = needs_modeset(new_crtc_state);
+ struct intel_crtc *slave = new_crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ if (modeset) {
+ /* Enable slave first */
+ update_scanline_offset(new_slave_crtc_state);
+ drm_calc_timestamping_constants(&slave->base, &new_slave_crtc_state->hw.transcoder_mode);
+ dev_priv->display.crtc_enable(new_slave_crtc_state, state);
+
+ /* Then master */
+ update_scanline_offset(new_crtc_state);
+ drm_calc_timestamping_constants(&crtc->base, &new_crtc_state->hw.transcoder_mode);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+
+ /* vblanks work again, re-enable pipe CRC. */
+ intel_crtc_enable_pipe_crc(crtc);
+
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+
+ if (new_crtc_state->update_pipe)
+ intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ }
+
+ /*
+ * Perform vblank evasion around commit operation, and make sure to
+ * commit both planes simultaneously for best results.
+ */
+ intel_pipe_update_start(new_crtc_state);
+
+ commit_pipe_config(state, old_crtc_state, new_crtc_state);
+ commit_pipe_config(state, old_slave_crtc_state, new_slave_crtc_state);
+
+ skl_update_planes_on_crtc(state, crtc);
+ skl_update_planes_on_crtc(state, slave);
+
+ intel_pipe_update_end(new_crtc_state, new_slave_crtc_state);
+}
+
static void intel_commit_modeset_enables(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
@@ -14455,7 +14505,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc, *slave;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
unsigned int updated = 0;
bool progress;
@@ -14464,11 +14514,47 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
u8 required_slices = state->wm_results.ddb.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+ struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
+ const struct intel_crtc_state *slave_crtc_state;
+ u32 dirty_pipes = state->wm_results.dirty_pipes;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (new_crtc_state->bigjoiner_slave) {
+ /* clear dirty bit, we're updated in master */
+ dirty_pipes &= ~drm_crtc_mask(&crtc->base);
+ continue;
+ }
+
+ if (new_crtc_state->hw.active) {
+ if (new_crtc_state->bigjoiner) {
+ slave = new_crtc_state->bigjoiner_linked_crtc;
+ slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+ slave);
+
+ /* put both entries in */
+ new_entries[i].start = new_crtc_state->wm.skl.ddb.start;
+ new_entries[i].end = slave_crtc_state->wm.skl.ddb.end;
+ } else {
+ new_entries[i] = new_crtc_state->wm.skl.ddb;
+ }
+ }
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
/* ignore allocations for crtc's that have been turned off. */
- if (new_crtc_state->hw.active)
+ if (!new_crtc_state->hw.active || needs_modeset(new_crtc_state))
+ continue;
+
+ if (old_crtc_state->bigjoiner) {
+ slave = old_crtc_state->bigjoiner_linked_crtc;
+ slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ entries[i].start = old_crtc_state->wm.skl.ddb.start;
+ entries[i].end = slave_crtc_state->wm.skl.ddb.end;
+ } else {
entries[i] = old_crtc_state->wm.skl.ddb;
+ }
+ }
/* If 2nd DBuf slice required, enable it here */
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
@@ -14489,16 +14575,15 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
pipe = crtc->pipe;
- if (updated & cmask || !new_crtc_state->hw.active)
+ if (updated & cmask || !new_crtc_state->hw.active ||
+ new_crtc_state->bigjoiner_slave)
continue;
- if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
- entries,
+ if (skl_ddb_allocation_overlaps(&new_entries[i], entries,
INTEL_NUM_PIPES(dev_priv), i))
continue;
updated |= cmask;
- entries[i] = new_crtc_state->wm.skl.ddb;
/*
* If this is an already active pipe, it's DDB changed,
@@ -14506,18 +14591,23 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
- &old_crtc_state->wm.skl.ddb) &&
- !new_crtc_state->uapi.active_changed &&
- state->wm_results.dirty_pipes != updated)
+ if (!skl_ddb_entry_equal(&entries[i], &new_entries[i]) &&
+ !needs_modeset(new_crtc_state) &&
+ dirty_pipes != updated)
vbl_wait = true;
- intel_update_crtc(crtc, state, old_crtc_state,
- new_crtc_state);
+ if (new_crtc_state->bigjoiner)
+ intel_update_bigjoiner(crtc, state,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
if (vbl_wait)
intel_wait_for_vblank(dev_priv, pipe);
+ entries[i] = new_entries[i];
progress = true;
}
} while (progress);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 3213ea0bd838..272c08fa5d1b 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -98,6 +98,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
/* FIXME needs to be calibrated sensibly */
min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ new_crtc_state->bigjoiner ?
+ 2 * VBLANK_EVASION_TIME_US :
VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
@@ -188,7 +190,8 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
* re-enables interrupts and verifies the update was actually completed
* before a vblank.
*/
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state,
+ struct intel_crtc_state *slave_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
@@ -203,15 +206,24 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
* while ... */
- if (new_crtc_state->uapi.event) {
- WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
+ if (new_crtc_state->uapi.event || (slave_crtc_state && slave_crtc_state->uapi.event)) {
+ if (new_crtc_state->uapi.event)
+ WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
+ if (slave_crtc_state && slave_crtc_state->uapi.event)
+ WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
spin_lock(&crtc->base.dev->event_lock);
- drm_crtc_arm_vblank_event(&crtc->base,
- new_crtc_state->uapi.event);
+ if (new_crtc_state->uapi.event)
+ drm_crtc_arm_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
+ if (slave_crtc_state && slave_crtc_state->uapi.event)
+ drm_crtc_arm_vblank_event(&crtc->base,
+ slave_crtc_state->uapi.event);
spin_unlock(&crtc->base.dev->event_lock);
new_crtc_state->uapi.event = NULL;
+ if (slave_crtc_state)
+ slave_crtc_state->uapi.event = NULL;
}
local_irq_enable();
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 229336214f68..6df62fae9368 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -24,7 +24,8 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state,
+ struct intel_crtc_state *slave_crtc_state);
int intel_plane_check_stride(const struct intel_plane_state *plane_state);
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 23/24] drm/i915: Add debugfs dumping for bigjoiner, v2.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (21 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 22/24] drm/i915: Add intel_update_bigjoiner handling Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 11:35 ` [PATCH 24/24] semi-hax: drm/i915: Always verify ddb allocation Maarten Lankhorst
` (3 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
It's useful to know what the actual clipped state is, rather than
the unclipped crtc properties.
This is useful when a plane is spread across 2 crtc's, where the
slave crtc has no own plane properties but derives its clipped
values from the master crtc.
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++++++++++++--------------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7ce3ae1ec586..2a7fefdda96f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2657,6 +2657,17 @@ static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation)
rotation);
}
+static const char *plane_visibility(struct intel_plane_state *plane_state)
+{
+ if (plane_state->uapi.visible)
+ return "visible";
+
+ if (plane_state->planar_slave)
+ return "planar-slave";
+
+ return "hidden";
+}
+
static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2664,42 +2675,29 @@ static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
struct intel_plane *intel_plane;
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- struct drm_plane_state *state;
+ struct intel_plane_state *state;
struct drm_plane *plane = &intel_plane->base;
struct drm_format_name_buf format_name;
char rot_str[48];
- if (!plane->state) {
- seq_puts(m, "plane->state is NULL!\n");
- continue;
- }
-
- state = plane->state;
+ state = to_intel_plane_state(plane->state);
- if (state->fb) {
- drm_get_format_name(state->fb->format->format,
+ if (state->hw.fb) {
+ drm_get_format_name(state->hw.fb->format->format,
&format_name);
} else {
sprintf(format_name.str, "N/A");
}
- plane_rotation(rot_str, sizeof(rot_str), state->rotation);
+ plane_rotation(rot_str, sizeof(rot_str), state->hw.rotation);
- seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
+ seq_printf(m, "\t--Plane id %d: type=%s, %s, clipped crtc="DRM_RECT_FMT", clipped src="DRM_RECT_FP_FMT", format=%s, rotation=%s\n",
plane->base.id,
plane_type(intel_plane->base.type),
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h,
- (state->src_x >> 16),
- ((state->src_x & 0xffff) * 15625) >> 10,
- (state->src_y >> 16),
- ((state->src_y & 0xffff) * 15625) >> 10,
- (state->src_w >> 16),
- ((state->src_w & 0xffff) * 15625) >> 10,
- (state->src_h >> 16),
- ((state->src_h & 0xffff) * 15625) >> 10,
- format_name.str,
- rot_str);
+ plane_visibility(state),
+ DRM_RECT_ARG(&state->uapi.dst),
+ DRM_RECT_FP_ARG(&state->uapi.src),
+ format_name.str, rot_str);
}
}
@@ -2755,6 +2753,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
yesno(pipe_config->hw.active),
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
yesno(pipe_config->dither), pipe_config->pipe_bpp);
+ if (pipe_config->bigjoiner)
+ seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
+ pipe_config->bigjoiner_linked_crtc->base.base.id,
+ pipe_config->bigjoiner_linked_crtc->base.name,
+ pipe_config->bigjoiner_slave ? "slave" : "master");
if (pipe_config->hw.active) {
struct intel_plane *cursor =
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH 24/24] semi-hax: drm/i915: Always verify ddb allocation
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (22 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 23/24] drm/i915: Add debugfs dumping for bigjoiner, v2 Maarten Lankhorst
@ 2019-10-04 11:35 ` Maarten Lankhorst
2019-10-04 14:23 ` [PATCH] " Maarten Lankhorst
2019-10-04 13:10 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach Patchwork
` (2 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 11:35 UTC (permalink / raw)
To: intel-gfx
And only verify cursor allocation when cursor plane is active.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 46e3e8296251..34c4a558a56b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13369,7 +13369,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
* allocation. In that case since the ddb allocation will be updated
* once the plane becomes visible, we can skip this check
*/
- if (1) {
+ if (CURCNTR(pipe) & MCURSOR_MODE) {
struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
@@ -13665,10 +13665,11 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ verify_wm_state(crtc, new_crtc_state);
+
if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
return;
- verify_wm_state(crtc, new_crtc_state);
verify_connector_state(state, crtc);
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH] semi-hax: drm/i915: Always verify ddb allocation
2019-10-04 11:35 ` [PATCH 24/24] semi-hax: drm/i915: Always verify ddb allocation Maarten Lankhorst
@ 2019-10-04 14:23 ` Maarten Lankhorst
0 siblings, 0 replies; 60+ messages in thread
From: Maarten Lankhorst @ 2019-10-04 14:23 UTC (permalink / raw)
To: intel-gfx
And only verify cursor allocation when cursor plane is active.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 46e3e8296251..6bdff08cf9c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13369,7 +13369,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
* allocation. In that case since the ddb allocation will be updated
* once the plane becomes visible, we can skip this check
*/
- if (1) {
+ if (I915_READ(CURCNTR(pipe)) & MCURSOR_MODE) {
struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
@@ -13665,10 +13665,11 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ verify_wm_state(crtc, new_crtc_state);
+
if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
return;
- verify_wm_state(crtc, new_crtc_state);
verify_connector_state(state, crtc);
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 60+ messages in thread
* ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach.
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (23 preceding siblings ...)
2019-10-04 11:35 ` [PATCH 24/24] semi-hax: drm/i915: Always verify ddb allocation Maarten Lankhorst
@ 2019-10-04 13:10 ` Patchwork
2019-10-04 18:03 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev2) Patchwork
2019-10-10 16:25 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev3) Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2019-10-04 13:10 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Enable bigjoiner support, second approach.
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/display/intel_display.o
drivers/gpu/drm/i915/display/intel_display.c: In function ‘verify_wm_state’:
drivers/gpu/drm/i915/display/intel_display.c:13372:20: error: invalid operands to binary & (have ‘i915_reg_t {aka const struct <anonymous>}’ and ‘int’)
if (CURCNTR(pipe) & MCURSOR_MODE) {
^
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/display/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_display.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1670: recipe for target 'drivers' failed
make: *** [drivers] Error 2
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^ permalink raw reply [flat|nested] 60+ messages in thread* ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev2)
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (24 preceding siblings ...)
2019-10-04 13:10 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach Patchwork
@ 2019-10-04 18:03 ` Patchwork
2019-10-10 16:25 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev3) Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2019-10-04 18:03 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Enable bigjoiner support, second approach. (rev2)
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
Applying: HAX to make DSC work on the icelake test system
Applying: drm/i915: Fix for_each_intel_plane_mask definition
Applying: drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state.
Applying: drm/i915: Remove cursor use of properties for coordinates
Applying: drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0005 drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread* ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev3)
2019-10-04 11:34 [PATCH 00/24] Enable bigjoiner support, second approach Maarten Lankhorst
` (25 preceding siblings ...)
2019-10-04 18:03 ` ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev2) Patchwork
@ 2019-10-10 16:25 ` Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2019-10-10 16:25 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Enable bigjoiner support, second approach. (rev3)
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
Applying: HAX to make DSC work on the icelake test system
Applying: drm/i915: Fix for_each_intel_plane_mask definition
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.h
No changes -- Patch already applied.
Applying: drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.h
M drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_pm.c
No changes -- Patch already applied.
Applying: drm/i915: Remove cursor use of properties for coordinates
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
M drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
No changes -- Patch already applied.
Applying: drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0005 drm/i915: Use intel_plane_state in prepare and cleanup plane_fb
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 60+ messages in thread