[PATCH 1/3] drm/i915: Add microcontrollers documentation section

[PATCH 1/3] drm/i915: Add microcontrollers documentation section

[Daniele Ceraolo Spurio]

To better organize the information, add a microcontrollers section and
move/link the GuC, HuC and DMC documentation under it. Also add a small
intro.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 Documentation/gpu/i915.rst | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 465779670fd4..f1bae7867045 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -415,6 +415,15 @@ Object Tiling IOCTLs
 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
    :doc: buffer object tiling
 
+Microcontrollers
+================
+
+Starting from gen9, three microcontrollers are available on the HW: the
+graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the
+display microcontroller (DMC). The driver is responsible for loading the
+firmwares on the microcontrollers; the GuC and HuC firmwares are transferred
+to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
+
 WOPCM
 -----
 
@@ -454,6 +463,15 @@ GuC Address Space
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
    :doc: GuC Address Space
 
+HuC
+---
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+   :doc: HuC Firmware
+
+DMC
+---
+See `CSR firmware support for DMC`_
+
 Tracing
 =======
 
-- 
2.23.0

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[PATCH 2/3] drm/i915/guc: improve documentation

[Daniele Ceraolo Spurio]

Add a short description of what we expect from GuC and some minor
improvements to existing documentation. Also remove a comment about a
difference between GuC and HuC that is not true anymore.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 Documentation/gpu/i915.rst                    | 22 ++++++++++------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 26 +++++++++++++++++--
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 +++++
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h  |  3 ---
 4 files changed, 44 insertions(+), 13 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index f1bae7867045..357e9dfa7de1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -436,12 +436,24 @@ WOPCM Layout
 GuC
 ---
 
-Firmware Layout
-~~~~~~~~~~~~~~~
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+   :doc: GuC
+
+GuC Firmware Layout
+~~~~~~~~~~~~~~~~~~~
 
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
    :doc: Firmware Layout
 
+GuC Memory Management
+~~~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+   :doc: GuC Memory Management
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
+   :functions: intel_guc_allocate_vma
+
+
 GuC-specific firmware loader
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -457,12 +469,6 @@ GuC-based command submission
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
    :internal:
 
-GuC Address Space
-~~~~~~~~~~~~~~~~~
-
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
-   :doc: GuC Address Space
-
 HuC
 ---
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 249c747e9756..c6f018099fd0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -9,6 +9,22 @@
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
 
+/**
+ * DOC: GuC
+ *
+ * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
+ * designed to offload some of the functionality usually run on the host driver;
+ * currently the main operations it can take care of are:
+ *
+ * - Authentication of the HuC, which is required to fully enable HuC usage.
+ * - Low latency graphics context scheduling (a.k.a. GuC submission).
+ * - GT Power management.
+ *
+ * The enable_guc module parameter can be used to select which of those
+ * operations to enable within GuC. Note that not all the operations are
+ * supported on all gen9+ platforms.
+ */
+
 static void gen8_guc_raise_irq(struct intel_guc *guc)
 {
 	struct intel_gt *gt = guc_to_gt(guc);
@@ -548,9 +564,15 @@ int intel_guc_resume(struct intel_guc *guc)
 }
 
 /**
- * DOC: GuC Address Space
+ * DOC: GuC Memory Management
  *
- * The layout of GuC address space is shown below:
+ * GuC can't allocate any memory for its own usage, so all the allocations must
+ * be handled by the host driver. GuC accesses the memory via the GGTT, with the
+ * exception of the top and bottom parts of the 4GB address space, which are
+ * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
+ * or other parts of the HW. The driver must take care not to place objects that
+ * the GuC is going to access in these reserved ranges. The layout of the GuC
+ * address space is shown below:
  *
  * ::
  *
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..849a44add424 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -29,6 +29,12 @@ enum {
 /**
  * DOC: GuC-based command submission
  *
+ * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
+ * firmware is moving to an updated submission interface and we plan to
+ * turn submission back on when that lands. The below documentation (and related
+ * code) matches the old submission model and will be updated as part of the
+ * upgrade to the new flow.
+ *
  * GuC client:
  * A intel_guc_client refers to a submission path through GuC. Currently, there
  * is only one client, which is charged with all submissions to the GuC. This
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
index f8f6c91a0df6..029214cdedd5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
@@ -39,9 +39,6 @@
  * 3. Length info of each component can be found in header, in dwords.
  * 4. Modulus and exponent key are not required by driver. They may not appear
  *    in fw. So driver will load a truncated firmware in this case.
- *
- * The only difference between GuC and HuC firmwares is how the version
- * information is saved.
  */
 
 struct uc_css_header {
-- 
2.23.0

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Re: [PATCH 2/3] drm/i915/guc: improve documentation

[akaras]

Hello Daniele, 

On Fri, Sep 27, 2019 at 02:42:42PM -0700, Daniele Ceraolo Spurio wrote:
> Add a short description of what we expect from GuC and some minor
> improvements to existing documentation. Also remove a comment about a
> difference between GuC and HuC that is not true anymore.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Acked-by: Anna Karas <anna.karas@intel.com>

Anna Karas
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Re: [PATCH 2/3] drm/i915/guc: improve documentation

[Martin Peres]

On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
> Add a short description of what we expect from GuC and some minor
> improvements to existing documentation. Also remove a comment about a
> difference between GuC and HuC that is not true anymore.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
>  Documentation/gpu/i915.rst                    | 22 ++++++++++------
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 26 +++++++++++++++++--
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 +++++
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h  |  3 ---
>  4 files changed, 44 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index f1bae7867045..357e9dfa7de1 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -436,12 +436,24 @@ WOPCM Layout
>  GuC
>  ---
>  
> -Firmware Layout
> -~~~~~~~~~~~~~~~
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +   :doc: GuC
> +
> +GuC Firmware Layout
> +~~~~~~~~~~~~~~~~~~~
>  
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
>     :doc: Firmware Layout
>  
> +GuC Memory Management
> +~~~~~~~~~~~~~~~~~~~~~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +   :doc: GuC Memory Management
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +   :functions: intel_guc_allocate_vma
> +
> +
>  GuC-specific firmware loader
>  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>  
> @@ -457,12 +469,6 @@ GuC-based command submission
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>     :internal:
>  
> -GuC Address Space
> -~~~~~~~~~~~~~~~~~
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> -   :doc: GuC Address Space
> -
>  HuC
>  ---
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 249c747e9756..c6f018099fd0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -9,6 +9,22 @@
>  #include "intel_guc_submission.h"
>  #include "i915_drv.h"
>  
> +/**
> + * DOC: GuC
> + *
> + * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
> + * designed to offload some of the functionality usually run on the host driver;

"... functionality usually run on the host driver" -> "... functionality
usually performed by the host driver"?

> + * currently the main operations it can take care of are:
> + *
> + * - Authentication of the HuC, which is required to fully enable HuC usage.
> + * - Low latency graphics context scheduling (a.k.a. GuC submission).
> + * - GT Power management.
> + *
> + * The enable_guc module parameter can be used to select which of those
> + * operations to enable within GuC. Note that not all the operations are
> + * supported on all gen9+ platforms.

It would be good to say that the FW is optional and that we support
running without it. Also, it would be good to explain what is lost when
not using this FW (for now, only losing the ability to use the HuC).

> + */
> +
>  static void gen8_guc_raise_irq(struct intel_guc *guc)
>  {
>  	struct intel_gt *gt = guc_to_gt(guc);
> @@ -548,9 +564,15 @@ int intel_guc_resume(struct intel_guc *guc)
>  }
>  
>  /**
> - * DOC: GuC Address Space
> + * DOC: GuC Memory Management
>   *
> - * The layout of GuC address space is shown below:
> + * GuC can't allocate any memory for its own usage, so all the allocations must
> + * be handled by the host driver. GuC accesses the memory via the GGTT, with the
> + * exception of the top and bottom parts of the 4GB address space, which are
> + * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
> + * or other parts of the HW. The driver must take care not to place objects that
> + * the GuC is going to access in these reserved ranges. The layout of the GuC
> + * address space is shown below:

Thanks for writing this! This is really beneficial!

>   *
>   * ::
>   *
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index f325d3dd564f..849a44add424 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -29,6 +29,12 @@ enum {
>  /**
>   * DOC: GuC-based command submission
>   *
> + * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
> + * firmware is moving to an updated submission interface and we plan to
> + * turn submission back on when that lands. The below documentation (and related
> + * code) matches the old submission model and will be updated as part of the
> + * upgrade to the new flow.

Thanks for adding this :)

> + *
>   * GuC client:
>   * A intel_guc_client refers to a submission path through GuC. Currently, there
>   * is only one client, which is charged with all submissions to the GuC. This
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
> index f8f6c91a0df6..029214cdedd5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
> @@ -39,9 +39,6 @@
>   * 3. Length info of each component can be found in header, in dwords.
>   * 4. Modulus and exponent key are not required by driver. They may not appear
>   *    in fw. So driver will load a truncated firmware in this case.
> - *
> - * The only difference between GuC and HuC firmwares is how the version
> - * information is saved.
>   */
>  
>  struct uc_css_header {
> 
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[PATCH 3/3] drm/i915/huc: improve documentation

[Daniele Ceraolo Spurio]

Better explain the usage of the microcontroller and what i915 is
responsible of. While at it, fix the documentation for the auth
function, which doesn't do any pinning anymore.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 Documentation/gpu/i915.rst                | 10 ++++++++--
 drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 19 +++++++++++++++----
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---------------
 3 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 357e9dfa7de1..bfb64337db66 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,8 +471,14 @@ GuC-based command submission
 
 HuC
 ---
-.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
-   :doc: HuC Firmware
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+   :doc: HuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
+   :functions: intel_huc_auth
+
+HuC Firmware Layout
+~~~~~~~~~~~~~~~~~~~
+The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
 
 DMC
 ---
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index d4625c97b4f9..6e10fe898c90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -9,6 +9,18 @@
 #include "intel_huc.h"
 #include "i915_drv.h"
 
+/**
+ * DOC: HuC
+ *
+ * The HuC is a dedicated microcontroller for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can directly use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ * The kernel driver is only responsible for loading the HuC firmware and
+ * triggering its security authentication, which is performed by the GuC. For
+ * The GuC to correctly perform the authentication, the HuC binary must be
+ * loaded before the GuC one.
+ */
+
 void intel_huc_init_early(struct intel_huc *huc)
 {
 	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
@@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
  *
  * Called after HuC and GuC firmware loading during intel_uc_init_hw().
  *
- * This function pins HuC firmware image object into GGTT.
- * Then it invokes GuC action to authenticate passing the offset to RSA
- * signature through intel_guc_auth_huc(). It then waits for 50ms for
- * firmware verification ACK and unpins the object.
+ * This function invokes the GuC action to authenticate the HuC firmware,
+ * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
+ * waits for up to 50ms for firmware verification ACK.
  */
 int intel_huc_auth(struct intel_huc *huc)
 {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 74602487ed67..d654340d4d03 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,21 +7,6 @@
 #include "intel_huc_fw.h"
 #include "i915_drv.h"
 
-/**
- * DOC: HuC Firmware
- *
- * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
- *
- * Implementation:
- * The same firmware loader is used as the GuC. However, the actual
- * loading to HW is deferred until GEM initialization is done.
- *
- * Note that HuC firmware loading must be done before GuC loading.
- */
-
 /**
  * intel_huc_fw_init_early() - initializes HuC firmware struct
  * @huc: intel_huc struct
-- 
2.23.0

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Re: [PATCH 3/3] drm/i915/huc: improve documentation

[Anna Karas]

Hello Daniele,

On Fri, Sep 27, 2019 at 02:42:43PM -0700, Daniele Ceraolo Spurio wrote:
> Better explain the usage of the microcontroller and what i915 is
> responsible of. While at it, fix the documentation for the auth
> function, which doesn't do any pinning anymore.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

Acked-by: Anna Karas <anna.karas@intel.com>

Anna Karas
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Re: [PATCH 3/3] drm/i915/huc: improve documentation

[Martin Peres]

On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
> Better explain the usage of the microcontroller and what i915 is
> responsible of. While at it, fix the documentation for the auth
> function, which doesn't do any pinning anymore.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  Documentation/gpu/i915.rst                | 10 ++++++++--
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 19 +++++++++++++++----
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---------------
>  3 files changed, 23 insertions(+), 21 deletions(-)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 357e9dfa7de1..bfb64337db66 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -471,8 +471,14 @@ GuC-based command submission
>  
>  HuC
>  ---
> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> -   :doc: HuC Firmware
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +   :doc: HuC
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +   :functions: intel_huc_auth
> +
> +HuC Firmware Layout
> +~~~~~~~~~~~~~~~~~~~
> +The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
>  
>  DMC
>  ---
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index d4625c97b4f9..6e10fe898c90 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -9,6 +9,18 @@
>  #include "intel_huc.h"
>  #include "i915_drv.h"
>  
> +/**
> + * DOC: HuC
> + *
> + * The HuC is a dedicated microcontroller for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can directly use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + * The kernel driver is only responsible for loading the HuC firmware and
> + * triggering its security authentication, which is performed by the GuC. For
> + * The GuC to correctly perform the authentication, the HuC binary must be
> + * loaded before the GuC one.
> + */
> +
>  void intel_huc_init_early(struct intel_huc *huc)
>  {
>  	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> @@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
>   *
>   * Called after HuC and GuC firmware loading during intel_uc_init_hw().
>   *
> - * This function pins HuC firmware image object into GGTT.
> - * Then it invokes GuC action to authenticate passing the offset to RSA
> - * signature through intel_guc_auth_huc(). It then waits for 50ms for
> - * firmware verification ACK and unpins the object.
> + * This function invokes the GuC action to authenticate the HuC firmware,
> + * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
> + * waits for up to 50ms for firmware verification ACK.
>   */
>  int intel_huc_auth(struct intel_huc *huc)
>  {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index 74602487ed67..d654340d4d03 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -7,21 +7,6 @@
>  #include "intel_huc_fw.h"
>  #include "i915_drv.h"
>  
> -/**
> - * DOC: HuC Firmware
> - *
> - * Motivation:
> - * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> - * Efficiency Video Coding) operations. Userspace can use the firmware
> - * capabilities by adding HuC specific commands to batch buffers.

Having a link to the media driver here that would explain what the HuC
enables would be beneficial (we don't want to maintain that).

> - *
> - * Implementation:
> - * The same firmware loader is used as the GuC. However, the actual
> - * loading to HW is deferred until GEM initialization is done.
> - *
> - * Note that HuC firmware loading must be done before GuC loading.
> - */

Could we add a section explaining the access the HuC has to memory, and
one stating that the firmware is optional?

Anyways, thanks! The series could be landed as-is already, but a few
more additions would be welcomed :)

Martin

> -
>  /**
>   * intel_huc_fw_init_early() - initializes HuC firmware struct
>   * @huc: intel_huc struct
> 
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Re: [PATCH 3/3] drm/i915/huc: improve documentation

[Daniele Ceraolo Spurio]

On 10/9/19 7:41 AM, Martin Peres wrote:
> On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
>> Better explain the usage of the microcontroller and what i915 is
>> responsible of. While at it, fix the documentation for the auth
>> function, which doesn't do any pinning anymore.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> ---
>>   Documentation/gpu/i915.rst                | 10 ++++++++--
>>   drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 19 +++++++++++++++----
>>   drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---------------
>>   3 files changed, 23 insertions(+), 21 deletions(-)
>>
>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>> index 357e9dfa7de1..bfb64337db66 100644
>> --- a/Documentation/gpu/i915.rst
>> +++ b/Documentation/gpu/i915.rst
>> @@ -471,8 +471,14 @@ GuC-based command submission
>>   
>>   HuC
>>   ---
>> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> -   :doc: HuC Firmware
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> +   :doc: HuC
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> +   :functions: intel_huc_auth
>> +
>> +HuC Firmware Layout
>> +~~~~~~~~~~~~~~~~~~~
>> +The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
>>   
>>   DMC
>>   ---
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> index d4625c97b4f9..6e10fe898c90 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> @@ -9,6 +9,18 @@
>>   #include "intel_huc.h"
>>   #include "i915_drv.h"
>>   
>> +/**
>> + * DOC: HuC
>> + *
>> + * The HuC is a dedicated microcontroller for usage in media HEVC (High
>> + * Efficiency Video Coding) operations. Userspace can directly use the firmware
>> + * capabilities by adding HuC specific commands to batch buffers.
>> + * The kernel driver is only responsible for loading the HuC firmware and
>> + * triggering its security authentication, which is performed by the GuC. For
>> + * The GuC to correctly perform the authentication, the HuC binary must be
>> + * loaded before the GuC one.
>> + */
>> +
>>   void intel_huc_init_early(struct intel_huc *huc)
>>   {
>>   	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
>> @@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
>>    *
>>    * Called after HuC and GuC firmware loading during intel_uc_init_hw().
>>    *
>> - * This function pins HuC firmware image object into GGTT.
>> - * Then it invokes GuC action to authenticate passing the offset to RSA
>> - * signature through intel_guc_auth_huc(). It then waits for 50ms for
>> - * firmware verification ACK and unpins the object.
>> + * This function invokes the GuC action to authenticate the HuC firmware,
>> + * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
>> + * waits for up to 50ms for firmware verification ACK.
>>    */
>>   int intel_huc_auth(struct intel_huc *huc)
>>   {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> index 74602487ed67..d654340d4d03 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> @@ -7,21 +7,6 @@
>>   #include "intel_huc_fw.h"
>>   #include "i915_drv.h"
>>   
>> -/**
>> - * DOC: HuC Firmware
>> - *
>> - * Motivation:
>> - * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
>> - * Efficiency Video Coding) operations. Userspace can use the firmware
>> - * capabilities by adding HuC specific commands to batch buffers.
> 
> Having a link to the media driver here that would explain what the HuC
> enables would be beneficial (we don't want to maintain that).
> 
>> - *
>> - * Implementation:
>> - * The same firmware loader is used as the GuC. However, the actual
>> - * loading to HW is deferred until GEM initialization is done.
>> - *
>> - * Note that HuC firmware loading must be done before GuC loading.
>> - */
> 
> Could we add a section explaining the access the HuC has to memory, and

I'll have to follow up with the HuC team to understand how the memory 
access works because I'm not too familiar with HuC. Are you ok if I 
address all your other comments for GuC and HuC and add this as a follow 
up later once I get the info?

Daniele

> one stating that the firmware is optional?
> 
> Anyways, thanks! The series could be landed as-is already, but a few
> more additions would be welcomed :)
> 
> Martin
> 
>> -
>>   /**
>>    * intel_huc_fw_init_early() - initializes HuC firmware struct
>>    * @huc: intel_huc struct
>>
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Re: [PATCH 3/3] drm/i915/huc: improve documentation

[Daniele Ceraolo Spurio]

On 10/9/19 2:44 PM, Daniele Ceraolo Spurio wrote:
> 
> 
> On 10/9/19 7:41 AM, Martin Peres wrote:
>> On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
>>> Better explain the usage of the microcontroller and what i915 is
>>> responsible of. While at it, fix the documentation for the auth
>>> function, which doesn't do any pinning anymore.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>> ---
>>>   Documentation/gpu/i915.rst                | 10 ++++++++--
>>>   drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 19 +++++++++++++++----
>>>   drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---------------
>>>   3 files changed, 23 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>>> index 357e9dfa7de1..bfb64337db66 100644
>>> --- a/Documentation/gpu/i915.rst
>>> +++ b/Documentation/gpu/i915.rst
>>> @@ -471,8 +471,14 @@ GuC-based command submission
>>>   HuC
>>>   ---
>>> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>>> -   :doc: HuC Firmware
>>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
>>> +   :doc: HuC
>>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
>>> +   :functions: intel_huc_auth
>>> +
>>> +HuC Firmware Layout
>>> +~~~~~~~~~~~~~~~~~~~
>>> +The HuC FW layout is the same as the GuC one, see `GuC Firmware 
>>> Layout`_
>>>   DMC
>>>   ---
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
>>> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>>> index d4625c97b4f9..6e10fe898c90 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>>> @@ -9,6 +9,18 @@
>>>   #include "intel_huc.h"
>>>   #include "i915_drv.h"
>>> +/**
>>> + * DOC: HuC
>>> + *
>>> + * The HuC is a dedicated microcontroller for usage in media HEVC (High
>>> + * Efficiency Video Coding) operations. Userspace can directly use 
>>> the firmware
>>> + * capabilities by adding HuC specific commands to batch buffers.
>>> + * The kernel driver is only responsible for loading the HuC 
>>> firmware and
>>> + * triggering its security authentication, which is performed by the 
>>> GuC. For
>>> + * The GuC to correctly perform the authentication, the HuC binary 
>>> must be
>>> + * loaded before the GuC one.
>>> + */
>>> +
>>>   void intel_huc_init_early(struct intel_huc *huc)
>>>   {
>>>       struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
>>> @@ -118,10 +130,9 @@ void intel_huc_fini(struct intel_huc *huc)
>>>    *
>>>    * Called after HuC and GuC firmware loading during 
>>> intel_uc_init_hw().
>>>    *
>>> - * This function pins HuC firmware image object into GGTT.
>>> - * Then it invokes GuC action to authenticate passing the offset to RSA
>>> - * signature through intel_guc_auth_huc(). It then waits for 50ms for
>>> - * firmware verification ACK and unpins the object.
>>> + * This function invokes the GuC action to authenticate the HuC 
>>> firmware,
>>> + * passing the offset of the RSA signature to intel_guc_auth_huc(). 
>>> It then
>>> + * waits for up to 50ms for firmware verification ACK.
>>>    */
>>>   int intel_huc_auth(struct intel_huc *huc)
>>>   {
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
>>> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>>> index 74602487ed67..d654340d4d03 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>>> @@ -7,21 +7,6 @@
>>>   #include "intel_huc_fw.h"
>>>   #include "i915_drv.h"
>>> -/**
>>> - * DOC: HuC Firmware
>>> - *
>>> - * Motivation:
>>> - * GEN9 introduces a new dedicated firmware for usage in media HEVC 
>>> (High
>>> - * Efficiency Video Coding) operations. Userspace can use the firmware
>>> - * capabilities by adding HuC specific commands to batch buffers.
>>
>> Having a link to the media driver here that would explain what the HuC
>> enables would be beneficial (we don't want to maintain that).
>>
>>> - *
>>> - * Implementation:
>>> - * The same firmware loader is used as the GuC. However, the actual
>>> - * loading to HW is deferred until GEM initialization is done.
>>> - *
>>> - * Note that HuC firmware loading must be done before GuC loading.
>>> - */
>>
>> Could we add a section explaining the access the HuC has to memory, and
> 
> I'll have to follow up with the HuC team to understand how the memory 
> access works because I'm not too familiar with HuC. Are you ok if I 
> address all your other comments for GuC and HuC and add this as a follow 
> up later once I get the info?
> 

Never mind, I found the info  I needed (Bspec 48058), so I can do all 
the changes in one go.

Daniele

> Daniele
> 
>> one stating that the firmware is optional?
>>
>> Anyways, thanks! The series could be landed as-is already, but a few
>> more additions would be welcomed :)
>>
>> Martin
>>
>>> -
>>>   /**
>>>    * intel_huc_fw_init_early() - initializes HuC firmware struct
>>>    * @huc: intel_huc struct
>>>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add microcontrollers documentation section

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Add microcontrollers documentation section
URL   : https://patchwork.freedesktop.org/series/67356/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14575
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14575 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14575, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14575:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_gem_contexts:
    - fi-kbl-r:           [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_14575 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] / [fdo#111381])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-blb-e6850/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-blb-e6850/igt@i915_module_load@reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [PASS][7] -> [FAIL][8] ([fdo#109635 ] / [fdo#110387])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][9] -> [FAIL][10] ([fdo#111045] / [fdo#111096])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-icl-u3:          [PASS][11] -> [DMESG-WARN][12] ([fdo#107724]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_mmap@basic-small-bo:
    - fi-icl-u3:          [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6973/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/fi-icl-u3/igt@gem_mmap@basic-small-bo.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6973 -> Patchwork_14575

  CI-20190529: 20190529
  CI_DRM_6973: 7462c58bba0fb6e85bd380591c3fd86e298c0f95 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5206: 5a6c68568def840cd720f18fc66f529a89f84675 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14575: 61eab783ca84603326cd35cda16c3f4fcb9365ff @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

61eab783ca84 drm/i915/huc: improve documentation
1b0401f1da97 drm/i915/guc: improve documentation
46bf0b6b061f drm/i915: Add microcontrollers documentation section

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14575/index.html
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Re: [PATCH 1/3] drm/i915: Add microcontrollers documentation section

[root]

Hello Daniele,

On Fri, Sep 27, 2019 at 02:42:41PM -0700, Daniele Ceraolo Spurio wrote:
> To better organize the information, add a microcontrollers section and
> move/link the GuC, HuC and DMC documentation under it. Also add a small
> intro.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

Acked-by: Anna Karas <anna.karas@intel.com>

Anna Karas
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Re: [PATCH 1/3] drm/i915: Add microcontrollers documentation section

[Martin Peres]

On 28/09/2019 00:42, Daniele Ceraolo Spurio wrote:
> To better organize the information, add a microcontrollers section and
> move/link the GuC, HuC and DMC documentation under it. Also add a small
> intro.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Martin Peres <martin.peres@linux.intel.com>

> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  Documentation/gpu/i915.rst | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 465779670fd4..f1bae7867045 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -415,6 +415,15 @@ Object Tiling IOCTLs
>  .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
>     :doc: buffer object tiling
>  
> +Microcontrollers
> +================
> +
> +Starting from gen9, three microcontrollers are available on the HW: the
> +graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the
> +display microcontroller (DMC). The driver is responsible for loading the
> +firmwares on the microcontrollers; the GuC and HuC firmwares are transferred
> +to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
> +
>  WOPCM
>  -----
>  
> @@ -454,6 +463,15 @@ GuC Address Space
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
>     :doc: GuC Address Space
>  
> +HuC
> +---
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +   :doc: HuC Firmware
> +
> +DMC
> +---
> +See `CSR firmware support for DMC`_
> +
>  Tracing
>  =======
>  
> 
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