Re: [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT

Souza, Jose
2019-10-10T20:45:42Z

I messed up on this patch, please ignore this one.
Will send the fixed version soon.

On Thu, 2019-10-10 at 12:32 -0700, José Roberto de Souza wrote:
> On GLK those registers are reserved and on another gens it have
> another meaning, so renaming it to BXT only.
>
> BSpec: 7548
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++-------
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> 2 files changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 43564295b864..a1787d165467 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2384,8 +2384,8 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = 652800;
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> - } else if (IS_GEN9_BC(dev_priv)) {
> - u32 limit = I915_READ(SKL_DFSM) &
> SKL_DFSM_CDCLK_LIMIT_MASK;
> + } else if (IS_BROXTON(dev_priv)) {
> + u32 limit = I915_READ(SKL_DFSM) &
> BXT_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> vco = dev_priv->skl_preferred_vco_freq;
> @@ -2396,11 +2396,11 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> * first guess. skl_calc_cdclk() will correct it
> * if the preferred vco is 8100 instead.
> */
> - if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> + if (limit == BXT_DFSM_CDCLK_LIMIT_675)
> max_cdclk = 617143;
> - else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
> + else if (limit == BXT_DFSM_CDCLK_LIMIT_540)
> max_cdclk = 540000;
> - else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
> + else if (limit == BXT_DFSM_CDCLK_LIMIT_450)
> max_cdclk = 432000;
> else
> max_cdclk = 308571;
> @@ -2408,8 +2408,6 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk,
> vco);
> } else if (IS_GEMINILAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 316800;
> - } else if (IS_BROXTON(dev_priv)) {
> - dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> * FIXME with extra cooling we can allow
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index b383511b6231..39c65f051468 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7644,11 +7644,11 @@ enum {
>
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_450 (2 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)