* [PATCH 2/4] drm/i915/display: Handle fused off HDCP
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
@ 2019-10-10 19:32 ` José Roberto de Souza
2019-10-11 12:27 ` Ville Syrjälä
2019-10-10 19:32 ` [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT José Roberto de Souza
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: José Roberto de Souza @ 2019-10-10 19:32 UTC (permalink / raw)
To: intel-gfx
HDCP could be fused off, so not all GEN9+ platforms will support it.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e69fa34528df..f1f41ca8402b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{
/* PORT E doesn't have HDCP, and PORT F is disabled */
- return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
+ return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
}
static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1cbf3998b361..cf956deb0bdf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -600,6 +600,7 @@ static const struct intel_device_info intel_cherryview_info = {
.has_logical_ring_preemption = 1, \
.display.has_csr = 1, \
.has_gt_uc = 1, \
+ .display.has_hdcp = 1, \
.display.has_ipc = 1, \
.ddb_size = 896
@@ -643,6 +644,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.display.has_ddi = 1, \
.has_fpga_dbg = 1, \
.display.has_fbc = 1, \
+ .display.has_hdcp = 1, \
.display.has_psr = 1, \
.has_runtime_pm = 1, \
.display.has_csr = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fb9030b89f1..b383511b6231 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7643,6 +7643,7 @@ enum {
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
#define SKL_DFSM _MMIO(0x51000)
+#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c01fccfe3cca..5cfa197090e2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -980,6 +980,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
enabled_mask);
info->pipe_mask = enabled_mask;
+
+ if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
+ info->display.has_hdcp = 0;
}
/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0cdc2465534b..94165b18ed9b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -138,6 +138,7 @@ enum intel_ppgtt_type {
func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
+ func(has_hdcp); \
func(has_hotplug); \
func(has_ipc); \
func(has_modular_fia); \
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] drm/i915/display: Handle fused off HDCP
2019-10-10 19:32 ` [PATCH 2/4] drm/i915/display: Handle fused off HDCP José Roberto de Souza
@ 2019-10-11 12:27 ` Ville Syrjälä
0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2019-10-11 12:27 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Oct 10, 2019 at 12:32:39PM -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 5 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
> bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
> {
> /* PORT E doesn't have HDCP, and PORT F is disabled */
> - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1cbf3998b361..cf956deb0bdf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -600,6 +600,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_logical_ring_preemption = 1, \
> .display.has_csr = 1, \
> .has_gt_uc = 1, \
> + .display.has_hdcp = 1, \
> .display.has_ipc = 1, \
> .ddb_size = 896
>
> @@ -643,6 +644,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> .display.has_fbc = 1, \
> + .display.has_hdcp = 1, \
> .display.has_psr = 1, \
> .has_runtime_pm = 1, \
> .display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0fb9030b89f1..b383511b6231 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7643,6 +7643,7 @@ enum {
> #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
Looks correct.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index c01fccfe3cca..5cfa197090e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -980,6 +980,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> enabled_mask);
>
> info->pipe_mask = enabled_mask;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> + info->display.has_hdcp = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 0cdc2465534b..94165b18ed9b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> func(has_dsb); \
> func(has_fbc); \
> func(has_gmch); \
> + func(has_hdcp); \
> func(has_hotplug); \
> func(has_ipc); \
> func(has_modular_fia); \
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
2019-10-10 19:32 ` [PATCH 2/4] drm/i915/display: Handle fused off HDCP José Roberto de Souza
@ 2019-10-10 19:32 ` José Roberto de Souza
2019-10-10 20:45 ` Souza, Jose
2019-10-10 19:32 ` [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off José Roberto de Souza
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: José Roberto de Souza @ 2019-10-10 19:32 UTC (permalink / raw)
To: intel-gfx
On GLK those registers are reserved and on another gens it have
another meaning, so renaming it to BXT only.
BSpec: 7548
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++-------
drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 43564295b864..a1787d165467 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2384,8 +2384,8 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->max_cdclk_freq = 652800;
} else if (IS_CANNONLAKE(dev_priv)) {
dev_priv->max_cdclk_freq = 528000;
- } else if (IS_GEN9_BC(dev_priv)) {
- u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+ } else if (IS_BROXTON(dev_priv)) {
+ u32 limit = I915_READ(SKL_DFSM) & BXT_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
vco = dev_priv->skl_preferred_vco_freq;
@@ -2396,11 +2396,11 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* first guess. skl_calc_cdclk() will correct it
* if the preferred vco is 8100 instead.
*/
- if (limit == SKL_DFSM_CDCLK_LIMIT_675)
+ if (limit == BXT_DFSM_CDCLK_LIMIT_675)
max_cdclk = 617143;
- else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
+ else if (limit == BXT_DFSM_CDCLK_LIMIT_540)
max_cdclk = 540000;
- else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
+ else if (limit == BXT_DFSM_CDCLK_LIMIT_450)
max_cdclk = 432000;
else
max_cdclk = 308571;
@@ -2408,8 +2408,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_GEMINILAKE(dev_priv)) {
dev_priv->max_cdclk_freq = 316800;
- } else if (IS_BROXTON(dev_priv)) {
- dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b383511b6231..39c65f051468 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7644,11 +7644,11 @@ enum {
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
-#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
+#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
+#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
+#define BXT_DFSM_CDCLK_LIMIT_450 (2 << 23)
+#define BXT_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT
2019-10-10 19:32 ` [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT José Roberto de Souza
@ 2019-10-10 20:45 ` Souza, Jose
2019-10-11 12:31 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Souza, Jose @ 2019-10-10 20:45 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org
I messed up on this patch, please ignore this one.
Will send the fixed version soon.
On Thu, 2019-10-10 at 12:32 -0700, José Roberto de Souza wrote:
> On GLK those registers are reserved and on another gens it have
> another meaning, so renaming it to BXT only.
>
> BSpec: 7548
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++-------
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> 2 files changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 43564295b864..a1787d165467 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2384,8 +2384,8 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = 652800;
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 528000;
> - } else if (IS_GEN9_BC(dev_priv)) {
> - u32 limit = I915_READ(SKL_DFSM) &
> SKL_DFSM_CDCLK_LIMIT_MASK;
> + } else if (IS_BROXTON(dev_priv)) {
> + u32 limit = I915_READ(SKL_DFSM) &
> BXT_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> vco = dev_priv->skl_preferred_vco_freq;
> @@ -2396,11 +2396,11 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> * first guess. skl_calc_cdclk() will correct it
> * if the preferred vco is 8100 instead.
> */
> - if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> + if (limit == BXT_DFSM_CDCLK_LIMIT_675)
> max_cdclk = 617143;
> - else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
> + else if (limit == BXT_DFSM_CDCLK_LIMIT_540)
> max_cdclk = 540000;
> - else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
> + else if (limit == BXT_DFSM_CDCLK_LIMIT_450)
> max_cdclk = 432000;
> else
> max_cdclk = 308571;
> @@ -2408,8 +2408,6 @@ void intel_update_max_cdclk(struct
> drm_i915_private *dev_priv)
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk,
> vco);
> } else if (IS_GEMINILAKE(dev_priv)) {
> dev_priv->max_cdclk_freq = 316800;
> - } else if (IS_BROXTON(dev_priv)) {
> - dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> * FIXME with extra cooling we can allow
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index b383511b6231..39c65f051468 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7644,11 +7644,11 @@ enum {
>
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_450 (2 << 23)
> +#define BXT_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT
2019-10-10 20:45 ` Souza, Jose
@ 2019-10-11 12:31 ` Ville Syrjälä
0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2019-10-11 12:31 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx@lists.freedesktop.org
On Thu, Oct 10, 2019 at 08:45:42PM +0000, Souza, Jose wrote:
> I messed up on this patch, please ignore this one.
> Will send the fixed version soon.
The whole thing is wrong according to the spec:
"This field is unused on BXT. Any CD clock frequency limitation must be
done in software."
>
> On Thu, 2019-10-10 at 12:32 -0700, José Roberto de Souza wrote:
> > On GLK those registers are reserved and on another gens it have
> > another meaning, so renaming it to BXT only.
> >
> > BSpec: 7548
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++-------
> > drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> > 2 files changed, 10 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 43564295b864..a1787d165467 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2384,8 +2384,8 @@ void intel_update_max_cdclk(struct
> > drm_i915_private *dev_priv)
> > dev_priv->max_cdclk_freq = 652800;
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > dev_priv->max_cdclk_freq = 528000;
> > - } else if (IS_GEN9_BC(dev_priv)) {
> > - u32 limit = I915_READ(SKL_DFSM) &
> > SKL_DFSM_CDCLK_LIMIT_MASK;
> > + } else if (IS_BROXTON(dev_priv)) {
> > + u32 limit = I915_READ(SKL_DFSM) &
> > BXT_DFSM_CDCLK_LIMIT_MASK;
> > int max_cdclk, vco;
> >
> > vco = dev_priv->skl_preferred_vco_freq;
> > @@ -2396,11 +2396,11 @@ void intel_update_max_cdclk(struct
> > drm_i915_private *dev_priv)
> > * first guess. skl_calc_cdclk() will correct it
> > * if the preferred vco is 8100 instead.
> > */
> > - if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> > + if (limit == BXT_DFSM_CDCLK_LIMIT_675)
> > max_cdclk = 617143;
> > - else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
> > + else if (limit == BXT_DFSM_CDCLK_LIMIT_540)
> > max_cdclk = 540000;
> > - else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
> > + else if (limit == BXT_DFSM_CDCLK_LIMIT_450)
> > max_cdclk = 432000;
> > else
> > max_cdclk = 308571;
> > @@ -2408,8 +2408,6 @@ void intel_update_max_cdclk(struct
> > drm_i915_private *dev_priv)
> > dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk,
> > vco);
> > } else if (IS_GEMINILAKE(dev_priv)) {
> > dev_priv->max_cdclk_freq = 316800;
> > - } else if (IS_BROXTON(dev_priv)) {
> > - dev_priv->max_cdclk_freq = 624000;
> > } else if (IS_BROADWELL(dev_priv)) {
> > /*
> > * FIXME with extra cooling we can allow
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index b383511b6231..39c65f051468 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7644,11 +7644,11 @@ enum {
> >
> > #define SKL_DFSM _MMIO(0x51000)
> > #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> > -#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> > -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> > -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > +#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> > +#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
> > +#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > +#define BXT_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > +#define BXT_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
2019-10-10 19:32 ` [PATCH 2/4] drm/i915/display: Handle fused off HDCP José Roberto de Souza
2019-10-10 19:32 ` [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT José Roberto de Souza
@ 2019-10-10 19:32 ` José Roberto de Souza
2019-10-11 12:29 ` Ville Syrjälä
2019-10-10 20:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly Patchwork
2019-10-11 12:25 ` [PATCH 1/4] " Ville Syrjälä
4 siblings, 1 reply; 13+ messages in thread
From: José Roberto de Souza @ 2019-10-10 19:32 UTC (permalink / raw)
To: intel-gfx
Those features could be fused off on GEN9 non-low power and newer
GENs.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39c65f051468..086a8e6e86f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7643,7 +7643,9 @@ enum {
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
#define SKL_DFSM _MMIO(0x51000)
+#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
+#define SKL_DFSM_DMC_DISABLE (1 << 23)
#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 5cfa197090e2..deeab3790a51 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -983,6 +983,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
info->display.has_hdcp = 0;
+
+ if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
+ info->display.has_fbc = 0;
+
+ if (!IS_GEN9_BC(dev_priv) && dfsm & SKL_DFSM_DMC_DISABLE)
+ info->display.has_csr = 0;
}
/* Initialize slice/subslice/EU info */
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off
2019-10-10 19:32 ` [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off José Roberto de Souza
@ 2019-10-11 12:29 ` Ville Syrjälä
0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2019-10-11 12:29 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Thu, Oct 10, 2019 at 12:32:41PM -0700, José Roberto de Souza wrote:
> Those features could be fused off on GEN9 non-low power and newer
> GENs.
Should probably be two patches.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39c65f051468..086a8e6e86f1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7643,7 +7643,9 @@ enum {
> #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
Looks correct.
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> +#define SKL_DFSM_DMC_DISABLE (1 << 23)
That seems to be a thing for icl+ only.
> #define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> #define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
> #define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 5cfa197090e2..deeab3790a51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -983,6 +983,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>
> if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> info->display.has_hdcp = 0;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> + info->display.has_fbc = 0;
> +
> + if (!IS_GEN9_BC(dev_priv) && dfsm & SKL_DFSM_DMC_DISABLE)
> + info->display.has_csr = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
` (2 preceding siblings ...)
2019-10-10 19:32 ` [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off José Roberto de Souza
@ 2019-10-10 20:18 ` Patchwork
2019-10-11 7:16 ` Martin Peres
2019-10-11 12:25 ` [PATCH 1/4] " Ville Syrjälä
4 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2019-10-10 20:18 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/display: Handle fused off display correctly
URL : https://patchwork.freedesktop.org/series/67872/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14757
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14757 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14757, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14757:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_hangcheck:
- fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-bxt-dsi/igt@runner@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-apl-guc/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_14757 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-copy:
- fi-glk-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-glk-dsi/igt@gem_mmap_gtt@basic-copy.html
* igt@prime_vgem@basic-read:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-icl-u3/igt@prime_vgem@basic-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-icl-u3/igt@prime_vgem@basic-read.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- {fi-icl-dsi}: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (54 -> 46)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7058 -> Patchwork_14757
CI-20190529: 20190529
CI_DRM_7058: ec85c0501ada08c2aea8adb7da74931a6d0ae39b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14757: f63b7c8bdcaf056403ca7455b1ed124e3ab390ac @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f63b7c8bdcaf drm/i915/display: Check if FBC and DMC are fused off
3424a77abcd0 drm/i915/display: DFSM CDCLK LIMIT is only available in BXT
ce9873d331e3 drm/i915/display: Handle fused off HDCP
da2924335660 drm/i915/display: Handle fused off display correctly
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly
2019-10-10 20:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly Patchwork
@ 2019-10-11 7:16 ` Martin Peres
2019-10-11 19:30 ` Souza, Jose
0 siblings, 1 reply; 13+ messages in thread
From: Martin Peres @ 2019-10-11 7:16 UTC (permalink / raw)
To: intel-gfx, Patchwork, José Roberto de Souza
On 10/10/2019 23:18, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/4] drm/i915/display: Handle fused off display correctly
> URL : https://patchwork.freedesktop.org/series/67872/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14757
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14757 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14757, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_14757:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live_hangcheck:
> - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
Do you think this is related to your patch series?
>
> * igt@runner@aborted:
> - fi-bxt-dsi: NOTRUN -> [FAIL][3]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-bxt-dsi/igt@runner@aborted.html
> - fi-apl-guc: NOTRUN -> [FAIL][4]
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-apl-guc/igt@runner@aborted.html
<7>[ 7.816334] [drm:intel_dump_cdclk_state [i915]] Current CDCLK
624000 kHz, VCO 1248000 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
level 25
<4>[ 7.816371] ------------[ cut here ]------------
<4>[ 7.816375] WARN_ON(vco != 8100000 && vco != 8640000)
<4>[ 7.816540] WARNING: CPU: 2 PID: 330 at
drivers/gpu/drm/i915/display/intel_cdclk.c:2392
intel_update_max_cdclk+0x27f/0x330 [i915]
<4>[ 7.816544] Modules linked in: i915(+) x86_pkg_temp_thermal
coretemp btusb btrtl crct10dif_pclmul btbcm crc32_pclmul btintel
snd_hda_intel snd_intel_nhlt bluetooth snd_hda_codec ghash_clmulni_intel
snd_hwdep snd_hda_core ecdh_generic ecc lpc_ich snd_pcm r8169 realtek
mei_me mei prime_numbers pinctrl_broxton pinctrl_intel
<4>[ 7.816575] CPU: 2 PID: 330 Comm: modprobe Tainted: G U
5.4.0-rc2-CI-Patchwork_14757+ #1
<4>[ 7.816579] Hardware name: Intel corporation NUC6CAYS/NUC6CAYB,
BIOS AYAPLCEL.86A.0056.2018.0926.1100 09/26/2018
<4>[ 7.816705] RIP: 0010:intel_update_max_cdclk+0x27f/0x330 [i915]
<4>[ 7.816710] Code: 4c 0a 00 e9 e0 fd ff ff 69 f0 b4 00 00 00 e9 59
ff ff ff 48 c7 c6 d0 9c 46 a0 48 c7 c7 c3 07 49 a0 89 44 24 04 e8 51 71
d4 e0 <0f> 0b 8b 44 24 04 e9 94 fe ff ff c7 87 e0 8f 00 00 80 d5 04 00 b8
<4>[ 7.816714] RSP: 0000:ffffc9000036b9c8 EFLAGS: 00010286
<4>[ 7.816718] RAX: 0000000000000000 RBX: ffff888258600000 RCX:
0000000000000002
<4>[ 7.816722] RDX: 0000000000000006 RSI: ffff8882614e56d0 RDI:
ffffffff8213bd09
<4>[ 7.816725] RBP: 0000000000000000 R08: ffff8882614e56d0 R09:
0000000000000000
<4>[ 7.816729] R10: 0000000000000000 R11: 0000000000000000 R12:
0000000000000003
<4>[ 7.816732] R13: 0000000000000002 R14: ffff888258600000 R15:
0000000000000000
<4>[ 7.816736] FS: 00007f016a3d6540(0000) GS:ffff888277b00000(0000)
knlGS:0000000000000000
<4>[ 7.816739] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4>[ 7.816743] CR2: 00007fc9f38265a0 CR3: 0000000262ea0000 CR4:
00000000003406e0
<4>[ 7.816746] Call Trace:
<4>[ 7.816863] intel_modeset_init+0xcfc/0x1be0 [i915]
<4>[ 7.816958] ? intel_irq_postinstall+0x1a6/0x5c0 [i915]
<4>[ 7.817051] i915_driver_probe+0xb68/0x15e0 [i915]
<4>[ 7.817065] ? find_held_lock+0x2d/0x90
<4>[ 7.817073] ? __pm_runtime_resume+0x4f/0x80
<4>[ 7.817172] i915_pci_probe+0x43/0x1b0 [i915]
<4>[ 7.817180] ? _raw_spin_unlock_irqrestore+0x39/0x60
<4>[ 7.817190] pci_device_probe+0x9e/0x120
<4>[ 7.817199] really_probe+0xea/0x420
<4>[ 7.817207] driver_probe_device+0x10b/0x120
<4>[ 7.817214] device_driver_attach+0x4a/0x50
<4>[ 7.817220] __driver_attach+0x97/0x130
<4>[ 7.817226] ? device_driver_attach+0x50/0x50
<4>[ 7.817231] bus_for_each_dev+0x74/0xc0
<4>[ 7.817239] bus_add_driver+0x142/0x220
<4>[ 7.817245] ? 0xffffffffa05a7000
<4>[ 7.817250] driver_register+0x56/0xf0
<4>[ 7.817255] ? 0xffffffffa05a7000
<4>[ 7.817260] do_one_initcall+0x58/0x2ff
<4>[ 7.817267] ? rcu_read_lock_sched_held+0x4d/0x80
<4>[ 7.817274] ? kmem_cache_alloc_trace+0x290/0x2c0
<4>[ 7.817284] do_init_module+0x56/0x1f8
<4>[ 7.817290] load_module+0x243e/0x29f0
<4>[ 7.817320] ? __do_sys_finit_module+0xe9/0x110
<4>[ 7.817324] __do_sys_finit_module+0xe9/0x110
<4>[ 7.817344] do_syscall_64+0x4f/0x210
<4>[ 7.817350] entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 7.817355] RIP: 0033:0x7f0169ef3839
<4>[ 7.817361] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40
00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08
0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
<4>[ 7.817364] RSP: 002b:00007ffcf9965528 EFLAGS: 00000246 ORIG_RAX:
0000000000000139
<4>[ 7.817369] RAX: ffffffffffffffda RBX: 000055c220e52f60 RCX:
00007f0169ef3839
<4>[ 7.817372] RDX: 0000000000000000 RSI: 000055c220e4bb30 RDI:
0000000000000000
<4>[ 7.817376] RBP: 000055c220e4bb30 R08: 0000000000000000 R09:
0000000000000000
<4>[ 7.817379] R10: 0000000000000000 R11: 0000000000000246 R12:
0000000000000000
<4>[ 7.817382] R13: 000055c220e53090 R14: 0000000000040000 R15:
0000000000000000
<4>[ 7.817399] irq event stamp: 398376
<4>[ 7.817405] hardirqs last enabled at (398375):
[<ffffffff8112a7fc>] vprintk_emit+0xcc/0x340
<4>[ 7.817409] hardirqs last disabled at (398376):
[<ffffffff81001bba>] trace_hardirqs_off_thunk+0x1a/0x20
<4>[ 7.817414] softirqs last enabled at (398360):
[<ffffffff81c00385>] __do_softirq+0x385/0x47f
<4>[ 7.817419] softirqs last disabled at (398353):
[<ffffffff810b7eaa>] irq_exit+0xba/0xc0
<4>[ 7.817422] ---[ end trace 43ed7a1d8633a989 ]---
Anyways, thanks for doing this work! That makes me think that maybe we
do not have good reporting capabilities for fused-off functionalities
which might confuse the userspace and developers looking at bug reports.
Martin
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly
2019-10-11 7:16 ` Martin Peres
@ 2019-10-11 19:30 ` Souza, Jose
0 siblings, 0 replies; 13+ messages in thread
From: Souza, Jose @ 2019-10-11 19:30 UTC (permalink / raw)
To: martin.peres@linux.intel.com, intel-gfx@lists.freedesktop.org,
patchwork@emeril.freedesktop.org
On Fri, 2019-10-11 at 10:16 +0300, Martin Peres wrote:
> On 10/10/2019 23:18, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/4] drm/i915/display: Handle fused
> > off display correctly
> > URL : https://patchwork.freedesktop.org/series/67872/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7058 -> Patchwork_14757
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_14757 absolutely
> > need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the
> > changes
> > introduced in Patchwork_14757, please notify your bug team to
> > allow them
> > to document this new failure mode, which will reduce false
> > positives in CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/index.html
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in
> > Patchwork_14757:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@i915_selftest@live_hangcheck:
> > - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
> > [1]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7058/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
> > [2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
>
> Do you think this is related to your patch series?
Yes, patch 3 is complete wrong but is passed on the retry run...
>
> > * igt@runner@aborted:
> > - fi-bxt-dsi: NOTRUN -> [FAIL][3]
> > [3]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-bxt-dsi/igt@runner@aborted.html
> > - fi-apl-guc: NOTRUN -> [FAIL][4]
> > [4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14757/fi-apl-guc/igt@runner@aborted.html
>
> <7>[ 7.816334] [drm:intel_dump_cdclk_state [i915]] Current CDCLK
> 624000 kHz, VCO 1248000 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
> level 25
> <4>[ 7.816371] ------------[ cut here ]------------
> <4>[ 7.816375] WARN_ON(vco != 8100000 && vco != 8640000)
> <4>[ 7.816540] WARNING: CPU: 2 PID: 330 at
> drivers/gpu/drm/i915/display/intel_cdclk.c:2392
> intel_update_max_cdclk+0x27f/0x330 [i915]
> <4>[ 7.816544] Modules linked in: i915(+) x86_pkg_temp_thermal
> coretemp btusb btrtl crct10dif_pclmul btbcm crc32_pclmul btintel
> snd_hda_intel snd_intel_nhlt bluetooth snd_hda_codec
> ghash_clmulni_intel
> snd_hwdep snd_hda_core ecdh_generic ecc lpc_ich snd_pcm r8169 realtek
> mei_me mei prime_numbers pinctrl_broxton pinctrl_intel
> <4>[ 7.816575] CPU: 2 PID: 330 Comm: modprobe Tainted: G U
> 5.4.0-rc2-CI-Patchwork_14757+ #1
> <4>[ 7.816579] Hardware name: Intel corporation NUC6CAYS/NUC6CAYB,
> BIOS AYAPLCEL.86A.0056.2018.0926.1100 09/26/2018
> <4>[ 7.816705] RIP: 0010:intel_update_max_cdclk+0x27f/0x330 [i915]
> <4>[ 7.816710] Code: 4c 0a 00 e9 e0 fd ff ff 69 f0 b4 00 00 00 e9
> 59
> ff ff ff 48 c7 c6 d0 9c 46 a0 48 c7 c7 c3 07 49 a0 89 44 24 04 e8 51
> 71
> d4 e0 <0f> 0b 8b 44 24 04 e9 94 fe ff ff c7 87 e0 8f 00 00 80 d5 04
> 00 b8
> <4>[ 7.816714] RSP: 0000:ffffc9000036b9c8 EFLAGS: 00010286
> <4>[ 7.816718] RAX: 0000000000000000 RBX: ffff888258600000 RCX:
> 0000000000000002
> <4>[ 7.816722] RDX: 0000000000000006 RSI: ffff8882614e56d0 RDI:
> ffffffff8213bd09
> <4>[ 7.816725] RBP: 0000000000000000 R08: ffff8882614e56d0 R09:
> 0000000000000000
> <4>[ 7.816729] R10: 0000000000000000 R11: 0000000000000000 R12:
> 0000000000000003
> <4>[ 7.816732] R13: 0000000000000002 R14: ffff888258600000 R15:
> 0000000000000000
> <4>[ 7.816736] FS: 00007f016a3d6540(0000)
> GS:ffff888277b00000(0000)
> knlGS:0000000000000000
> <4>[ 7.816739] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> <4>[ 7.816743] CR2: 00007fc9f38265a0 CR3: 0000000262ea0000 CR4:
> 00000000003406e0
> <4>[ 7.816746] Call Trace:
> <4>[ 7.816863] intel_modeset_init+0xcfc/0x1be0 [i915]
> <4>[ 7.816958] ? intel_irq_postinstall+0x1a6/0x5c0 [i915]
> <4>[ 7.817051] i915_driver_probe+0xb68/0x15e0 [i915]
> <4>[ 7.817065] ? find_held_lock+0x2d/0x90
> <4>[ 7.817073] ? __pm_runtime_resume+0x4f/0x80
> <4>[ 7.817172] i915_pci_probe+0x43/0x1b0 [i915]
> <4>[ 7.817180] ? _raw_spin_unlock_irqrestore+0x39/0x60
> <4>[ 7.817190] pci_device_probe+0x9e/0x120
> <4>[ 7.817199] really_probe+0xea/0x420
> <4>[ 7.817207] driver_probe_device+0x10b/0x120
> <4>[ 7.817214] device_driver_attach+0x4a/0x50
> <4>[ 7.817220] __driver_attach+0x97/0x130
> <4>[ 7.817226] ? device_driver_attach+0x50/0x50
> <4>[ 7.817231] bus_for_each_dev+0x74/0xc0
> <4>[ 7.817239] bus_add_driver+0x142/0x220
> <4>[ 7.817245] ? 0xffffffffa05a7000
> <4>[ 7.817250] driver_register+0x56/0xf0
> <4>[ 7.817255] ? 0xffffffffa05a7000
> <4>[ 7.817260] do_one_initcall+0x58/0x2ff
> <4>[ 7.817267] ? rcu_read_lock_sched_held+0x4d/0x80
> <4>[ 7.817274] ? kmem_cache_alloc_trace+0x290/0x2c0
> <4>[ 7.817284] do_init_module+0x56/0x1f8
> <4>[ 7.817290] load_module+0x243e/0x29f0
> <4>[ 7.817320] ? __do_sys_finit_module+0xe9/0x110
> <4>[ 7.817324] __do_sys_finit_module+0xe9/0x110
> <4>[ 7.817344] do_syscall_64+0x4f/0x210
> <4>[ 7.817350] entry_SYSCALL_64_after_hwframe+0x49/0xbe
> <4>[ 7.817355] RIP: 0033:0x7f0169ef3839
> <4>[ 7.817361] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f
> 40
> 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24
> 08
> 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89
> 01 48
> <4>[ 7.817364] RSP: 002b:00007ffcf9965528 EFLAGS: 00000246
> ORIG_RAX:
> 0000000000000139
> <4>[ 7.817369] RAX: ffffffffffffffda RBX: 000055c220e52f60 RCX:
> 00007f0169ef3839
> <4>[ 7.817372] RDX: 0000000000000000 RSI: 000055c220e4bb30 RDI:
> 0000000000000000
> <4>[ 7.817376] RBP: 000055c220e4bb30 R08: 0000000000000000 R09:
> 0000000000000000
> <4>[ 7.817379] R10: 0000000000000000 R11: 0000000000000246 R12:
> 0000000000000000
> <4>[ 7.817382] R13: 000055c220e53090 R14: 0000000000040000 R15:
> 0000000000000000
> <4>[ 7.817399] irq event stamp: 398376
> <4>[ 7.817405] hardirqs last enabled at (398375):
> [<ffffffff8112a7fc>] vprintk_emit+0xcc/0x340
> <4>[ 7.817409] hardirqs last disabled at (398376):
> [<ffffffff81001bba>] trace_hardirqs_off_thunk+0x1a/0x20
> <4>[ 7.817414] softirqs last enabled at (398360):
> [<ffffffff81c00385>] __do_softirq+0x385/0x47f
> <4>[ 7.817419] softirqs last disabled at (398353):
> [<ffffffff810b7eaa>] irq_exit+0xba/0xc0
> <4>[ 7.817422] ---[ end trace 43ed7a1d8633a989 ]---
>
> Anyways, thanks for doing this work! That makes me think that maybe
> we
> do not have good reporting capabilities for fused-off functionalities
> which might confuse the userspace and developers looking at bug
> reports.
>
> Martin
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/4] drm/i915/display: Handle fused off display correctly
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
` (3 preceding siblings ...)
2019-10-10 20:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly Patchwork
@ 2019-10-11 12:25 ` Ville Syrjälä
2019-10-11 15:00 ` Souza, Jose
4 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjälä @ 2019-10-11 12:25 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Thu, Oct 10, 2019 at 12:32:38PM -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above.
>
> On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
> it has another function, probably on GEN 9 when bit 31 is set all
> the 3 pipes disable bit are set, so we can unify the handling.
I'm not sure this is really correct. The description says the pipe will
just output a solid color, so the display hardware may be there to some
degree and if we don't want to waste power we may have to power manage
some of it still.
Not sure how high up we've plugged in the 'pipe_mask==0 -> display not
there' logic. If it's too high up we may leave some power on the floor.
But all that is just speculation on my part. Would probably be good
to get some clarification to the spec about this stuff.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..c01fccfe3cca 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,14 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> enabled_mask &= ~BIT(PIPE_D);
>
> /*
> - * At least one pipe should be enabled and if there are
> - * disabled pipes, they should be the last ones, with no holes
> - * in the mask.
> + * If there are disabled pipes, they should be the last ones,
> + * with no holes in the mask.
> */
> - if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> + if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
> enabled_mask);
> - else
> - info->pipe_mask = enabled_mask;
> +
> + info->pipe_mask = enabled_mask;
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.23.0
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 1/4] drm/i915/display: Handle fused off display correctly
2019-10-11 12:25 ` [PATCH 1/4] " Ville Syrjälä
@ 2019-10-11 15:00 ` Souza, Jose
0 siblings, 0 replies; 13+ messages in thread
From: Souza, Jose @ 2019-10-11 15:00 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas
On Fri, 2019-10-11 at 15:25 +0300, Ville Syrjälä wrote:
> On Thu, Oct 10, 2019 at 12:32:38PM -0700, José Roberto de Souza
> wrote:
> > If all pipes are fused off it means that display is disabled,
> > similar
> > like we handle for GEN 7 and 8 right above.
> >
> > On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer
> > GENs
Here should be bit 30 is "Internal Display Disable".
If bit 31 is set I guess not even GT is available but will not handle
this here.
> > it has another function, probably on GEN 9 when bit 31 is set all
> > the 3 pipes disable bit are set, so we can unify the handling.
>
> I'm not sure this is really correct. The description says the pipe
> will
> just output a solid color, so the display hardware may be there to
> some
> degree and if we don't want to waste power we may have to power
> manage
> some of it still.
>
> Not sure how high up we've plugged in the 'pipe_mask==0 -> display
> not
> there' logic. If it's too high up we may leave some power on the
> floor.
>
> But all that is just speculation on my part. Would probably be good
> to get some clarification to the spec about this stuff.
So would be better set i915_modparams.disable_display = 1, so in future
we can power off.
>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_device_info.c | 11 +++++------
> > 1 file changed, 5 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 85e480bdc673..c01fccfe3cca 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -972,15 +972,14 @@ void intel_device_info_runtime_init(struct
> > drm_i915_private *dev_priv)
> > enabled_mask &= ~BIT(PIPE_D);
> >
> > /*
> > - * At least one pipe should be enabled and if there are
> > - * disabled pipes, they should be the last ones, with
> > no holes
> > - * in the mask.
> > + * If there are disabled pipes, they should be the last
> > ones,
> > + * with no holes in the mask.
> > */
> > - if (enabled_mask == 0 || !is_power_of_2(enabled_mask +
> > 1))
> > + if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> > DRM_ERROR("invalid pipe fuse configuration:
> > enabled_mask=0x%x\n",
> > enabled_mask);
> > - else
> > - info->pipe_mask = enabled_mask;
> > +
> > + info->pipe_mask = enabled_mask;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > --
> > 2.23.0
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^ permalink raw reply [flat|nested] 13+ messages in thread