Re: [PATCH] drm/i915/selftests: Add coverage of mocs registers

["Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>]

On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote:
> Probe the mocs registers for new contexts and across GPU resets. Similar
> to intel_workarounds, we have tables of what register values we expect
> to see, so verify that user contexts are affected by them. In the
> future, we should add tests similar to intel_sseu to cover dynamic
> reconfigurations.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>

s/for_each_engine/for_each_uabi_engine ?

Otherwise

Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c          |   4 +
>  drivers/gpu/drm/i915/gt/selftest_mocs.c       | 393 ++++++++++++++++++
>  .../drm/i915/selftests/i915_live_selftests.h  |   1 +
>  3 files changed, 398 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 445ec025bda0..06dba7ff294e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -448,3 +448,7 @@ void intel_mocs_init(struct intel_gt *gt)
>  	if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
>  		init_global_mocs(gt);
>  }
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> +#include "selftest_mocs.c"
> +#endif
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> new file mode 100644
> index 000000000000..ca9679c3ee68
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -0,0 +1,393 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "gt/intel_engine_pm.h"
> +#include "i915_selftest.h"
> +
> +#include "gem/selftests/mock_context.h"
> +#include "selftests/igt_reset.h"
> +#include "selftests/igt_spinner.h"
> +
> +struct live_mocs {
> +	struct drm_i915_mocs_table table;
> +	struct i915_vma *scratch;
> +	void *vaddr;
> +};
> +
> +static int request_add_sync(struct i915_request *rq, int err)
> +{
> +	i915_request_get(rq);
> +	i915_request_add(rq);
> +	if (i915_request_wait(rq, 0, HZ / 5) < 0)
> +		err = -ETIME;
> +	i915_request_put(rq);
> +
> +	return err;
> +}
> +
> +static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
> +{
> +	int err = 0;
> +
> +	i915_request_get(rq);
> +	i915_request_add(rq);
> +	if (spin && !igt_wait_for_spinner(spin, rq))
> +		err = -ETIME;
> +	i915_request_put(rq);
> +
> +	return err;
> +}
> +
> +static struct i915_vma *create_scratch(struct intel_gt *gt)
> +{
> +	struct drm_i915_gem_object *obj;
> +	struct i915_vma *vma;
> +	int err;
> +
> +	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> +	if (IS_ERR(obj))
> +		return ERR_CAST(obj);
> +
> +	i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
> +
> +	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
> +	if (IS_ERR(vma)) {
> +		i915_gem_object_put(obj);
> +		return vma;
> +	}
> +
> +	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
> +	if (err) {
> +		i915_gem_object_put(obj);
> +		return ERR_PTR(err);
> +	}
> +
> +	return vma;
> +}
> +
> +static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
> +{
> +	int err;
> +
> +	if (!get_mocs_settings(gt->i915, &arg->table))
> +		return -EINVAL;
> +
> +	arg->scratch = create_scratch(gt);
> +	if (IS_ERR(arg->scratch))
> +		return PTR_ERR(arg->scratch);
> +
> +	arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
> +	if (IS_ERR(arg->vaddr)) {
> +		err = PTR_ERR(arg->vaddr);
> +		goto err_scratch;
> +	}
> +
> +	return 0;
> +
> +err_scratch:
> +	i915_vma_unpin_and_release(&arg->scratch, 0);
> +	return err;
> +}
> +
> +static void live_mocs_fini(struct live_mocs *arg)
> +{
> +	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
> +}
> +
> +static int read_regs(struct i915_request *rq,
> +		     u32 addr, unsigned int count,
> +		     uint32_t *offset)
> +{
> +	unsigned int i;
> +	u32 *cs;
> +
> +	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
> +
> +	cs = intel_ring_begin(rq, 4 * count);
> +	if (IS_ERR(cs))
> +		return PTR_ERR(cs);
> +
> +	for (i = 0; i < count; i++) {
> +		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> +		*cs++ = addr;
> +		*cs++ = *offset;
> +		*cs++ = 0;
> +
> +		addr += sizeof(u32);
> +		*offset += sizeof(u32);
> +	}
> +
> +	intel_ring_advance(rq, cs);
> +
> +	return 0;
> +}
> +
> +static int read_mocs_table(struct i915_request *rq,
> +			   const struct drm_i915_mocs_table *table,
> +			   uint32_t *offset)
> +{
> +	u32 addr;
> +
> +	if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> +		addr = 0x4000;
> +	else
> +		addr = mocs_register(rq->engine);
> +
> +	return read_regs(rq, addr, table->n_entries, offset);
> +}
> +
> +static int read_l3cc_table(struct i915_request *rq,
> +			   const struct drm_i915_mocs_table *table,
> +			   uint32_t *offset)
> +{
> +	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
> +	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
> +
> +	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
> +}
> +
> +static int check_mocs_table(struct intel_engine_cs *engine,
> +			    const struct drm_i915_mocs_table *table,
> +			    uint32_t **vaddr)
> +{
> +	unsigned int i;
> +	u32 expect;
> +
> +	for_each_mocs(expect, table, i) {
> +		if (**vaddr != expect) {
> +			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
> +			       engine->name, i, **vaddr, expect);
> +			return -EINVAL;
> +		}
> +		++*vaddr;
> +	}
> +
> +	return 0;
> +}
> +
> +static int check_l3cc_table(struct intel_engine_cs *engine,
> +			    const struct drm_i915_mocs_table *table,
> +			    uint32_t **vaddr)
> +{
> +	unsigned int i;
> +	u32 expect;
> +
> +	for_each_l3cc(expect, table, i) {
> +		if (**vaddr != expect) {
> +			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
> +			       engine->name, i, **vaddr, expect);
> +			return -EINVAL;
> +		}
> +		++*vaddr;
> +	}
> +
> +	return 0;
> +}
> +
> +static int check_mocs_engine(struct live_mocs *arg,
> +			     struct intel_context *ce)
> +{
> +	struct i915_vma *vma = arg->scratch;
> +	struct i915_request *rq;
> +	u32 offset;
> +	u32 *vaddr;
> +	int err;
> +
> +	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
> +
> +	rq = intel_context_create_request(ce);
> +	if (IS_ERR(rq))
> +		return PTR_ERR(rq);
> +
> +	i915_vma_lock(vma);
> +	err = i915_request_await_object(rq, vma->obj, true);
> +	if (!err)
> +		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
> +	i915_vma_unlock(vma);
> +
> +	offset = i915_ggtt_offset(vma);
> +	if (!err)
> +		err = read_mocs_table(rq, &arg->table, &offset);
> +	if (!err && ce->engine->class == RENDER_CLASS)
> +		err = read_l3cc_table(rq, &arg->table, &offset);
> +	offset -= i915_ggtt_offset(vma);
> +	GEM_BUG_ON(offset > PAGE_SIZE);
> +
> +	err = request_add_sync(rq, err);
> +	if (err)
> +		return err;
> +
> +	vaddr = arg->vaddr;
> +	if (!err)
> +		err = check_mocs_table(ce->engine, &arg->table, &vaddr);
> +	if (!err && ce->engine->class == RENDER_CLASS)
> +		err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
> +	if (err)
> +		return err;
> +
> +	GEM_BUG_ON(arg->vaddr + offset != vaddr);
> +	return 0;
> +}
> +
> +static int live_mocs_kernel(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +	struct live_mocs mocs;
> +	int err;
> +
> +	err = live_mocs_init(&mocs, gt);
> +	if (err)
> +		return err;
> +
> +	for_each_engine(engine, gt, id) {
> +		err = check_mocs_engine(&mocs, engine->kernel_context);
> +		if (err)
> +			break;
> +	}
> +
> +	live_mocs_fini(&mocs);
> +	return err;
> +}
> +
> +static int live_mocs_clean(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +	struct live_mocs mocs;
> +	int err;
> +
> +	err = live_mocs_init(&mocs, gt);
> +	if (err)
> +		return err;
> +
> +	for_each_engine(engine, gt, id) {
> +		struct intel_context *ce;
> +
> +		ce = intel_context_create(engine->kernel_context->gem_context,
> +					  engine);
> +		if (IS_ERR(ce)) {
> +			err = PTR_ERR(ce);
> +			break;
> +		}
> +
> +		err = check_mocs_engine(&mocs, ce);
> +		intel_context_put(ce);
> +		if (err)
> +			break;
> +	}
> +
> +	live_mocs_fini(&mocs);
> +	return err;
> +}
> +
> +static int active_engine_reset(struct intel_context *ce,
> +			       const char *reason)
> +{
> +	struct igt_spinner spin;
> +	struct i915_request *rq;
> +	int err;
> +
> +	err = igt_spinner_init(&spin, ce->engine->gt);
> +	if (err)
> +		return err;
> +
> +	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
> +	if (IS_ERR(rq)) {
> +		igt_spinner_fini(&spin);
> +		return PTR_ERR(rq);
> +	}
> +
> +	err = request_add_spin(rq, &spin);
> +	if (err == 0)
> +		err = intel_engine_reset(ce->engine, reason);
> +
> +	igt_spinner_end(&spin);
> +	igt_spinner_fini(&spin);
> +
> +	return err;
> +}
> +
> +static int __live_mocs_reset(struct live_mocs *mocs,
> +			     struct intel_context *ce)
> +{
> +	int err;
> +
> +	err = intel_engine_reset(ce->engine, "mocs");
> +	if (err)
> +		return err;
> +
> +	err = check_mocs_engine(mocs, ce);
> +	if (err)
> +		return err;
> +
> +	err = active_engine_reset(ce, "mocs");
> +	if (err)
> +		return err;
> +
> +	err = check_mocs_engine(mocs, ce);
> +	if (err)
> +		return err;
> +
> +	return 0;
> +}
> +
> +static int live_mocs_reset(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +	struct live_mocs mocs;
> +	int err = 0;
> +
> +	if (!intel_has_reset_engine(gt))
> +		return 0;
> +
> +	err = live_mocs_init(&mocs, gt);
> +	if (err)
> +		return err;
> +
> +	igt_global_reset_lock(gt);
> +	for_each_engine(engine, gt, id) {
> +		struct intel_context *ce;
> +
> +		ce = intel_context_create(engine->kernel_context->gem_context,
> +					  engine);
> +		if (IS_ERR(ce)) {
> +			err = PTR_ERR(ce);
> +			break;
> +		}
> +
> +		intel_engine_pm_get(engine);
> +		err = __live_mocs_reset(&mocs, ce);
> +		intel_engine_pm_put(engine);
> +
> +		intel_context_put(ce);
> +		if (err)
> +			break;
> +	}
> +	igt_global_reset_unlock(gt);
> +
> +	live_mocs_fini(&mocs);
> +	return err;
> +}
> +
> +int intel_mocs_live_selftests(struct drm_i915_private *i915)
> +{
> +	static const struct i915_subtest tests[] = {
> +		SUBTEST(live_mocs_kernel),
> +		SUBTEST(live_mocs_clean),
> +		SUBTEST(live_mocs_reset),
> +	};
> +	struct drm_i915_mocs_table table;
> +
> +	if (!get_mocs_settings(i915, &table))
> +		return 0;
> +
> +	return intel_gt_live_subtests(tests, &i915->gt);
> +}
> diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> index 00a063730bc3..c23d06bca09e 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> +++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
> @@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
>  selftest(gt_timelines, intel_timeline_live_selftests)
>  selftest(gt_contexts, intel_context_live_selftests)
>  selftest(gt_lrc, intel_lrc_live_selftests)
> +selftest(gt_mocs, intel_mocs_live_selftests)
>  selftest(gt_pm, intel_gt_pm_live_selftests)
>  selftest(gt_heartbeat, intel_heartbeat_live_selftests)
>  selftest(requests, i915_request_live_selftests)
> -- 
> 2.24.0.rc0
> 
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