[PATCH 1/5] drm/i915/display: Handle fused off display correctly

[PATCH 1/5] drm/i915/display: Handle fused off display correctly

[José Roberto de Souza]

If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above but for GEN9+ spec says
that hardware will override the pipe output to a solid color, so
some display is there and maybe we would need to shutdown display
to save power, so setting disable_display = true, to keep consistent
to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().

In addition to have all pipes fused off, GEN/display 9 have the
bit 30 "Internal Display Disable", not sure if all pipes will be set
as unfused when this bit is set so handling both.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
 drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 855db888516c..6e3ae6e9cbb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7651,16 +7651,17 @@ enum {
 #define   MASK_WAKEMEM			(1 << 13)
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
-#define SKL_DFSM			_MMIO(0x51000)
-#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
-#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
-#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
-#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
-#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
+#define SKL_DFSM				_MMIO(0x51000)
+#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
+#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 85e480bdc673..8d6492afdd6a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			enabled_mask &= ~BIT(PIPE_D);
 
 		/*
-		 * At least one pipe should be enabled and if there are
-		 * disabled pipes, they should be the last ones, with no holes
-		 * in the mask.
+		 * If there are disabled pipes, they should be the last ones,
+		 * with no holes in the mask.
 		 */
-		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
+		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
 			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
 				  enabled_mask);
 		else
 			info->pipe_mask = enabled_mask;
+
+		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
+		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
+			i915_modparams.disable_display = true;
+
+		if (!enabled_mask)
+			i915_modparams.disable_display = true;
 	}
 
 	/* Initialize slice/subslice/EU info */
-- 
2.23.0

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[PATCH 2/5] drm/i915/display: Handle fused off HDCP

[José Roberto de Souza]

HDCP could be fused off, so not all GEN9+ platforms will support it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
 drivers/gpu/drm/i915/i915_pci.c           | 2 ++
 drivers/gpu/drm/i915/i915_reg.h           | 1 +
 drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h  | 1 +
 5 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e69fa34528df..f1f41ca8402b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
+	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
 }
 
 static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9a3bfe68689..f2280709c8c9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_preemption = 1, \
 	.display.has_csr = 1, \
 	.has_gt_uc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
 	.ddb_size = 896
 
@@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.display.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.display.has_fbc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_psr = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_csr = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e3ae6e9cbb8..eacc5ba307b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7653,6 +7653,7 @@ enum {
 
 #define SKL_DFSM				_MMIO(0x51000)
 #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
+#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
 #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8d6492afdd6a..753c2cf2fbf4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 		if (!enabled_mask)
 			i915_modparams.disable_display = true;
+
+		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
+			info->display.has_hdcp = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e9940f932d26..118d922261e2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -138,6 +138,7 @@ enum intel_ppgtt_type {
 	func(has_dsb); \
 	func(has_fbc); \
 	func(has_gmch); \
+	func(has_hdcp); \
 	func(has_hotplug); \
 	func(has_ipc); \
 	func(has_modular_fia); \
-- 
2.23.0

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Re: [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Ramalingam C]

On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
Here HDCP stands for HDCP1.4, so please call it so.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
>  drivers/gpu/drm/i915/i915_reg.h           | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
>  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
>  5 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
>  }
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f9a3bfe68689..f2280709c8c9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_logical_ring_preemption = 1, \
>  	.display.has_csr = 1, \
>  	.has_gt_uc = 1, \
> +	.display.has_hdcp = 1, \
We dont support HDCP1.4 on chv, though hw supports it.
>  	.display.has_ipc = 1, \
>  	.ddb_size = 896
>  
> @@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.display.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
>  	.display.has_fbc = 1, \
> +	.display.has_hdcp = 1, \
Need not add for each platform, Instead add it into GEN9_FEATURES and GEN9_LP_FEATURES.
HDCP1.4 is supported on all Gen 9+ unless it is fused off.

-Ram.
>  	.display.has_psr = 1, \
>  	.has_runtime_pm = 1, \
>  	.display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e3ae6e9cbb8..eacc5ba307b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>  
>  #define SKL_DFSM				_MMIO(0x51000)
>  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 8d6492afdd6a..753c2cf2fbf4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (!enabled_mask)
>  			i915_modparams.disable_display = true;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> +			info->display.has_hdcp = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e9940f932d26..118d922261e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
>  	func(has_dsb); \
>  	func(has_fbc); \
>  	func(has_gmch); \
> +	func(has_hdcp); \
>  	func(has_hotplug); \
>  	func(has_ipc); \
>  	func(has_modular_fia); \
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Ramalingam C]

On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
Here HDCP stands for HDCP1.4, so please call it so.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
>  drivers/gpu/drm/i915/i915_reg.h           | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
>  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
>  5 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
>  }
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f9a3bfe68689..f2280709c8c9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_logical_ring_preemption = 1, \
>  	.display.has_csr = 1, \
>  	.has_gt_uc = 1, \
> +	.display.has_hdcp = 1, \
We dont support HDCP1.4 on chv, though hw supports it.
>  	.display.has_ipc = 1, \
>  	.ddb_size = 896
>  
> @@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.display.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
>  	.display.has_fbc = 1, \
> +	.display.has_hdcp = 1, \
Need not add for each platform, Instead add it into GEN9_FEATURES and GEN9_LP_FEATURES.
HDCP1.4 is supported on all Gen 9+ unless it is fused off.

-Ram.
>  	.display.has_psr = 1, \
>  	.has_runtime_pm = 1, \
>  	.display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e3ae6e9cbb8..eacc5ba307b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>  
>  #define SKL_DFSM				_MMIO(0x51000)
>  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 8d6492afdd6a..753c2cf2fbf4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (!enabled_mask)
>  			i915_modparams.disable_display = true;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> +			info->display.has_hdcp = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e9940f932d26..118d922261e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
>  	func(has_dsb); \
>  	func(has_fbc); \
>  	func(has_gmch); \
> +	func(has_hdcp); \
>  	func(has_hotplug); \
>  	func(has_ipc); \
>  	func(has_modular_fia); \
> -- 
> 2.23.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Souza, Jose]

On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > HDCP could be fused off, so not all GEN9+ platforms will support
> > it.
> Here HDCP stands for HDCP1.4, so please call it so.

Okay, will update the commit description with the version.


> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Martin Peres <martin.peres@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> >  5 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index e69fa34528df..f1f41ca8402b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > work_struct *work)
> >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > port port)
> >  {
> >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> >  }
> >  
> >  static int
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f9a3bfe68689..f2280709c8c9 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > intel_cherryview_info = {
> >  	.has_logical_ring_preemption = 1, \
> >  	.display.has_csr = 1, \
> >  	.has_gt_uc = 1, \
> > +	.display.has_hdcp = 1, \
> We dont support HDCP1.4 on chv, though hw supports it.
> >  	.display.has_ipc = 1, \
> >  	.ddb_size = 896
> >  
> > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > intel_skylake_gt4_info = {
> >  	.display.has_ddi = 1, \
> >  	.has_fpga_dbg = 1, \
> >  	.display.has_fbc = 1, \
> > +	.display.has_hdcp = 1, \
> Need not add for each platform, Instead add it into GEN9_FEATURES and
> GEN9_LP_FEATURES.
> HDCP1.4 is supported on all Gen 9+ unless it is fused off.

It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
diff it what you commented, you can check the real output of this patch
here:

https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c


> 
> -Ram.
> >  	.display.has_psr = 1, \
> >  	.has_runtime_pm = 1, \
> >  	.display.has_csr = 1, \
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7653,6 +7653,7 @@ enum {
> >  
> >  #define SKL_DFSM				_MMIO(0x51000)
> >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 8d6492afdd6a..753c2cf2fbf4 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > drm_i915_private *dev_priv)
> >  
> >  		if (!enabled_mask)
> >  			i915_modparams.disable_display = true;
> > +
> > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > +			info->display.has_hdcp = 0;
> >  	}
> >  
> >  	/* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index e9940f932d26..118d922261e2 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> >  	func(has_dsb); \
> >  	func(has_fbc); \
> >  	func(has_gmch); \
> > +	func(has_hdcp); \
> >  	func(has_hotplug); \
> >  	func(has_ipc); \
> >  	func(has_modular_fia); \
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Souza, Jose]

On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > HDCP could be fused off, so not all GEN9+ platforms will support
> > it.
> Here HDCP stands for HDCP1.4, so please call it so.

Okay, will update the commit description with the version.


> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Martin Peres <martin.peres@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> >  5 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index e69fa34528df..f1f41ca8402b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > work_struct *work)
> >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > port port)
> >  {
> >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> >  }
> >  
> >  static int
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f9a3bfe68689..f2280709c8c9 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > intel_cherryview_info = {
> >  	.has_logical_ring_preemption = 1, \
> >  	.display.has_csr = 1, \
> >  	.has_gt_uc = 1, \
> > +	.display.has_hdcp = 1, \
> We dont support HDCP1.4 on chv, though hw supports it.
> >  	.display.has_ipc = 1, \
> >  	.ddb_size = 896
> >  
> > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > intel_skylake_gt4_info = {
> >  	.display.has_ddi = 1, \
> >  	.has_fpga_dbg = 1, \
> >  	.display.has_fbc = 1, \
> > +	.display.has_hdcp = 1, \
> Need not add for each platform, Instead add it into GEN9_FEATURES and
> GEN9_LP_FEATURES.
> HDCP1.4 is supported on all Gen 9+ unless it is fused off.

It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
diff it what you commented, you can check the real output of this patch
here:

https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c


> 
> -Ram.
> >  	.display.has_psr = 1, \
> >  	.has_runtime_pm = 1, \
> >  	.display.has_csr = 1, \
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7653,6 +7653,7 @@ enum {
> >  
> >  #define SKL_DFSM				_MMIO(0x51000)
> >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 8d6492afdd6a..753c2cf2fbf4 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > drm_i915_private *dev_priv)
> >  
> >  		if (!enabled_mask)
> >  			i915_modparams.disable_display = true;
> > +
> > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > +			info->display.has_hdcp = 0;
> >  	}
> >  
> >  	/* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index e9940f932d26..118d922261e2 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> >  	func(has_dsb); \
> >  	func(has_fbc); \
> >  	func(has_gmch); \
> > +	func(has_hdcp); \
> >  	func(has_hotplug); \
> >  	func(has_ipc); \
> >  	func(has_modular_fia); \
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Ramalingam C]

On 2019-10-24 at 00:24:00 +0530, Souza, Jose wrote:
> On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > > HDCP could be fused off, so not all GEN9+ platforms will support
> > > it.
> > Here HDCP stands for HDCP1.4, so please call it so.
> 
> Okay, will update the commit description with the version.
> 
> 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Martin Peres <martin.peres@linux.intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> > >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> > >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> > >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> > >  5 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index e69fa34528df..f1f41ca8402b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > > work_struct *work)
> > >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > > port port)
> > >  {
> > >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> > >  }
> > >  
> > >  static int
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index f9a3bfe68689..f2280709c8c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > > intel_cherryview_info = {
> > >  	.has_logical_ring_preemption = 1, \
> > >  	.display.has_csr = 1, \
> > >  	.has_gt_uc = 1, \
> > > +	.display.has_hdcp = 1, \
> > We dont support HDCP1.4 on chv, though hw supports it.
> > >  	.display.has_ipc = 1, \
> > >  	.ddb_size = 896
> > >  
> > > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > > intel_skylake_gt4_info = {
> > >  	.display.has_ddi = 1, \
> > >  	.has_fpga_dbg = 1, \
> > >  	.display.has_fbc = 1, \
> > > +	.display.has_hdcp = 1, \
> > Need not add for each platform, Instead add it into GEN9_FEATURES and
> > GEN9_LP_FEATURES.
> > HDCP1.4 is supported on all Gen 9+ unless it is fused off.
> 
> It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
> diff it what you commented, you can check the real output of this patch
> here:
Yes. Got it. Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> 
> https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c
> 
> 
> > 
> > -Ram.
> > >  	.display.has_psr = 1, \
> > >  	.has_runtime_pm = 1, \
> > >  	.display.has_csr = 1, \
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7653,6 +7653,7 @@ enum {
> > >  
> > >  #define SKL_DFSM				_MMIO(0x51000)
> > >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> > >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 8d6492afdd6a..753c2cf2fbf4 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >  
> > >  		if (!enabled_mask)
> > >  			i915_modparams.disable_display = true;
> > > +
> > > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > > +			info->display.has_hdcp = 0;
> > >  	}
> > >  
> > >  	/* Initialize slice/subslice/EU info */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > index e9940f932d26..118d922261e2 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> > >  	func(has_dsb); \
> > >  	func(has_fbc); \
> > >  	func(has_gmch); \
> > > +	func(has_hdcp); \
> > >  	func(has_hotplug); \
> > >  	func(has_ipc); \
> > >  	func(has_modular_fia); \
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP

[Ramalingam C]

On 2019-10-24 at 00:24:00 +0530, Souza, Jose wrote:
> On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > > HDCP could be fused off, so not all GEN9+ platforms will support
> > > it.
> > Here HDCP stands for HDCP1.4, so please call it so.
> 
> Okay, will update the commit description with the version.
> 
> 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Martin Peres <martin.peres@linux.intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> > >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> > >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> > >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> > >  5 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index e69fa34528df..f1f41ca8402b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > > work_struct *work)
> > >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > > port port)
> > >  {
> > >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> > >  }
> > >  
> > >  static int
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index f9a3bfe68689..f2280709c8c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > > intel_cherryview_info = {
> > >  	.has_logical_ring_preemption = 1, \
> > >  	.display.has_csr = 1, \
> > >  	.has_gt_uc = 1, \
> > > +	.display.has_hdcp = 1, \
> > We dont support HDCP1.4 on chv, though hw supports it.
> > >  	.display.has_ipc = 1, \
> > >  	.ddb_size = 896
> > >  
> > > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > > intel_skylake_gt4_info = {
> > >  	.display.has_ddi = 1, \
> > >  	.has_fpga_dbg = 1, \
> > >  	.display.has_fbc = 1, \
> > > +	.display.has_hdcp = 1, \
> > Need not add for each platform, Instead add it into GEN9_FEATURES and
> > GEN9_LP_FEATURES.
> > HDCP1.4 is supported on all Gen 9+ unless it is fused off.
> 
> It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
> diff it what you commented, you can check the real output of this patch
> here:
Yes. Got it. Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> 
> https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c
> 
> 
> > 
> > -Ram.
> > >  	.display.has_psr = 1, \
> > >  	.has_runtime_pm = 1, \
> > >  	.display.has_csr = 1, \
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7653,6 +7653,7 @@ enum {
> > >  
> > >  #define SKL_DFSM				_MMIO(0x51000)
> > >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> > >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 8d6492afdd6a..753c2cf2fbf4 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >  
> > >  		if (!enabled_mask)
> > >  			i915_modparams.disable_display = true;
> > > +
> > > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > > +			info->display.has_hdcp = 0;
> > >  	}
> > >  
> > >  	/* Initialize slice/subslice/EU info */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > index e9940f932d26..118d922261e2 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> > >  	func(has_dsb); \
> > >  	func(has_fbc); \
> > >  	func(has_gmch); \
> > > +	func(has_hdcp); \
> > >  	func(has_hotplug); \
> > >  	func(has_ipc); \
> > >  	func(has_modular_fia); \
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 3/5] drm/i915/display: Check if FBC is fused off

[José Roberto de Souza]

Check if FBC is fused off and handle it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eacc5ba307b0..31375ddc2b3b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7653,6 +7653,7 @@ enum {
 
 #define SKL_DFSM				_MMIO(0x51000)
 #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
+#define SKL_DFSM_DISPLAY_PM_DISABLE		(1 << 27)
 #define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
 #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 753c2cf2fbf4..b6a9f527f8f9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -990,6 +990,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 			info->display.has_hdcp = 0;
+
+		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
+			info->display.has_fbc = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
-- 
2.23.0

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Re: [PATCH 3/5] drm/i915/display: Check if FBC is fused off

[Ramalingam C]

On 2019-10-18 at 17:41:22 -0700, José Roberto de Souza wrote:
> Check if FBC is fused off and handle it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eacc5ba307b0..31375ddc2b3b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>  
>  #define SKL_DFSM				_MMIO(0x51000)
>  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE		(1 << 27)
May be you want to add two char like
#define   SKL_DFSM_DISPLAY_PM_DISABLE          (1 << 27)

Either way
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>

-Ram
>  #define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 753c2cf2fbf4..b6a9f527f8f9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -990,6 +990,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
>  			info->display.has_hdcp = 0;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> +			info->display.has_fbc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Check if FBC is fused off

[Ramalingam C]

On 2019-10-18 at 17:41:22 -0700, José Roberto de Souza wrote:
> Check if FBC is fused off and handle it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eacc5ba307b0..31375ddc2b3b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>  
>  #define SKL_DFSM				_MMIO(0x51000)
>  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE		(1 << 27)
May be you want to add two char like
#define   SKL_DFSM_DISPLAY_PM_DISABLE          (1 << 27)

Either way
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>

-Ram
>  #define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 753c2cf2fbf4..b6a9f527f8f9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -990,6 +990,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
>  			info->display.has_hdcp = 0;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> +			info->display.has_fbc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 4/5] drm/i915/display/icl+: Check if DMC is fused off

[José Roberto de Souza]

Check if DMC is fused off and handle it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31375ddc2b3b..84fca4f3af5a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7660,6 +7660,7 @@ enum {
 #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
+#define ICL_DFSM_DMC_DISABLE			(1 << 23)
 #define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
 #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b6a9f527f8f9..97d962944e48 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -993,6 +993,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 			info->display.has_fbc = 0;
+
+		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
+			info->display.has_csr = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
-- 
2.23.0

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Re: [PATCH 4/5] drm/i915/display/icl+: Check if DMC is fused off

[Ramalingam C]

On 2019-10-18 at 17:41:23 -0700, José Roberto de Souza wrote:
> Check if DMC is fused off and handle it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31375ddc2b3b..84fca4f3af5a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7660,6 +7660,7 @@ enum {
>  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define ICL_DFSM_DMC_DISABLE			(1 << 23)
>  #define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index b6a9f527f8f9..97d962944e48 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -993,6 +993,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
>  			info->display.has_fbc = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> +			info->display.has_csr = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/display/icl+: Check if DMC is fused off

[Ramalingam C]

On 2019-10-18 at 17:41:23 -0700, José Roberto de Souza wrote:
> Check if DMC is fused off and handle it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 31375ddc2b3b..84fca4f3af5a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7660,6 +7660,7 @@ enum {
>  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define ICL_DFSM_DMC_DISABLE			(1 << 23)
>  #define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index b6a9f527f8f9..97d962944e48 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -993,6 +993,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
>  			info->display.has_fbc = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> +			info->display.has_csr = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC

[José Roberto de Souza]

DSC could be fused off, so not all GEN10+ platforms will support it.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 5 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3792d143bea9..e01690701fdd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
+	if (!INTEL_INFO(dev_priv)->display.has_dsc)
+		return false;
+
 	/* On TGL, DSC is supported on all Pipes */
 	if (INTEL_GEN(dev_priv) >= 12)
 		return true;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f2280709c8c9..09dbfea7c81f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
 	GEN9_FEATURES, \
 	GEN(10), \
 	.ddb_size = 1024, \
+	.display.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84fca4f3af5a..bfa301759b6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7665,6 +7665,7 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
 #define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
+#define CNL_DFSM_DISPLAY_DSC_DISABLE		(1 << 7)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 97d962944e48..6a24e85c6d10 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 			info->display.has_csr = 0;
+
+		if (INTEL_GEN(dev_priv) >= 10 &&
+		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
+			info->display.has_dsc = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 118d922261e2..ba31d68bb7ba 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -136,6 +136,7 @@ enum intel_ppgtt_type {
 	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_dsb); \
+	func(has_dsc); \
 	func(has_fbc); \
 	func(has_gmch); \
 	func(has_hdcp); \
-- 
2.23.0

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Re: [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC

[Manasi Navare]

On Fri, Oct 18, 2019 at 05:41:24PM -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
>  drivers/gpu/drm/i915/i915_pci.c          | 1 +
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  5 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3792d143bea9..e01690701fdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> +	if (!INTEL_INFO(dev_priv)->display.has_dsc)
> +		return false;
> +
>  	/* On TGL, DSC is supported on all Pipes */
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		return true;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f2280709c8c9..09dbfea7c81f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
>  	GEN9_FEATURES, \
>  	GEN(10), \
>  	.ddb_size = 1024, \
> +	.display.has_dsc = 1, \
>  	.has_coherent_ggtt = false, \
>  	GLK_COLORS
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84fca4f3af5a..bfa301759b6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7665,6 +7665,7 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>  #define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> +#define CNL_DFSM_DISPLAY_DSC_DISABLE		(1 << 7)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 97d962944e48..6a24e85c6d10 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>  			info->display.has_csr = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 10 &&
> +		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> +			info->display.has_dsc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 118d922261e2..ba31d68bb7ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>  	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_dsb); \
> +	func(has_dsc); \
>  	func(has_fbc); \
>  	func(has_gmch); \
>  	func(has_hdcp); \
> -- 
> 2.23.0
> 
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC

[Manasi Navare]

On Fri, Oct 18, 2019 at 05:41:24PM -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
>  drivers/gpu/drm/i915/i915_pci.c          | 1 +
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  5 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3792d143bea9..e01690701fdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> +	if (!INTEL_INFO(dev_priv)->display.has_dsc)
> +		return false;
> +
>  	/* On TGL, DSC is supported on all Pipes */
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		return true;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f2280709c8c9..09dbfea7c81f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
>  	GEN9_FEATURES, \
>  	GEN(10), \
>  	.ddb_size = 1024, \
> +	.display.has_dsc = 1, \
>  	.has_coherent_ggtt = false, \
>  	GLK_COLORS
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84fca4f3af5a..bfa301759b6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7665,6 +7665,7 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>  #define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> +#define CNL_DFSM_DISPLAY_DSC_DISABLE		(1 << 7)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 97d962944e48..6a24e85c6d10 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>  			info->display.has_csr = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 10 &&
> +		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> +			info->display.has_dsc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 118d922261e2..ba31d68bb7ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>  	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_dsb); \
> +	func(has_dsc); \
>  	func(has_fbc); \
>  	func(has_gmch); \
>  	func(has_hdcp); \
> -- 
> 2.23.0
> 
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC

[Ramalingam C]

On 2019-10-18 at 17:41:24 -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
>  drivers/gpu/drm/i915/i915_pci.c          | 1 +
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  5 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3792d143bea9..e01690701fdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> +	if (!INTEL_INFO(dev_priv)->display.has_dsc)
> +		return false;
> +
>  	/* On TGL, DSC is supported on all Pipes */
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		return true;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f2280709c8c9..09dbfea7c81f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
>  	GEN9_FEATURES, \
>  	GEN(10), \
>  	.ddb_size = 1024, \
> +	.display.has_dsc = 1, \
>  	.has_coherent_ggtt = false, \
>  	GLK_COLORS
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84fca4f3af5a..bfa301759b6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7665,6 +7665,7 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>  #define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> +#define CNL_DFSM_DISPLAY_DSC_DISABLE		(1 << 7)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 97d962944e48..6a24e85c6d10 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>  			info->display.has_csr = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 10 &&
> +		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> +			info->display.has_dsc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 118d922261e2..ba31d68bb7ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>  	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_dsb); \
> +	func(has_dsc); \
>  	func(has_fbc); \
>  	func(has_gmch); \
>  	func(has_hdcp); \
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC

[Ramalingam C]

On 2019-10-18 at 17:41:24 -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c  | 3 +++
>  drivers/gpu/drm/i915/i915_pci.c          | 1 +
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 4 ++++
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  5 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3792d143bea9..e01690701fdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> +	if (!INTEL_INFO(dev_priv)->display.has_dsc)
> +		return false;
> +
>  	/* On TGL, DSC is supported on all Pipes */
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		return true;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f2280709c8c9..09dbfea7c81f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
>  	GEN9_FEATURES, \
>  	GEN(10), \
>  	.ddb_size = 1024, \
> +	.display.has_dsc = 1, \
>  	.has_coherent_ggtt = false, \
>  	GLK_COLORS
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84fca4f3af5a..bfa301759b6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7665,6 +7665,7 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>  #define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> +#define CNL_DFSM_DISPLAY_DSC_DISABLE		(1 << 7)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 97d962944e48..6a24e85c6d10 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>  			info->display.has_csr = 0;
> +
> +		if (INTEL_GEN(dev_priv) >= 10 &&
> +		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> +			info->display.has_dsc = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 118d922261e2..ba31d68bb7ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>  	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_dsb); \
> +	func(has_dsc); \
>  	func(has_fbc); \
>  	func(has_gmch); \
>  	func(has_hdcp); \
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/display: Handle fused off display correctly

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/display: Handle fused off display correctly
URL   : https://patchwork.freedesktop.org/series/68247/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7133 -> Patchwork_14891
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/index.html

Known issues
------------

  Here are the changes found in Patchwork_14891 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@flink-lifetime:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - {fi-icl-guc}:       [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-icl-guc/igt@gem_ctx_create@basic-files.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-icl-guc/igt@gem_ctx_create@basic-files.html
    - {fi-tgl-u}:         [INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-tgl-u/igt@gem_ctx_create@basic-files.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-tgl-u/igt@gem_ctx_create@basic-files.html

  * igt@gem_exec_create@basic:
    - fi-cml-u:           [INCOMPLETE][7] ([fdo#110566]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-cml-u/igt@gem_exec_create@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-cml-u/igt@gem_exec_create@basic.html

  * igt@gem_mmap_gtt@basic:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-icl-u3/igt@gem_mmap_gtt@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-icl-u3/igt@gem_mmap_gtt@basic.html

  * igt@gem_mmap_gtt@basic-write-gtt-no-prefault:
    - {fi-icl-dsi}:       [DMESG-WARN][11] ([fdo#106107]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-gtt-no-prefault.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-icl-dsi/igt@gem_mmap_gtt@basic-write-gtt-no-prefault.html

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [DMESG-WARN][13] ([fdo#106107]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-icl-u3/igt@i915_module_load@reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_coherency:
    - fi-skl-6260u:       [TIMEOUT][15] ([fdo#111944]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-skl-6260u/igt@i915_selftest@live_coherency.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-skl-6260u/igt@i915_selftest@live_coherency.html

  * igt@i915_selftest@live_execlists:
    - fi-whl-u:           [INCOMPLETE][17] ([fdo#112065] / [fdo#112066]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-whl-u/igt@i915_selftest@live_execlists.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-whl-u/igt@i915_selftest@live_execlists.html
    - fi-kbl-7500u:       [INCOMPLETE][19] ([fdo#112065]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-kbl-7500u/igt@i915_selftest@live_execlists.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-kbl-7500u/igt@i915_selftest@live_execlists.html
    - fi-kbl-soraka:      [INCOMPLETE][21] ([fdo#112065]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-kbl-soraka/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-kbl-7500u:       [WARN][23] ([fdo#109483]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111833]: https://bugs.freedesktop.org/show_bug.cgi?id=111833
  [fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
  [fdo#112065]: https://bugs.freedesktop.org/show_bug.cgi?id=112065
  [fdo#112066]: https://bugs.freedesktop.org/show_bug.cgi?id=112066


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7133 -> Patchwork_14891

  CI-20190529: 20190529
  CI_DRM_7133: 7772485d78936b34bff23251190fc5b0759d3045 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5233: 19d40524c102aa086ae536dfb3e81f9b8456099f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14891: a149107510fe3100e2175de4377cdba4794222ff @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a149107510fe drm/i915/display/cnl+: Handle fused off DSC
dd27a6653899 drm/i915/display/icl+: Check if DMC is fused off
690d5b8afde8 drm/i915/display: Check if FBC is fused off
792c6177c2f5 drm/i915/display: Handle fused off HDCP
a250f3c6f26f drm/i915/display: Handle fused off display correctly

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/display: Handle fused off display correctly

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/display: Handle fused off display correctly
URL   : https://patchwork.freedesktop.org/series/68247/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7133_full -> Patchwork_14891_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14891_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_flink_race@flink_name:
    - {shard-tglb}:       [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb1/igt@gem_flink_race@flink_name.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb6/igt@gem_flink_race@flink_name.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - {shard-tglb}:       NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  
Known issues
------------

  Here are the changes found in Patchwork_14891_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@basic-hang-rcs0:
    - shard-apl:          [PASS][4] -> [INCOMPLETE][5] ([fdo#103927])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-apl1/igt@gem_busy@basic-hang-rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-apl6/igt@gem_busy@basic-hang-rcs0.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][6] -> [SKIP][7] ([fdo#110841])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276]) +18 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][10] -> [SKIP][11] ([fdo#111325]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [PASS][14] -> [SKIP][15] ([fdo#109271])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
    - shard-iclb:         [PASS][16] -> [INCOMPLETE][17] ([fdo#107713])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][18] -> [FAIL][19] ([fdo#105363])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
    - shard-glk:          [PASS][20] -> [FAIL][21] ([fdo#105363])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-glk1/igt@kms_flip@flip-vs-expired-vblank.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          [PASS][22] -> [INCOMPLETE][23] ([fdo#105411])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-snb5/igt@kms_flip@flip-vs-suspend.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-snb1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip_tiling@flip-changes-tiling-y:
    - shard-skl:          [PASS][24] -> [FAIL][25] ([fdo#107931] / [fdo#108303])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl6/igt@kms_flip_tiling@flip-changes-tiling-y.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl6/igt@kms_flip_tiling@flip-changes-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][26] -> [FAIL][27] ([fdo#103167]) +4 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-iclb:         [PASS][28] -> [INCOMPLETE][29] ([fdo#106978] / [fdo#107713])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][30] -> [DMESG-WARN][31] ([fdo#108566]) +6 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][32] -> [FAIL][33] ([fdo#108145] / [fdo#110403])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][34] -> [SKIP][35] ([fdo#109441]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-a-query-idle:
    - shard-hsw:          [PASS][36] -> [INCOMPLETE][37] ([fdo#103540])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-hsw6/igt@kms_vblank@pipe-a-query-idle.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-hsw5/igt@kms_vblank@pipe-a-query-idle.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@q-smoketest-vebox:
    - {shard-tglb}:       [INCOMPLETE][38] ([fdo#111735]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb6/igt@gem_ctx_shared@q-smoketest-vebox.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb8/igt@gem_ctx_shared@q-smoketest-vebox.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][40] ([fdo#111325]) -> [PASS][41] +5 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - {shard-tglb}:       [INCOMPLETE][42] ([fdo#111855]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb2/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_softpin@noreloc-interruptible:
    - {shard-tglb}:       [INCOMPLETE][44] ([fdo#111747]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb2/igt@gem_softpin@noreloc-interruptible.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb3/igt@gem_softpin@noreloc-interruptible.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-hsw:          [DMESG-WARN][46] ([fdo#111870]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-hsw2/igt@gem_userptr_blits@dmabuf-unsync.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-hsw5/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@stress-mm-invalidate-close:
    - shard-apl:          [INCOMPLETE][48] ([fdo#103927]) -> [PASS][49] +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-apl7/igt@gem_userptr_blits@stress-mm-invalidate-close.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-apl8/igt@gem_userptr_blits@stress-mm-invalidate-close.html

  * igt@gem_workarounds@suspend-resume:
    - {shard-tglb}:       [INCOMPLETE][50] ([fdo#111832] / [fdo#111850]) -> [PASS][51] +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb4/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@system-suspend:
    - {shard-tglb}:       [INCOMPLETE][52] ([fdo#111747] / [fdo#111850]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb8/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_selftest@live_execlists:
    - shard-skl:          [INCOMPLETE][54] ([fdo#111934]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl6/igt@i915_selftest@live_execlists.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl1/igt@i915_selftest@live_execlists.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][56] ([fdo#108566]) -> [PASS][57] +2 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-apl2/igt@i915_suspend@sysfs-reader.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-apl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][58] ([fdo#103540]) -> [PASS][59] +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - {shard-tglb}:       [FAIL][60] ([fdo#103167]) -> [PASS][61] +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-iclb:         [FAIL][62] ([fdo#103167]) -> [PASS][63] +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][64] ([fdo#108145]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][66] ([fdo#108145] / [fdo#110403]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][68] ([fdo#109441]) -> [PASS][69] +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][70] ([fdo#109276]) -> [PASS][71] +21 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb3/igt@prime_busy@hang-bsd2.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [SKIP][72] ([fdo#109276]) -> [FAIL][73] ([fdo#111330])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb8/igt@gem_mocs_settings@mocs-isolation-bsd2.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [FAIL][74] ([fdo#111330]) -> [SKIP][75] ([fdo#109276])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7133/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/shard-iclb7/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111934]: https://bugs.freedesktop.org/show_bug.cgi?id=111934


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7133 -> Patchwork_14891

  CI-20190529: 20190529
  CI_DRM_7133: 7772485d78936b34bff23251190fc5b0759d3045 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5233: 19d40524c102aa086ae536dfb3e81f9b8456099f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14891: a149107510fe3100e2175de4377cdba4794222ff @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14891/index.html
_______________________________________________
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Re: [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Jani Nikula]

On Fri, 18 Oct 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
>
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;

Hrmh, I really hate the approach of setting module parameters from the
kernel. Including the "sanitizing" them. IMO they should only ever be
set or modified by userspace.

BR,
Jani.

>  	}
>  
>  	/* Initialize slice/subslice/EU info */

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Jani Nikula]

On Fri, 18 Oct 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
>
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;

Hrmh, I really hate the approach of setting module parameters from the
kernel. Including the "sanitizing" them. IMO they should only ever be
set or modified by userspace.

BR,
Jani.

>  	}
>  
>  	/* Initialize slice/subslice/EU info */

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Ramalingam C]

On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> 
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;
Do we really need to set the disable_display here? on Gen 7 and 8 when
it is fused off, we were setting pipe_mask to 0. why that wont work
here?

INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

-Ram
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Ramalingam C]

On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> 
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;
Do we really need to set the disable_display here? on Gen 7 and 8 when
it is fused off, we were setting pipe_mask to 0. why that wont work
here?

INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

-Ram
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Jani Nikula]

On Wed, 23 Oct 2019, Ramalingam C <ramalingam.c@intel.com> wrote:
> On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
>> If all pipes are fused off it means that display is disabled, similar
>> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
>> that hardware will override the pipe output to a solid color, so
>> some display is there and maybe we would need to shutdown display
>> to save power, so setting disable_display = true, to keep consistent
>> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
>> 
>> In addition to have all pipes fused off, GEN/display 9 have the
>> bit 30 "Internal Display Disable", not sure if all pipes will be set
>> as unfused when this bit is set so handling both.
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Martin Peres <martin.peres@linux.intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>>  2 files changed, 21 insertions(+), 14 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 855db888516c..6e3ae6e9cbb8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7651,16 +7651,17 @@ enum {
>>  #define   MASK_WAKEMEM			(1 << 13)
>>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>>  
>> -#define SKL_DFSM			_MMIO(0x51000)
>> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
>> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
>> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
>> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
>> +#define SKL_DFSM				_MMIO(0x51000)
>> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
>> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
>> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
>> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>>  
>>  #define SKL_DSSM				_MMIO(0x51004)
>>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 85e480bdc673..8d6492afdd6a 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  			enabled_mask &= ~BIT(PIPE_D);
>>  
>>  		/*
>> -		 * At least one pipe should be enabled and if there are
>> -		 * disabled pipes, they should be the last ones, with no holes
>> -		 * in the mask.
>> +		 * If there are disabled pipes, they should be the last ones,
>> +		 * with no holes in the mask.
>>  		 */
>> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
>> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>>  				  enabled_mask);
>>  		else
>>  			info->pipe_mask = enabled_mask;
>> +
>> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
>> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
>> +			i915_modparams.disable_display = true;
>> +
>> +		if (!enabled_mask)
>> +			i915_modparams.disable_display = true;
> Do we really need to set the disable_display here? on Gen 7 and 8 when
> it is fused off, we were setting pipe_mask to 0. why that wont work
> here?
>
> INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

Indeed that's one of the problematic features of the patch; the
->pipe_mask won't reflect reality. But then INTEL_DISPLAY_ENABLED()
assumes you *do* have display...

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Jani Nikula]

On Wed, 23 Oct 2019, Ramalingam C <ramalingam.c@intel.com> wrote:
> On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
>> If all pipes are fused off it means that display is disabled, similar
>> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
>> that hardware will override the pipe output to a solid color, so
>> some display is there and maybe we would need to shutdown display
>> to save power, so setting disable_display = true, to keep consistent
>> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
>> 
>> In addition to have all pipes fused off, GEN/display 9 have the
>> bit 30 "Internal Display Disable", not sure if all pipes will be set
>> as unfused when this bit is set so handling both.
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Martin Peres <martin.peres@linux.intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>>  2 files changed, 21 insertions(+), 14 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 855db888516c..6e3ae6e9cbb8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7651,16 +7651,17 @@ enum {
>>  #define   MASK_WAKEMEM			(1 << 13)
>>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>>  
>> -#define SKL_DFSM			_MMIO(0x51000)
>> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
>> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
>> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
>> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
>> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
>> +#define SKL_DFSM				_MMIO(0x51000)
>> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
>> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
>> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
>> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
>> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
>> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
>> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>>  
>>  #define SKL_DSSM				_MMIO(0x51004)
>>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 85e480bdc673..8d6492afdd6a 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  			enabled_mask &= ~BIT(PIPE_D);
>>  
>>  		/*
>> -		 * At least one pipe should be enabled and if there are
>> -		 * disabled pipes, they should be the last ones, with no holes
>> -		 * in the mask.
>> +		 * If there are disabled pipes, they should be the last ones,
>> +		 * with no holes in the mask.
>>  		 */
>> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
>> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>>  				  enabled_mask);
>>  		else
>>  			info->pipe_mask = enabled_mask;
>> +
>> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
>> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
>> +			i915_modparams.disable_display = true;
>> +
>> +		if (!enabled_mask)
>> +			i915_modparams.disable_display = true;
> Do we really need to set the disable_display here? on Gen 7 and 8 when
> it is fused off, we were setting pipe_mask to 0. why that wont work
> here?
>
> INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

Indeed that's one of the problematic features of the patch; the
->pipe_mask won't reflect reality. But then INTEL_DISPLAY_ENABLED()
assumes you *do* have display...

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Souza, Jose]

On Wed, 2019-10-23 at 16:23 +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2019, Ramalingam C <ramalingam.c@intel.com> wrote:
> > On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> > > If all pipes are fused off it means that display is disabled,
> > > similar
> > > like we handle for GEN 7 and 8 right above but for GEN9+ spec
> > > says
> > > that hardware will override the pipe output to a solid color, so
> > > some display is there and maybe we would need to shutdown display
> > > to save power, so setting disable_display = true, to keep
> > > consistent
> > > to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> > > 
> > > In addition to have all pipes fused off, GEN/display 9 have the
> > > bit 30 "Internal Display Disable", not sure if all pipes will be
> > > set
> > > as unfused when this bit is set so handling both.
> > > 
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Martin Peres <martin.peres@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++-------
> > > ---
> > >  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
> > >  2 files changed, 21 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 855db888516c..6e3ae6e9cbb8 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7651,16 +7651,17 @@ enum {
> > >  #define   MASK_WAKEMEM			(1 << 13)
> > >  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
> > >  
> > > -#define SKL_DFSM			_MMIO(0x51000)
> > > -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> > > -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> > > -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> > > -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> > > -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> > > +#define SKL_DFSM				_MMIO(0x51000)
> > > +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > > +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> > > +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> > > +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> > > +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> > > +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> > >  
> > >  #define SKL_DSSM				_MMIO(0x51004)
> > >  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 85e480bdc673..8d6492afdd6a 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >  			enabled_mask &= ~BIT(PIPE_D);
> > >  
> > >  		/*
> > > -		 * At least one pipe should be enabled and if there are
> > > -		 * disabled pipes, they should be the last ones, with
> > > no holes
> > > -		 * in the mask.
> > > +		 * If there are disabled pipes, they should be the last
> > > ones,
> > > +		 * with no holes in the mask.
> > >  		 */
> > > -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask +
> > > 1))
> > > +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> > >  			DRM_ERROR("invalid pipe fuse configuration:
> > > enabled_mask=0x%x\n",
> > >  				  enabled_mask);
> > >  		else
> > >  			info->pipe_mask = enabled_mask;
> > > +
> > > +		if ((INTEL_GEN(dev_priv) == 9 &&
> > > !IS_GEMINILAKE(dev_priv)) &&
> > > +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> > > +			i915_modparams.disable_display = true;
> > > +
> > > +		if (!enabled_mask)
> > > +			i915_modparams.disable_display = true;
> > Do we really need to set the disable_display here? on Gen 7 and 8
> > when
> > it is fused off, we were setting pipe_mask to 0. why that wont work
> > here?
> > 
> > INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

Like said in the commit description, GEN9+ even when fused off the pipe
still outputs some solid color so in future we would need to shut it
down using INTEL_DISPLAY_ENABLED().

> 
> Indeed that's one of the problematic features of the patch; the
> ->pipe_mask won't reflect reality. But then INTEL_DISPLAY_ENABLED()
> assumes you *do* have display...

In the other comment that you left, you said that you don't like the
idea of change module parameters, so the other option would be add a
has_display to intel_device_info, what do you think?

> 
> BR,
> Jani.
> 
> 
> 
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Souza, Jose]

On Wed, 2019-10-23 at 16:23 +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2019, Ramalingam C <ramalingam.c@intel.com> wrote:
> > On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> > > If all pipes are fused off it means that display is disabled,
> > > similar
> > > like we handle for GEN 7 and 8 right above but for GEN9+ spec
> > > says
> > > that hardware will override the pipe output to a solid color, so
> > > some display is there and maybe we would need to shutdown display
> > > to save power, so setting disable_display = true, to keep
> > > consistent
> > > to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> > > 
> > > In addition to have all pipes fused off, GEN/display 9 have the
> > > bit 30 "Internal Display Disable", not sure if all pipes will be
> > > set
> > > as unfused when this bit is set so handling both.
> > > 
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Martin Peres <martin.peres@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++-------
> > > ---
> > >  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
> > >  2 files changed, 21 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 855db888516c..6e3ae6e9cbb8 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7651,16 +7651,17 @@ enum {
> > >  #define   MASK_WAKEMEM			(1 << 13)
> > >  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
> > >  
> > > -#define SKL_DFSM			_MMIO(0x51000)
> > > -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> > > -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> > > -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> > > -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> > > -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> > > +#define SKL_DFSM				_MMIO(0x51000)
> > > +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > > +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> > > +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> > > +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> > > +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> > > +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
> > >  
> > >  #define SKL_DSSM				_MMIO(0x51004)
> > >  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 85e480bdc673..8d6492afdd6a 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >  			enabled_mask &= ~BIT(PIPE_D);
> > >  
> > >  		/*
> > > -		 * At least one pipe should be enabled and if there are
> > > -		 * disabled pipes, they should be the last ones, with
> > > no holes
> > > -		 * in the mask.
> > > +		 * If there are disabled pipes, they should be the last
> > > ones,
> > > +		 * with no holes in the mask.
> > >  		 */
> > > -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask +
> > > 1))
> > > +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> > >  			DRM_ERROR("invalid pipe fuse configuration:
> > > enabled_mask=0x%x\n",
> > >  				  enabled_mask);
> > >  		else
> > >  			info->pipe_mask = enabled_mask;
> > > +
> > > +		if ((INTEL_GEN(dev_priv) == 9 &&
> > > !IS_GEMINILAKE(dev_priv)) &&
> > > +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> > > +			i915_modparams.disable_display = true;
> > > +
> > > +		if (!enabled_mask)
> > > +			i915_modparams.disable_display = true;
> > Do we really need to set the disable_display here? on Gen 7 and 8
> > when
> > it is fused off, we were setting pipe_mask to 0. why that wont work
> > here?
> > 
> > INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.

Like said in the commit description, GEN9+ even when fused off the pipe
still outputs some solid color so in future we would need to shut it
down using INTEL_DISPLAY_ENABLED().

> 
> Indeed that's one of the problematic features of the patch; the
> ->pipe_mask won't reflect reality. But then INTEL_DISPLAY_ENABLED()
> assumes you *do* have display...

In the other comment that you left, you said that you don't like the
idea of change module parameters, so the other option would be add a
has_display to intel_device_info, what do you think?

> 
> BR,
> Jani.
> 
> 
> 
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Re: [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Ramalingam C]

On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> 
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
As we are touching all of these anyway, we can add two char space
before the bit definitions as usual.

-Ram
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly

[Ramalingam C]

On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> 
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++----------
>  drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++----
>  2 files changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> -#define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define SKL_DFSM				_MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
As we are touching all of these anyway, we can add two char space
before the bit definitions as usual.

-Ram
> +#define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450		(2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5		(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE			(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE			(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE			(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE			(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
> -		 * At least one pipe should be enabled and if there are
> -		 * disabled pipes, they should be the last ones, with no holes
> -		 * in the mask.
> +		 * If there are disabled pipes, they should be the last ones,
> +		 * with no holes in the mask.
>  		 */
> -		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> +		if (enabled_mask && !is_power_of_2(enabled_mask + 1))
>  			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>  				  enabled_mask);
>  		else
>  			info->pipe_mask = enabled_mask;
> +
> +		if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> +		    (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> +			i915_modparams.disable_display = true;
> +
> +		if (!enabled_mask)
> +			i915_modparams.disable_display = true;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
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[PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers

[José Roberto de Souza]

The next patches are going to touch this registers so here already
fixing it for older registers and make it consistent with most of
the other registers in this file.

Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 746326784a4d..09cb43f4e976 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,15 +7663,15 @@ enum {
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
 #define SKL_DFSM			_MMIO(0x51000)
-#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
-#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
-#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
-#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
-#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
+#define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
+#define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
+#define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
+#define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
+#define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
+#define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
-- 
2.23.0

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[PATCH 2/5] drm/i915/display: Handle fused off HDCP

[José Roberto de Souza]

HDCP could be fused off, so not all GEN9+ platforms will support it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
 drivers/gpu/drm/i915/i915_pci.c           | 2 ++
 drivers/gpu/drm/i915/i915_reg.h           | 1 +
 drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h  | 1 +
 5 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e69fa34528df..f1f41ca8402b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
+	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
 }
 
 static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 04307e111f57..430da2d4082a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_preemption = 1, \
 	.display.has_csr = 1, \
 	.has_gt_uc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
 	.ddb_size = 896
 
@@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.display.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.display.has_fbc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_psr = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_csr = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09cb43f4e976..1317c0df76b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,6 +7663,7 @@ enum {
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
 #define SKL_DFSM			_MMIO(0x51000)
+#define   SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
 #define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 85e480bdc673..e7dd6092c105 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 				  enabled_mask);
 		else
 			info->pipe_mask = enabled_mask;
+
+		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
+			info->display.has_hdcp = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 78a383f63957..64e4f1923c68 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -139,6 +139,7 @@ enum intel_ppgtt_type {
 	func(has_dsb); \
 	func(has_fbc); \
 	func(has_gmch); \
+	func(has_hdcp); \
 	func(has_hotplug); \
 	func(has_ipc); \
 	func(has_modular_fia); \
-- 
2.23.0

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