From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20CD1C3F2D2 for ; Fri, 28 Feb 2020 13:38:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB0DF24699 for ; Fri, 28 Feb 2020 13:38:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB0DF24699 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83C4A6E197; Fri, 28 Feb 2020 13:38:01 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 110A56E197 for ; Fri, 28 Feb 2020 13:37:59 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Feb 2020 05:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,496,1574150400"; d="scan'208";a="227546594" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 28 Feb 2020 05:37:57 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 28 Feb 2020 15:37:56 +0200 Date: Fri, 28 Feb 2020 15:37:56 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Chris Wilson Message-ID: <20200228133756.GC13686@intel.com> References: <20200227193954.5585-1-ville.syrjala@linux.intel.com> <158287851663.19174.2013462831358055362@skylake-alporthouse-com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <158287851663.19174.2013462831358055362@skylake-alporthouse-com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH] drm/i915: Lock gmbus/aux mutexes while changing cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Feb 28, 2020 at 08:28:36AM +0000, Chris Wilson wrote: > Quoting Ville Syrjala (2020-02-27 19:39:54) > > From: Ville Syrj=E4l=E4 > > = > > gmbus/aux may be clocked by cdclk, thus we should make sure no > > transfers are ongoing while the cdclk frequency is being changed. > > We do that by simply grabbing all the gmbus/aux mutexes. No one > > else should be holding any more than one of those at a time so > > the lock ordering here shouldn't matter. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/d= rm/i915/display/intel_cdclk.c > > index 0741d643455b..f69bf4a4eb1c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -1868,6 +1868,9 @@ static void intel_set_cdclk(struct drm_i915_priva= te *dev_priv, > > const struct intel_cdclk_config *cdclk_conf= ig, > > enum pipe pipe) > > { > > + struct intel_encoder *encoder; > > + unsigned int aux_mutex_lockclass =3D 0; > > + > > if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) > > return; > > = > > @@ -1876,8 +1879,28 @@ static void intel_set_cdclk(struct drm_i915_priv= ate *dev_priv, > > = > > intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); > > = > > + /* > > + * Lock aux/gmbus while we change cdclk in case those > > + * functions use cdclk. Not all platforms/ports do, > > + * but we'll lock them all for simplicity. > > + */ > > + mutex_lock(&dev_priv->gmbus_mutex); > > + for_each_intel_dp(&dev_priv->drm, encoder) { > > + struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > > + > > + mutex_lock_nested(&intel_dp->aux.hw_mutex, > > + aux_mutex_lockclass++); > = > mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, &dev_priv->gmbus_mutex); > ? That does seems to work. Not sure what it means though since no docs and I was too lazy to read the code. Does it say "as long as we hold nest_lock the order doesn't matter"? -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx