From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 060E6C3F2D1 for ; Wed, 4 Mar 2020 18:31:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBCD32146E for ; Wed, 4 Mar 2020 18:31:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DBCD32146E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F6196EB54; Wed, 4 Mar 2020 18:31:31 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEFB36E0E7; Wed, 4 Mar 2020 18:31:29 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Mar 2020 10:31:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,514,1574150400"; d="scan'208";a="229415047" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 04 Mar 2020 10:31:25 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 04 Mar 2020 20:31:23 +0200 Date: Wed, 4 Mar 2020 20:31:23 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Manasi Navare Message-ID: <20200304183123.GG13686@intel.com> References: <20200303000859.29339-1-manasi.d.navare@intel.com> <20200303134212.GR13686@intel.com> <20200304173606.GA19311@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200304173606.GA19311@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Kazlauskas@freedesktop.org, dri-devel@lists.freedesktop.org, Nicholas Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Mar 04, 2020 at 09:36:06AM -0800, Manasi Navare wrote: > On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrj=E4l=E4 wrote: > > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse > > > the EDID's detailed descritors to obtain the adaptive sync monitor ra= nge. > > > Store this info as part fo drm_display_info so it can be used > > > across all drivers. > > > This part of the code is stripped out of amdgpu's function > > > amdgpu_dm_update_freesync_caps() to make it generic and be used > > > across all DRM drivers > > > = > > > v3: > > > * Remove the edid parsing restriction for just DP (Nicholas) > > > * Use drm_for_each_detailed_block (Ville) > > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > > > v2: > > > * Change vmin and vmax to use u8 (Ville) > > > * Dont store pixel clock since that is just a max dotclock > > > and not related to VRR mode (Manasi) > > > = > > > Cc: Ville Syrj=E4l=E4 > > > Cc: Harry Wentland > > > Cc: Clinton A Taylor > > > Cc: Kazlauskas, Nicholas > > > Signed-off-by: Manasi Navare > > > --- > > > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++= ++ > > > include/drm/drm_connector.h | 22 +++++++++++++++++++ > > > 2 files changed, 66 insertions(+) > > > = > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > > > index ad41764a4ebe..e3f152180b6b 100644 > > > --- a/drivers/gpu/drm/drm_edid.c > > > +++ b/drivers/gpu/drm/drm_edid.c > > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_conne= ctor *connector, > > > } > > > } > > > = > > > +static > > > +void get_adaptive_sync_range(struct detailed_timing *timing, > > > + void *info_adaptive_sync) > > > +{ > > > + struct drm_adaptive_sync_info *adaptive_sync =3D info_adaptive_sync; > > > + const struct detailed_non_pixel *data =3D &timing->data.other_data; > > > + const struct detailed_data_monitor_range *range =3D &data->data.ran= ge; > > > + > > > + if (data->type !=3D EDID_DETAIL_MONITOR_RANGE)a > > = > > is_display_descriptor() > = > Will change to use is_display_descriptor() > = > > = > > > + return; > > > + > > > + /* > > > + * Check for flag range limits only. If flag =3D=3D 1 then > > > + * no additional timing information provided. > > > + * Default GTF, GTF Secondary curve and CVT are not > > > + * supported > > > + */ > > > + if (range->flags !=3D 1) > > = > > Pls name the flags. > = > I dont see that we have any enum with the flag names, do you want me to d= efine them looking > at EDID spec? What else? -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx