From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34CC2C4332D for ; Thu, 19 Mar 2020 22:44:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 11B91207FC for ; Thu, 19 Mar 2020 22:44:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 11B91207FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FCEC6EA98; Thu, 19 Mar 2020 22:44:41 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 625826EA97; Thu, 19 Mar 2020 22:44:40 +0000 (UTC) IronPort-SDR: aZS+q3YQ09Fw05f/1UjQgiEvKmmLLovTmCBczr7lPvf/eImBME8r2IimV7Rxirag/EFBNj9FKa XNvKz58hDvvw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Mar 2020 15:44:39 -0700 IronPort-SDR: GtQMaXqyth5TKsZRlJ/Rg4I2JkwE4kwGgBSGsPZ+iFwbo7ert3QG4kPIBBjG9Bu2kX23h7CsjY R5S+b88CLwEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,573,1574150400"; d="scan'208";a="234324257" Received: from labuser-z97x-ud5h.jf.intel.com (HELO intel.com) ([10.165.21.211]) by orsmga007.jf.intel.com with ESMTP; 19 Mar 2020 15:44:39 -0700 Date: Thu, 19 Mar 2020 15:46:16 -0700 From: Manasi Navare To: Jani Nikula Message-ID: <20200319224615.GE11219@intel.com> References: <20200318063517.3844-1-manasi.d.navare@intel.com> <871rpoekc5.fsf@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <871rpoekc5.fsf@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [Intel-gfx] [PATCH 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Harry Wentland , dri-devel@lists.freedesktop.org, Nicholas Kazlauskas Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Mar 19, 2020 at 11:59:38AM +0200, Jani Nikula wrote: > On Tue, 17 Mar 2020, Manasi Navare wrote: > > DP sink device sets the Ignore MSA bit in its > > DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to > > ignore the MSA video timing paramaters and its ability to support > > seamless video timing change over a range of timing exposed by > > DisplayID and EDID. > > This is required for the sink to indicate that it is Adaptive sync > > capable. > > > > Cc: Jani Nikula > > Cc: Ville Syrj=E4l=E4 > > Cc: Harry Wentland > > Cc: Nicholas Kazlauskas > > Signed-off-by: Manasi Navare > > --- > > include/drm/drm_dp_helper.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index c6119e4c169a..ccd6e2e988b9 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dp= cd[DP_RECEIVER_CAP_SIZE]) > > DP_ALTERNATE_SCRAMBLER_RESET_CAP; > > } > > = > > +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ > > +static inline bool > > +drm_dp_sink_is_capable_without_timing_msa(const u8 dpcd[DP_RECEIVER_CA= P_SIZE]) > = > From the department of nitpicks, if you read the name of the function > aloud, what does it actually mean? > = > Is sink capable of *what*? As per the DP 1.4 spec, it says this indicates sink's ability to ignore MSA= video timing parameters to support seamless video timing change over range of timing exp= osed in DisplayID and legacy EDID. This query should occur before enabling dynamic video timing c= hange of incoming video stream without valid MSA video timing params. May be i rename it as: drm_dp_sink_capable_video_without_timing_msa() ? Manasi > = > BR, > Jani. > = > = > > +{ > > + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & > > + DP_MSA_TIMING_PAR_IGNORED; > > +} > > + > > /* > > * DisplayPort AUX channel > > */ > = > -- = > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx