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Wysocki" , linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org, Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Andy Shevchenko , Mika Westerberg , Len Brown Content-Type: multipart/mixed; boundary="===============0323334348==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============0323334348== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="/QKKmeG/X/bPShih" Content-Disposition: inline --/QKKmeG/X/bPShih Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Aug 30, 2020 at 02:57:44PM +0200, Hans de Goede wrote: > While looking into adding atomic-pwm support to the pwm-crc driver I > noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and > there is a clock-divider which divides this with a value between 1-128, > and there are 256 duty-cycle steps. >=20 > The pwm-crc code before this commit assumed that a clock-divider > setting of 1 means that the PWM output is running at 6 MHZ, if that > is true, where do these 256 duty-cycle steps come from? >=20 > This would require an internal frequency of 256 * 6 MHz =3D 1.5 GHz, that > seems unlikely for a PMIC which is using a silicon process optimized for > power-switching transistors. It is way more likely that there is an 8 > bit counter for the duty cycle which acts as an extra fixed divider > wrt the PWM output frequency. >=20 > The main user of the pwm-crc driver is the i915 GPU driver which uses it > for backlight control. Lets compare the PWM register values set by the > video-BIOS (the GOP), assuming the extra fixed divider is present versus > the PWM frequency specified in the Video-BIOS-Tables: >=20 > Device: PWM Hz set by BIOS PWM Hz specified in VBT > Asus T100TA 200 200 > Asus T100HA 200 200 > Lenovo Miix 2 8 23437 20000 > Toshiba WT8-A 23437 20000 >=20 > So as we can see if we assume the extra division by 256 then the register > values set by the GOP are an exact match for the VBT values, where as > otherwise the values would be of by a factor of 256. >=20 > This commit fixes the period / duty_cycle calculations to take the > extra division by 256 into account. >=20 > Reviewed-by: Andy Shevchenko > Signed-off-by: Hans de Goede > --- > Changes in v3: > - Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ d= efine > --- > drivers/pwm/pwm-crc.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Acked-by: Thierry Reding --/QKKmeG/X/bPShih Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9M23UACgkQ3SOs138+ s6FFYg/+Mtzc1XwV7Zl1w99FCSgZyIrsahQ4SvPhVAXHLByxVW0Sgfi/z9K/bDcB Fjw3E5MB0XL4UD9DWtdCKefCLe/5kIlbsS/LK7BPplf1GNfctSYQ72L5soS7HKrn vBjHnIr5ohFn/EGf3RWeLczkUoFVhfbMYFgor/H1FjXo5OeHQ3Fkr2AVPsnyIYXZ Iuc7iGLT8lI57IoxRlJ7ZKu0IXImzrN7YU4a+pfZ77fBAu3B9D9jom+L+U0E+E6q Y+ZBnaRVz13j6OSRMtfu13/kATzx1HgJZfjmMiimldrXbucWCovYXK2GWz8RJp5J YrXCFi8WdHdxB/JxDSYsswynJtRiSmGTjQmvxy6GYXZe8IvSB3VkpaTkQS5bzA65 QAYAclX3dnxT46eQ+yiNH4WEWlgL5gxsLeOMCvFWa5Lismv4q2gvxjBTF0RapKaD oncskpQfC4HlP1vQieYkUrYQUfAq+Gq2a6OU5qk0HES6N504YLAhS35xqHvWvT+9 QT50ulvZJVyUzZN9HgmMphXKi0jTeJ5dAZjdf8RbzIXD8hBlFJbObnPl6Xk2VRh2 kJSwxDm74OT4sD2IydJQQCBnOtf6MZ/HjfLa5M6UP34DyWKg5LTlUbBDjp5+cJcs jrZ53SdqyD8MbZ/0meG1wcRvneBbIEKkPtAkowDRt2wkQHEO6nc= =4Oyz -----END PGP SIGNATURE----- --/QKKmeG/X/bPShih-- --===============0323334348== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0323334348==--