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Wysocki" , linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org, Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Andy Shevchenko , Mika Westerberg , Len Brown Content-Type: multipart/mixed; boundary="===============1495371338==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============1495371338== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="BXr400anF0jyguTS" Content-Disposition: inline --BXr400anF0jyguTS Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Aug 30, 2020 at 02:57:45PM +0200, Hans de Goede wrote: > The CRC PWM controller has a clock-divider which divides the clock with > a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx > defines, this range maps to a register value of 0-127. >=20 > So after calculating the clock-divider we must subtract 1 to get the > register value, unless the requested frequency was so high that the > calculation has already resulted in a (rounded) divider value of 0. >=20 > Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which > corresponds to the max. divider value of 128 could have resulted in a > bug where the code would use 128 as divider-register value which would > have resulted in an actual divider value of 0 (and the enable bit being > set). A rounding error stopped this bug from actually happen. This > same rounding error means that after the subtraction of 1 it is impossible > to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow > setting a divider of 128 (register-value 127). >=20 > Reviewed-by: Andy Shevchenko > Signed-off-by: Hans de Goede > --- > Changes in v3: > - Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set > to reduce the amount of churn in the patch-set a bit > --- > drivers/pwm/pwm-crc.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) Acked-by: Thierry Reding --BXr400anF0jyguTS Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9M27UACgkQ3SOs138+ s6Gs7BAAkDVsNGuKpdYxyV/XBnq4T6ySPHcL3M15sN9QMC7UTr1DhcOGFHWlfC9E cJK7ctPCe74/xareIjriY3xTCumhIOj1dAYvFxJGiw4W6qzNG6bXUNrrn/QpGOTy tIUbrhj//YOgqwpzYvwwKbUjHtRRakOgAl6ayfXu1XggtVB2Tq/bf7wioyjNQGjy bFrN97KYyePQZ9dv9ig6/8Z4dsLaMNc1pcYSnOsixUewDxscC9rQYmtovoqyZTS2 AWSNnCzp0YZqVhVFssYArwzMiimxESmAfTqsc9L9D3vVj6EYiJoc9CYsX46nkmbr xeggxecSNtrGMSS8uce2krUt9KkqTTl8Li2tVtJZQ6N+jsEKEREnUISVJ7jvWCVJ ygTtZahw6Qx/aafFFaXjPoivcWc40QJS3obin8hUV452ktoX7p9DjWtHDbeiW8s/ wggeEy5ySja9kp1zzwz7Ijg3aW97wFvcAGHpGEpTCPXF4acWq6WbVLjWC3h+QQ9w II7rAObTNua3i+UDJ5JVS/bbxR9AwGMtYn3JwqLlXIUP7QvN8v8U8uCatj2Hg2Bd +C/jjZJeNM7TA8BayiZ9qUaXRjjD1V0cHM5h4GOSAQsBMA2emE8wY43PGwZCx3CW DgFi43ZSBldkZLZZQzm3CRXxWFWWdLv/k6rGHTy+B4Md1cqqIVw= =MFCA -----END PGP SIGNATURE----- --BXr400anF0jyguTS-- --===============1495371338== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1495371338==--