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Wysocki" , linux-acpi@vger.kernel.org, dri-devel@lists.freedesktop.org, Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Andy Shevchenko , Mika Westerberg , Len Brown Content-Type: multipart/mixed; boundary="===============0330254654==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============0330254654== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="svExV93C05KqedWb" Content-Disposition: inline --svExV93C05KqedWb Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Aug 30, 2020 at 02:57:46PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register >=20 > The BACKLIGHT_EN register at address 0x51 really controls a separate > output-only GPIO which is earmarked to be used as output connected to the > backlight-enable pin for LCD panels, this GPO is part of the PMIC's > "Display Panel Control Block." . This pin should probably be moved over > to a GPIO provider driver (and consumers modified accordingly), but that > is something for an(other) patch. >=20 > Enabling / disabling the actual PWM output is controlled by the > PWM_OUTPUT_ENABLE bit of the PWM0_CLK_DIV register. >=20 > As the comment in the old code already indicates we must disable the PWM > before we can change the clock divider. But the crc_pwm_disable() and > crc_pwm_enable() calls the old code make for this only change the > BACKLIGHT_EN register; and the value of that register does not matter for > changing the period / the divider. What does matter is that the > PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. >=20 > This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead > when changing the period, so that period changes actually work. >=20 > Note this fix will cause a significant behavior change on some devices > using the CRC PWM output to drive their backlight. Before the PWM would > always run with the output frequency configured by the BIOS at boot, now > the period time specified by the i915 driver will actually be honored. >=20 > Reviewed-by: Andy Shevchenko > Signed-off-by: Hans de Goede > --- > drivers/pwm/pwm-crc.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) Acked-by: Thierry Reding --svExV93C05KqedWb Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9M2+IACgkQ3SOs138+ s6E5KxAApXK34q3C3ieCWdzG1PdQ1k6JHm5UL/g7oRjpm8tKaVsZBkQUaG7zwYuQ jkG6bBRDtF/X2CLcncU4Dw6UYGzTcmh6byoYAkBggVgVVK789jq60jB87snEW8Wd DhnT5eO/XWiJmBT02roJYDpo02kmysXPJfP4224Be6aRfxaD0DVCpa4LAKFHYeSk Pu/u1ydColi8w2mgMb+MKj2bB8QNsaBTrG6N/BI1IwNVsUkerOQ9EjnmVy2f9b2N 0eWgby389QqZ242pVrWs8o6WOe/Ju+2Sq7POWLTBmiab3u2ngxPRRkiUDr2ZI9+l Auz8Fa8n1aOHRvIggyr/5oXH6UtqmcxIqWLL+D037/zSaWCmZsr09fLA8K+ZHpYg ymffnKrABbhMZciobvNrfbxQXGZQp2xp1oAqTAv0qrtuILYneL/sqA1vn24eNsK1 j1dDf5oDGrCij0ySeFx0dnKeEPfdRwGGC5fauVUoFwAxGonUFwiAcT1Ad6fOJvNG +w45vNKkn41+xl4FcpdmrEZRjogheai96ZMJVo/bJMnFawIxG7N9mDLMEH5biU3D U1YcTHdu5i2MYvALntwgOJ5kgRkjNIwbXRKqXNStimcmPq3I9pfaeFjkyvBiHTbt FChyPvjlvqBIqizaoy8CEQRPXRZ9eRQWCI90n3ax64irhCtkGdY= =bb6R -----END PGP SIGNATURE----- --svExV93C05KqedWb-- --===============0330254654== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0330254654==--