[Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

Imre Deak
2020-09-29T00:29:36Z

This patchset replaces [1], adding also a workaround for TGL BIOSes that
don't apply Display WA #22010492432. The first patch fixes an incorrect
BIOS PDIV programming I noticed while testing this patchset on an ASUS/SKL
system.

[1] https://patchwork.freedesktop.org/series/79486/

Imre Deak (5):
drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
drm/i915: Factor out skl_wrpll_calc_freq()
drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt.
hard-coded PLL freqs
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock
drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL
programming

drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 232 ++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 4 +
2 files changed, 161 insertions(+), 75 deletions(-)

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2.25.1