From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AE95C4363A for ; Tue, 6 Oct 2020 00:35:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4110A2074A for ; Tue, 6 Oct 2020 00:35:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4110A2074A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D832F6E203; Tue, 6 Oct 2020 00:35:50 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90E466E203 for ; Tue, 6 Oct 2020 00:35:49 +0000 (UTC) IronPort-SDR: jTUT9/YYuiOK1YFjGXvtJVnE+zYf18Om/x66M8RCGf7VuqD2bV+zGEC5XlsIpyVXoUbA8IuzS/ OEN81T+WuqSA== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="181733010" X-IronPort-AV: E=Sophos;i="5.77,341,1596524400"; d="scan'208";a="181733010" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 05 Oct 2020 17:35:48 -0700 IronPort-SDR: 7zU+jH1YRL56NWj412c//5EhcEcVmdfpih0XXcKL1QyhFr7CRMUcyPHZwuxRiJwQDBYNdyW+v5 /nBKufg75GGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,341,1596524400"; d="scan'208";a="417747787" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 05 Oct 2020 16:39:21 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 06 Oct 2020 02:39:13 +0300 Date: Tue, 6 Oct 2020 02:39:13 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Imre Deak Message-ID: <20201005233913.GQ6112@intel.com> References: <20201003001846.1271151-1-imre.deak@intel.com> <20201003001846.1271151-5-imre.deak@intel.com> <20201005203055.GM6112@intel.com> <20201005204617.GC1378377@ideak-desk.fi.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201005204617.GC1378377@ideak-desk.fi.intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Oct 05, 2020 at 11:46:17PM +0300, Imre Deak wrote: > On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrj=E4l=E4 wrote: > > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > > Atm, if a full modeset is performed during the initial modeset the li= nk > > > training will happen with uninitialized max DP rate and lane count. M= ake > > > sure the corresponding encoder state is initialized by adding an enco= der > > > hook called during driver init and system resume. > > > = > > > A better alternative would be to store all states in the CRTC state a= nd > > > make this state available for the link re-training code. Also instead= of > > > the DPCD read in the hook there should be really a proper sink HW > > > readout in place. Both of these require a bigger rework, so for now o= pting > > > for this minimal fix to make at least full initial modesets work. > > > = > > > The patch is based on > > > https://patchwork.freedesktop.org/patch/101473/?series=3D10354&rev=3D3 > > > = > > > Cc: Ville Syrj=E4l=E4 > > > Signed-off-by: Imre Deak > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++ > > > drivers/gpu/drm/i915/display/intel_display.c | 4 +++ > > > .../drm/i915/display/intel_display_types.h | 7 +++++ > > > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++= ++ > > > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > > > 6 files changed, 62 insertions(+) > > > = > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/d= rm/i915/display/intel_ddi.c > > > index 4e54c55ec99f..a0805260b224 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder= *encoder, > > > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); > > > } > > > = > > > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state) > > > +{ > > > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) > > > + intel_dp_sanitize_state(encoder, crtc_state); > > > +} > > = > > I think we usually use 'sanitize' to mean "hw state is garbage -> must > > take steps to sanitize it". This one is just filling in our intel_dp > > sidechannel state. So the name isn't super consistnet with existing > > practies. > = > It is called during init/resume time when encoders are sanitized as > well, but yea it's a separate step from HW readout. So I can rename it > for instance (back) to sync_state, or any better idea? All I know is that I suck at naming things. > = > > = > > > + > > > static bool intel_ddi_initial_fastset_check(struct intel_encoder *en= coder, > > > struct intel_crtc_state *crtc_state) > > > { > > > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *de= v_priv, enum port port) > > > encoder->update_pipe =3D intel_ddi_update_pipe; > > > encoder->get_hw_state =3D intel_ddi_get_hw_state; > > > encoder->get_config =3D intel_ddi_get_config; > > > + encoder->sanitize_state =3D intel_ddi_sanitize_state; > > > encoder->initial_fastset_check =3D intel_ddi_initial_fastset_check; > > > encoder->suspend =3D intel_dp_encoder_suspend; > > > encoder->get_power_domains =3D intel_ddi_get_power_domains; > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/g= pu/drm/i915/display/intel_display.c > > > index 31be63225b10..e61311ee8b8c 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(s= truct drm_device *dev) > > > = > > > encoder->base.crtc =3D &crtc->base; > > > encoder->get_config(encoder, crtc_state); > > > + if (encoder->sanitize_state) > > > + encoder->sanitize_state(encoder, crtc_state); > > > } else { > > > encoder->base.crtc =3D NULL; > > > + if (encoder->sanitize_state) > > > + encoder->sanitize_state(encoder, NULL); > > = > > I wonder if we should even bother calling it in this case. > = > Yes, it would be just a nop atm, and can't think what state would need > to be updated, so will remove it. > = > > = > > > } > > > = > > > drm_dbg_kms(&dev_priv->drm, > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/dri= vers/gpu/drm/i915/display/intel_display_types.h > > > index 5297b2f08ff9..b2b458144f5a 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -188,6 +188,13 @@ struct intel_encoder { > > > void (*get_config)(struct intel_encoder *, > > > struct intel_crtc_state *pipe_config); > > > = > > > + /* > > > + * Optional hook called during init/resume to sanitize any state > > > + * stored in the encoder (eg. DP link parameters). > > > + */ > > > + void (*sanitize_state)(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state); > > > + > > > /* > > > * Optional hook, returning true if this encoder allows a fastset > > > * during the initial commit, false otherwise. > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/dr= m/i915/display/intel_dp.c > > > index df5277c2b9ba..9b6fe3b3b5b2 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_e= ncoder *encoder, > > > } > > > } > > > = > > > +static bool > > > +intel_dp_get_dpcd(struct intel_dp *intel_dp); > > > + > > > +/** > > > + * intel_dp_sanitize_state - sanitize the encoder state during init/= resume > > > + * @encoder: intel encoder to sanitize > > > + * @crtc_state: state for the CRTC connected to the encoder > > > + * > > > + * Sanitize any state stored in the encoder during driver init and s= ystem > > > + * resume. > > > + */ > > > +void intel_dp_sanitize_state(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state) > > > +{ > > > + struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > > > + > > > + if (!crtc_state) > > > + return; > > > + > > > + /* > > > + * Don't clobber DPCD if it's been already read out during output > > > + * setup (eDP) or detect. > > > + */ > > > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd))) > > > + intel_dp_get_dpcd(intel_dp); > > > + > > > + intel_dp->max_link_lane_count =3D intel_dp_max_common_lane_count(in= tel_dp); > > > + intel_dp->max_link_rate =3D intel_dp_max_common_rate(intel_dp); > > > +} > > > + > > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, > > > struct intel_crtc_state *crtc_state) > > > { > > > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev= _priv, > > > intel_encoder->compute_config =3D intel_dp_compute_config; > > > intel_encoder->get_hw_state =3D intel_dp_get_hw_state; > > > intel_encoder->get_config =3D intel_dp_get_config; > > > + intel_encoder->sanitize_state =3D intel_dp_sanitize_state; > > > intel_encoder->initial_fastset_check =3D intel_dp_initial_fastset_c= heck; > > > intel_encoder->update_pipe =3D intel_panel_update_backlight; > > > intel_encoder->suspend =3D intel_dp_encoder_suspend; > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/dr= m/i915/display/intel_dp.h > > > index 977585aea3c8..1ab741e0be67 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > > > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port = *dig_port, > > > = > > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, > > > struct intel_crtc_state *crtc_state); > > > +void intel_dp_sanitize_state(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state); > > > = > > > #endif /* __INTEL_DP_H__ */ > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gp= u/drm/i915/display/intel_dp_mst.c > > > index e948aacbd4ab..0831d1ee7978 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct i= ntel_encoder *encoder, > > > intel_ddi_get_config(&dig_port->base, pipe_config); > > > } > > > = > > > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state) > > > +{ > > > + struct intel_dp_mst_encoder *intel_mst =3D enc_to_mst(encoder); > > > + struct intel_digital_port *dig_port =3D intel_mst->primary; > > > + > > > + return intel_dp_sanitize_state(&dig_port->base, crtc_state); > > > +} > > > + > > > static bool intel_dp_mst_initial_fastset_check(struct intel_encoder = *encoder, > > > struct intel_crtc_state *crtc_state) > > > { > > > @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_dig= ital_port *dig_port, enum pipe > > > intel_encoder->enable =3D intel_mst_enable_dp; > > > intel_encoder->get_hw_state =3D intel_dp_mst_enc_get_hw_state; > > > intel_encoder->get_config =3D intel_dp_mst_enc_get_config; > > > + intel_encoder->sanitize_state =3D intel_dp_mst_sync_state; > > > intel_encoder->initial_fastset_check =3D intel_dp_mst_initial_fasts= et_check; > > > = > > > return intel_mst; > > > -- = > > > 2.25.1 > > = > > -- = > > Ville Syrj=E4l=E4 > > Intel -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx