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d="scan'208";a="524620509" Received: from genxfsim-desktop.iind.intel.com (HELO intel.com) ([10.223.74.178]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2020 02:10:43 -0700 Date: Tue, 27 Oct 2020 14:27:05 +0530 From: Anshuman Gupta To: "Shankar, Uma" Message-ID: <20201027085704.GG29526@intel.com> References: <20201023122112.15265-1-anshuman.gupta@intel.com> <20201023122112.15265-15-anshuman.gupta@intel.com> <3b7df974286b4497ba31ad4a554062e0@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3b7df974286b4497ba31ad4a554062e0@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "seanpaul@chromium.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 2020-10-27 at 12:41:41 +0530, Shankar, Uma wrote: > > > > -----Original Message----- > > From: Anshuman Gupta > > Sent: Friday, October 23, 2020 5:51 PM > > To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > > Cc: seanpaul@chromium.org; Nikula, Jani ; C, > > Ramalingam ; Li, Juston ; > > Shankar, Uma ; Gupta, Anshuman > > > > Subject: [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register > > > > Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS > > and HDCP2_AUTH_STREAM register in i915_reg header. > > > > Cc: Ramalingam C > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 86a9a5145e47..cb6ec2c241f2 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9882,6 +9882,7 @@ enum skl_power_gate { > > _PORTD_HDCP2_BASE, \ > > _PORTE_HDCP2_BASE, \ > > _PORTF_HDCP2_BASE) + (x)) > > + > > #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) > > #define _TRANSA_HDCP2_AUTH 0x66498 > > #define _TRANSB_HDCP2_AUTH 0x66598 > > @@ -9921,6 +9922,35 @@ enum skl_power_gate { > > TRANS_HDCP2_STATUS(trans) : \ > > PORT_HDCP2_STATUS(port)) > > > > +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, > > 0xC0) > > +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 > > +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 > > +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ > > + > > _TRANSA_HDCP2_STREAM_STATUS, \ > > + > > _TRANSB_HDCP2_STREAM_STATUS) > > +#define STREAM_ENCRYPTION_STATUS BIT(31) > > +#define STREAM_TYPE_STATUS BIT(30) > > +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ > > + (INTEL_GEN(dev_priv) >= 12 ? \ > > + TRANS_HDCP2_STREAM_STATUS(trans) : > > \ > > + PORT_HDCP2_STREAM_STATUS(port)) > > + > > +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 > > +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 > > +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ > > + > > _PORTA_HDCP2_AUTH_STREAM, \ > > + > > _PORTB_HDCP2_AUTH_STREAM) > > Should it also not be defined as the other counterparts for pre Gen12. It has already been defined with Gen12 and Pre Gen12 annotation below HDCP2_AUTH_STREAM should TRANS_HDCP2_AUTH_STREAM for Gen12 and PORT_HDCP2_AUTH_STREAM for pre Gen12. Is it something else u find it is missing ? Thanks, Anshuman. > > > +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 > > +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 > > +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ > > + > > _TRANSA_HDCP2_AUTH_STREAM, \ > > + > > _TRANSB_HDCP2_AUTH_STREAM) > > +#define AUTH_STREAM_TYPE BIT(31) > > +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ > > + (INTEL_GEN(dev_priv) >= 12 ? \ > > + TRANS_HDCP2_AUTH_STREAM(trans) : \ > > + PORT_HDCP2_AUTH_STREAM(port)) > > + > > /* Per-pipe DDI Function Control */ > > #define _TRANS_DDI_FUNC_CTL_A 0x60400 > > #define _TRANS_DDI_FUNC_CTL_B 0x61400 > > -- > > 2.26.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx