From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5032C63697 for ; Thu, 26 Nov 2020 17:44:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59F1A207BC for ; Thu, 26 Nov 2020 17:44:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 59F1A207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DE4689E5B; Thu, 26 Nov 2020 17:44:33 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 717E66E9B0 for ; Thu, 26 Nov 2020 17:44:32 +0000 (UTC) IronPort-SDR: NVSeXlBioHUJWOpa+xPQfsus4a1AGybUAPuKGjwZtL43iv/Y0u/vwo0fy6lIrS0UH0dnUk5xoR bQQ0n7WGzlrg== X-IronPort-AV: E=McAfee;i="6000,8403,9817"; a="160083428" X-IronPort-AV: E=Sophos;i="5.78,372,1599548400"; d="scan'208";a="160083428" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2020 09:44:31 -0800 IronPort-SDR: bLc5dKdMUt5wu7bggUDpPiVrxcCiEW+DEWH9X6Mugnvaw3scFi4p2FiBtjxw3N9R4CqU4I2cc8 f39B7VwePnGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,372,1599548400"; d="scan'208";a="403686536" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 26 Nov 2020 09:44:29 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 26 Nov 2020 19:44:27 +0200 Date: Thu, 26 Nov 2020 19:44:27 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Uma Shankar Message-ID: <20201126174427.GK6112@intel.com> References: <20201126081445.29759-1-uma.shankar@intel.com> <20201126081445.29759-10-uma.shankar@intel.com> <20201126163202.GI6112@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201126163202.GI6112@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [v11 09/13] drm/i915/display: Implement infoframes readback for LSPCON X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Nov 26, 2020 at 06:32:02PM +0200, Ville Syrj=E4l=E4 wrote: > On Thu, Nov 26, 2020 at 01:44:41PM +0530, Uma Shankar wrote: > > Implemented Infoframes enabled readback for LSPCON devices. > > This will help align the implementation with state readback > > infrastructure. > > = > > v2: Added proper bitmask of enabled infoframes as per Ville's > > recommendation. > > = > > v3: Added pcon specific infoframe types instead of using the HSW > > one's, as recommended by Ville. > > = > > v4: Addressed Ville's review comment by adding HDMI infoframe > > versions directly instead of DIP wrappers. > > = > > Signed-off-by: Uma Shankar > > --- > > drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++- > > 1 file changed, 55 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/= drm/i915/display/intel_lspcon.c > > index 1d3dffade168..4f3c4943e918 100644 > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > @@ -574,11 +574,64 @@ void lspcon_set_infoframes(struct intel_encoder *= encoder, > > buf, ret); > > } > > = > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *= aux) > > +{ > > + int ret; > > + u32 val =3D 0; > > + u16 reg =3D LSPCON_MCA_AVI_IF_CTRL; > > + > > + ret =3D drm_dp_dpcd_read(aux, reg, &val, 1); > > + if (ret < 0) { > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > + return false; > > + } > > + > > + return val & LSPCON_MCA_AVI_IF_KICKOFF; > > +} > > + > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_au= x *aux) > > +{ > > + int ret; > > + u32 val =3D 0; > > + u16 reg =3D LSPCON_PARADE_AVI_IF_CTRL; > > + > > + ret =3D drm_dp_dpcd_read(aux, reg, &val, 1); > > + if (ret < 0) { > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > + return false; > > + } > > + > > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; > > +} > > + > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > const struct intel_crtc_state *pipe_config) > > { > > - /* FIXME actually read this from the hw */ > > - return 0; > > + struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > > + struct intel_lspcon *lspcon =3D enc_to_intel_lspcon(encoder); > > + struct drm_i915_private *dev_priv =3D to_i915(encoder->base.dev); > > + bool infoframes_enabled; > > + u32 val =3D 0; > > + u32 mask, tmp; > > + > > + if (lspcon->vendor =3D=3D LSPCON_VENDOR_MCA) > > + infoframes_enabled =3D _lspcon_read_avi_infoframe_enabled_mca(&intel= _dp->aux); > > + else > > + infoframes_enabled =3D _lspcon_read_avi_infoframe_enabled_parade(&in= tel_dp->aux); > > + > > + if (infoframes_enabled) > > + val |=3D intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); > > + > > + if (lspcon->hdr_supported) { > > + tmp =3D intel_de_read(dev_priv, > > + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); > > + mask =3D VIDEO_DIP_ENABLE_GMP_HSW; > > + > > + if (tmp & mask) > > + val |=3D intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADAT= A); > > + } > > + > > + return val; > > } > = > This seem broken until patch 10 which avoids the Actually, make that patch 11 > remapping from DIP bits to the index. With some reordering > of the patches this seems good. > = > Reviewed-by: Ville Syrj=E4l=E4 > > = > > void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) > > -- = > > 2.26.2 > = > -- = > Ville Syrj=E4l=E4 > Intel -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx