From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [v12 11/15] drm/i915/lspcon: Create separate infoframe_enabled helper
Date: Fri, 27 Nov 2020 02:33:10 +0530 [thread overview]
Message-ID: <20201126210314.7882-12-uma.shankar@intel.com> (raw)
In-Reply-To: <20201126210314.7882-1-uma.shankar@intel.com>
Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
Create a separate mechanism for lspcon compared to HDMI in order to
address the same and ensure future scalability.
v2: Streamlined this as per Ville's suggestions, making sure that
HDMI infoframe versions are directly returned instead of a redundant
and confusing DIP overhead.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_lspcon.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 92940a0c5ef8..48da5dc59939 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4583,6 +4583,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
u32 temp, flags = 0;
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
@@ -4657,9 +4658,12 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
pipe_config->fec_enable);
}
- pipe_config->infoframes.enable |=
- intel_hdmi_infoframes_enabled(encoder, pipe_config);
-
+ if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
+ pipe_config->infoframes.enable |=
+ intel_lspcon_infoframes_enabled(encoder, pipe_config);
+ else
+ pipe_config->infoframes.enable |=
+ intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 592c19deba00..303f23d35020 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -30,6 +30,7 @@
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_lspcon.h"
+#include "intel_hdmi.h"
/* LSPCON OUI Vendor ID(signatures) */
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
@@ -601,6 +602,14 @@ bool lspcon_init(struct intel_digital_port *dig_port)
return true;
}
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ return dig_port->infoframes_enabled(encoder, pipe_config);
+}
+
void lspcon_resume(struct intel_digital_port *dig_port)
{
struct intel_lspcon *lspcon = &dig_port->lspcon;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 42ccb21c908f..44aa6bc38512 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -33,6 +33,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state);
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config);
+u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
void hsw_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
--
2.26.2
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next prev parent reply other threads:[~2020-11-26 20:30 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-26 21:02 [Intel-gfx] [v12 00/15] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 01/15] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 02/15] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 03/15] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 04/15] drm/i915/display: Fixes quantization range for YCbCr output Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 05/15] drm/i915/display: Add a WARN for invalid output range and format Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 06/15] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-11-27 14:27 ` [Intel-gfx] [v13 " Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 07/15] drm/i915: Split intel_attach_colorspace_property() into HDMI vs. DP variants Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 08/15] drm/i915/display: Enable colorspace programming for LSPCON devices Uma Shankar
2020-11-27 13:45 ` Ville Syrjälä
2020-11-27 14:03 ` Shankar, Uma
2020-11-27 14:28 ` [Intel-gfx] [v13 " Uma Shankar
2020-11-30 19:51 ` Ville Syrjälä
2020-11-30 20:17 ` Shankar, Uma
2020-11-26 21:03 ` [Intel-gfx] [v12 09/15] drm/i915/display: Nuke bogus lspcon check Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 10/15] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-11-26 21:03 ` Uma Shankar [this message]
2020-11-27 14:55 ` [Intel-gfx] [v12 11/15] drm/i915/lspcon: Create separate infoframe_enabled helper Ville Syrjälä
2020-11-30 12:16 ` Shankar, Uma
2020-11-26 21:03 ` [Intel-gfx] [v12 12/15] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 13/15] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-11-26 21:03 ` [Intel-gfx] [v12 14/15] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-11-27 14:52 ` Ville Syrjälä
2020-11-30 12:35 ` Shankar, Uma
2020-11-26 21:03 ` [Intel-gfx] [v12 15/15] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-11-30 11:13 ` Shashank Sharma
2020-12-01 20:47 ` Shankar, Uma
2020-12-02 4:47 ` Shashank Sharma
2020-11-27 7:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev12) Patchwork
2020-11-27 7:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-27 8:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-27 9:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-27 16:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev14) Patchwork
2020-11-27 16:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-27 17:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-27 18:53 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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