From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8651C63798 for ; Fri, 27 Nov 2020 14:31:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8976720B1F for ; Fri, 27 Nov 2020 14:31:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8976720B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95EE06EDF4; Fri, 27 Nov 2020 14:31:08 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B3766EDF2; Fri, 27 Nov 2020 14:31:07 +0000 (UTC) IronPort-SDR: pHheU0FNQ0N55zp23On/FLa+BLayFtAw63si0GG44fesnvfw0mhvF0ZfCQ9axXjKGg3UI3fad8 nq6oIDHbeUUg== X-IronPort-AV: E=McAfee;i="6000,8403,9817"; a="151655664" X-IronPort-AV: E=Sophos;i="5.78,374,1599548400"; d="scan'208";a="151655664" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2020 06:31:06 -0800 IronPort-SDR: er6SrHf20zoATrwQlbgKTbC5Q4j+akiB7r8eXJiIdhFhlFx1o1MdR+Hgpug2i0o55jiC+eO2ra XeK0TljGWrIQ== X-IronPort-AV: E=Sophos;i="5.78,374,1599548400"; d="scan'208";a="548063594" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2020 06:31:04 -0800 Date: Fri, 27 Nov 2020 16:31:00 +0200 From: Imre Deak To: intel-gfx@lists.freedesktop.org, Jani Nikula , Daniel Vetter Message-ID: <20201127143100.GB2144692@ideak-desk.fi.intel.com> References: <20201123182631.1740781-1-imre.deak@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201123182631.1740781-1-imre.deak@intel.com> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: Rafael Antognolli , Kalyan Kondapally , Nanley Chery , Dhinakaran Pandiyan , dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Daniel, Jani, is it ok to merge this patch along with 2/2 via the i915 tree? --Imre On Mon, Nov 23, 2020 at 08:26:30PM +0200, Imre Deak wrote: > From: Radhakrishna Sripada > > Gen12 display can decompress surfaces compressed by render engine with > Clear Color, add a new modifier as the driver needs to know the surface > was compressed by render engine. > > V2: Description changes as suggested by Rafael. > V3: Mention the Clear Color size of 64 bits in the comments(DK) > v4: Fix trailing whitespaces > v5: Explain Clear Color in the documentation. > v6: Documentation Nitpicks(Nanley) > > Cc: Ville Syrjala > Cc: Dhinakaran Pandiyan > Cc: Kalyan Kondapally > Cc: Rafael Antognolli > Cc: Nanley Chery > Signed-off-by: Radhakrishna Sripada > Signed-off-by: Imre Deak > --- > include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index ca48ed0e6bc1..0a1b2c4c4bee 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -527,6 +527,25 @@ extern "C" { > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) > > +/* > + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render > + * compression. > + * > + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear > + * and at index 1. The clear color is stored at index 2, and the pitch should > + * be ignored. The clear color structure is 256 bits. The first 128 bits > + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > + * by 32 bits. The raw clear color is consumed by the 3d engine and generates > + * the converted clear color of size 64 bits. The first 32 bits store the Lower > + * Converted Clear Color value and the next 32 bits store the Higher Converted > + * Clear Color value when applicable. The Converted Clear Color values are > + * consumed by the DE. The last 64 bits are used to store Color Discard Enable > + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line > + * corresponds to an area of 4x1 tiles in the main surface. The main surface > + * pitch is required to be a multiple of 4 tile widths. > + */ > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > * > -- > 2.25.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx