From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required
Date: Mon, 30 Nov 2020 14:46:45 +0530 [thread overview]
Message-ID: <20201130091646.25576-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20201130091646.25576-1-anshuman.gupta@intel.com>
Reading backlight status from PPS register doesn't require
AUX power on the platform which has South Display Engine on PCH.
It invokes a unnecessary power well enable/disable noise.
optimize it wherever is possible.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++--
1 file changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3896d08c4177..37371aa5f7c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -892,6 +892,47 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
return 0;
}
+/*
+ * Platform with PCH based SDE doesn't require to enable AUX power
+ * for simple PPS register access like whether backlight is enabled.
+ * use pch_pps_lock()/pch_pps_unlock() wherever we don't require
+ * aux power to avoid unnecessary power well enable/disable back
+ * and forth.
+ */
+static intel_wakeref_t
+pch_pps_lock(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_wakeref_t wakeref;
+
+ if (!HAS_PCH_SPLIT(dev_priv))
+ wakeref = intel_display_power_get(dev_priv,
+ intel_aux_power_domain(dp_to_dig_port(intel_dp)));
+ else
+ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+
+ mutex_lock(&dev_priv->pps_mutex);
+
+ return wakeref;
+}
+
+static intel_wakeref_t
+pch_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ mutex_unlock(&dev_priv->pps_mutex);
+
+ if (!HAS_PCH_SPLIT(dev_priv))
+ intel_display_power_put(dev_priv,
+ intel_aux_power_domain(dp_to_dig_port(intel_dp)),
+ wakeref);
+ else
+ intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+
+ return 0;
+}
+
#define with_pps_lock(dp, wf) \
for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
@@ -3449,8 +3490,10 @@ static void intel_edp_backlight_power(struct intel_connector *connector,
bool is_enabled;
is_enabled = false;
- with_pps_lock(intel_dp, wakeref)
- is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
+ wakeref = pch_pps_lock(intel_dp);
+ is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
+ pch_pps_unlock(intel_dp, wakeref);
+
if (is_enabled == enable)
return;
--
2.26.2
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next prev parent reply other threads:[~2020-11-30 9:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta
2020-11-30 9:16 ` Anshuman Gupta [this message]
2020-11-30 9:16 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Anshuman Gupta
2020-11-30 15:28 ` Imre Deak
2020-11-30 16:16 ` Anshuman Gupta
2020-12-04 8:10 ` Anshuman Gupta
2020-12-04 15:51 ` Ville Syrjälä
2020-12-07 7:57 ` Anshuman Gupta
2020-12-08 9:11 ` Anshuman Gupta
2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork
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