From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78237C433FE for ; Mon, 7 Dec 2020 00:22:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1AE5C206B7 for ; Mon, 7 Dec 2020 00:22:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1AE5C206B7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DBFB6E544; Mon, 7 Dec 2020 00:22:12 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 54CBC6E550 for ; Mon, 7 Dec 2020 00:22:10 +0000 (UTC) IronPort-SDR: By13QJ0modaxJ58t9K+rjmcO1Os1Nv87JDtkLX0pacQ2p1C7f3f2nzLyqyAgt0apatHxqapW2N qfnsnoHqtlvQ== X-IronPort-AV: E=McAfee;i="6000,8403,9827"; a="191889198" X-IronPort-AV: E=Sophos;i="5.78,398,1599548400"; d="scan'208";a="191889198" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2020 16:22:08 -0800 IronPort-SDR: DqOZ9Gm5jCCJIXPxoOP4l9gnc7aJAf4+85MxDyqFU3QnBbPFfANsMjdjKdTtdeKDTEX4KJfo2m iWlNCc6Ba6tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,398,1599548400"; d="scan'208";a="369586442" Received: from sean-virtualbox.fm.intel.com ([10.105.158.96]) by fmsmga002.fm.intel.com with ESMTP; 06 Dec 2020 16:22:08 -0800 From: "Huang, Sean Z" To: Intel-gfx@lists.freedesktop.org Date: Sun, 6 Dec 2020 16:21:28 -0800 Message-Id: <20201207002134.13731-11-sean.z.huang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201207002134.13731-1-sean.z.huang@intel.com> References: <20201207002134.13731-1-sean.z.huang@intel.com> Subject: [Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Teardown is triggered when the display topology changes and no long meets the secure playback requirement, and hardware trashes all the encryption keys for display. So as a result, PXP should handle such case and terminate the type0 sessions, which including arb session Signed-off-by: Huang, Sean Z --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +- drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 + drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 207 ++++++++++++++++++++++++ drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 17 ++ 4 files changed, 232 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 10f4b1de07c4..48a0eb16f1d9 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -68,14 +68,18 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask) static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915) { + int ret; + mutex_lock(&i915->pxp.ctx->ctx_mutex); i915->pxp.ctx->global_state_attacked = true; i915->pxp.ctx->flag_display_hm_surface_keys = false; + ret = intel_pxp_sm_terminate_all_active_sessions(i915, SESSION_TYPE_TYPE0); + mutex_unlock(&i915->pxp.ctx->ctx_mutex); - return 0; + return ret; } static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index e5f6e2b1bdfd..425cafe24392 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -15,6 +15,9 @@ #define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \ &(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions) +#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \ + MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS) + #define MAX_TYPE0_SESSIONS 16 #define MAX_TYPE1_SESSIONS 6 diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c index c88243e02a3c..f8bb5248247f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c @@ -581,6 +581,213 @@ int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int ses return -EINVAL; } +static int add_pxp_prolog(struct drm_i915_private *i915, u32 *cmd, int session_type, + int session_index) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_prolog = cmd; + const int cmd_prolog_size_in_dw = 10; + + if (!cmd) + return cmd_prolog_size_in_dw; + + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_FLUSH_DW - pxp off */ + *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */ + *cmd_prolog++ = 0; /* DW1 */ + *cmd_prolog++ = 0; /* DW2 */ + + /* MI_SET_APPID */ + if (session_type == SESSION_TYPE_TYPE1) { + if (session_index >= MAX_TYPE1_SESSIONS) { + drm_err(&i915->drm, "Failed to %s invalid session_index\n", __func__); + goto end; + } + + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP | + MI_SET_APPID_SESSION_ID(session_index)); + } else { + if (session_index >= MAX_TYPE0_SESSIONS) { + drm_err(&i915->drm, "Failed to %s invalid session_index\n", __func__); + goto end; + } + + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index)); + } + + /* MFX_WAIT */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_FLUSH_DW - pxp on */ + *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */ + *cmd_prolog++ = 0; /* DW1 */ + *cmd_prolog++ = 0; /* DW2 */ + + /* MFX_WAIT */ + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + increased_size_in_dw = (cmd_prolog - cmd); +end: + return increased_size_in_dw; +} + +static int add_pxp_epilog(u32 *cmd) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_epilog = cmd; + const int cmd_epilog_size_in_dw = 5; + + if (!cmd) + return cmd_epilog_size_in_dw; + + /* MI_FLUSH_DW - pxp off */ + *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */ + *cmd_epilog++ = 0; /* DW1 */ + *cmd_epilog++ = 0; /* DW2 */ + + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */ + *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG); + + /* MI_BATCH_BUFFER_END */ + *cmd_epilog++ = MI_BATCH_BUFFER_END; + + increased_size_in_dw = (cmd_epilog - cmd); + return increased_size_in_dw; +} + +static int add_pxp_inline_termination(u32 *cmd) +{ + u32 increased_size_in_dw = 0; + u32 *cmd_termin = cmd; + const int cmd_termin_size_in_dw = 2; + + if (!cmd) + return cmd_termin_size_in_dw; + + /* CRYPTO_KEY_EXCHANGE - session inline termination */ + *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */ + *cmd_termin++ = 0; /* DW1 */ + + increased_size_in_dw = (cmd_termin - cmd); + return increased_size_in_dw; +} + +static int terminate_all_hw_sessions_with_global_termination(struct drm_i915_private *i915, + int session_type) +{ + u32 *cmd = NULL; + u32 *cmd_ptr = NULL; + int cmd_size_in_dw = 0; + int ret; + int session_index; + const int session_num_max = pxp_session_max(session_type); + + if (!i915) + return -EINVAL; + + /* Calculate how many bytes need to be alloc */ + for (session_index = 0; session_index < session_num_max; session_index++) { + if (is_hw_session_in_play(i915, session_type, session_index)) { + cmd_size_in_dw += add_pxp_prolog(i915, NULL, session_type, session_index); + cmd_size_in_dw += add_pxp_inline_termination(NULL); + } + } + cmd_size_in_dw += add_pxp_epilog(NULL); + + cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + /* Program the command */ + cmd_ptr = cmd; + for (session_index = 0; session_index < session_num_max; session_index++) { + if (is_hw_session_in_play(i915, session_type, session_index)) { + cmd_ptr += add_pxp_prolog(i915, cmd_ptr, session_type, session_index); + cmd_ptr += add_pxp_inline_termination(cmd_ptr); + } + } + cmd_ptr += add_pxp_epilog(cmd_ptr); + + if (cmd_size_in_dw != (cmd_ptr - cmd)) { + ret = -EINVAL; + drm_err(&i915->drm, "Failed to %s\n", __func__); + goto end; + } + + if (drm_debug_enabled(DRM_UT_DRIVER)) { + print_hex_dump(KERN_DEBUG, "global termination cmd binaries:", + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true); + } + + ret = pxp_submit_cmd(i915, cmd, cmd_size_in_dw); + if (ret) { + drm_err(&i915->drm, "Failed to pxp_submit_cmd()\n"); + goto end; + } + +end: + kfree(cmd); + return ret; +} + +static int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int session_type) +{ + int ret = 0; + struct pxp_protected_session *current_session, *n; + + list_for_each_entry_safe(current_session, n, pxp_session_list(i915, session_type), + session_list) { + ret = pxp_set_pxp_tag(i915, session_type, current_session->session_index, + PROTECTION_MODE_NONE); + if (ret) + drm_err(&i915->drm, "Failed to pxp_set_pxp_tag()\n"); + + list_del(¤t_session->session_list); + kfree(current_session); + } + + return ret; +} + +/** + * intel_pxp_sm_terminate_all_active_sessions - Terminate all active HW sessions and their entries. + * @i915: i915 device handle. + * @session_type: Type of the sessions to be terminated. + * One of enum pxp_session_types. + * + * This function is NOT intended to be called from the ioctl, and need to be protected by + * ctx_mutex to ensure no SIP change during the call. + * + * Return: status. 0 means terminate is successful. + */ +int intel_pxp_sm_terminate_all_active_sessions(struct drm_i915_private *i915, int session_type) +{ + int ret; + + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex); + + /* terminate the hw sessions */ + ret = terminate_all_hw_sessions_with_global_termination(i915, session_type); + if (ret) { + drm_err(&i915->drm, "Failed to terminate_all_hw_sessions_with_global_termination\n"); + return ret; + } + + ret = intel_pxp_sm_destroy_all_sw_sessions(i915, session_type); + if (ret) { + drm_err(&i915->drm, "Failed to intel_pxp_sm_destroy_all_sw_sessions\n"); + return ret; + } + + return ret; +} + int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915) { int ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h index 6eb5efd083a9..fd738f61e10f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h @@ -23,6 +23,22 @@ #define SESSION_TYPE_MASK BIT(7) #define SESSION_ID_MASK (BIT(7) - 1) +/* PXP GPU command definitions */ + +/* MI_SET_APPID */ +#define MI_SET_APPID_TYPE1_APP BIT(7) +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0) + +/* MI_FLUSH_DW */ +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22) + +/* MI_WAIT */ +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9) +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8) + +/* CRYPTO_KEY_EXCHANGE */ +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16)) + /* Arbitrary session */ #define ARB_SESSION_INDEX 0xf #define ARB_SESSION_TYPE SESSION_TYPE_TYPE0 @@ -92,6 +108,7 @@ struct pxp_protected_session { int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag); int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type, u32 session_id); +int intel_pxp_sm_terminate_all_active_sessions(struct drm_i915_private *i915, int session_type); int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915); #endif /* __INTEL_PXP_SM_H__ */ -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx