From: "Huang, Sean Z" <sean.z.huang@intel.com>
To: Intel-gfx@lists.freedesktop.org
Cc: Joonas@freedesktop.org,
Bommu Krishnaiah <krishnaiah.bommu@intel.com>,
Matthew@freedesktop.org
Subject: [Intel-gfx] [RFC-v1 14/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
Date: Sun, 6 Dec 2020 16:21:32 -0800 [thread overview]
Message-ID: <20201207002134.13731-15-sean.z.huang@intel.com> (raw)
In-Reply-To: <20201207002134.13731-1-sean.z.huang@intel.com>
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
Cc: Matthew Auld matthew.auld@intel.com
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++-
include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e0c31c1b0b36..14b0fa04ed14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..2c1ce2761d55 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1698,6 +1720,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull<<32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-12-07 0:22 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-07 10:01 ` Joonas Lahtinen
2020-12-07 18:25 ` Huang, Sean Z
2020-12-07 18:48 ` Huang, Sean Z
2020-12-10 9:02 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
2020-12-07 10:21 ` Joonas Lahtinen
2020-12-08 0:34 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states Huang, Sean Z
2020-12-07 10:50 ` Joonas Lahtinen
2020-12-08 20:11 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
2020-12-07 11:10 ` Joonas Lahtinen
2020-12-09 4:01 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state Huang, Sean Z
2020-12-07 11:44 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
2020-12-07 11:52 ` Joonas Lahtinen
2020-12-09 2:57 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
2020-12-07 11:55 ` Joonas Lahtinen
2020-12-09 5:10 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
2020-12-07 12:00 ` Joonas Lahtinen
2020-12-09 5:11 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
2020-12-07 12:21 ` Joonas Lahtinen
2020-12-09 5:16 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 11/16] drm/i915/pxp: Enable PXP power management Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 12/16] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 13/16] mei: pxp: export pavp client to me client bus Huang, Sean Z
2020-12-07 0:21 ` Huang, Sean Z [this message]
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 15/16] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support Huang, Sean Z
2020-12-07 6:21 ` Anshuman Gupta
2020-12-07 0:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session Patchwork
2020-12-07 1:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-07 4:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201207002134.13731-15-sean.z.huang@intel.com \
--to=sean.z.huang@intel.com \
--cc=Intel-gfx@lists.freedesktop.org \
--cc=Joonas@freedesktop.org \
--cc=Matthew@freedesktop.org \
--cc=krishnaiah.bommu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).