From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49E9DC433E9 for ; Fri, 29 Jan 2021 17:23:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE9C864E00 for ; Fri, 29 Jan 2021 17:23:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE9C864E00 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DB216EB94; Fri, 29 Jan 2021 17:23:27 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E109B6EB94 for ; Fri, 29 Jan 2021 17:23:25 +0000 (UTC) IronPort-SDR: OEg+U5Ttejvo2yOqhOZrJ72ZuX/Dyg6/i2o0vfgCFta8ztItXsds0G5Kf43X5sEvNFqo4ZuZpW vmwbSX+eDEEA== X-IronPort-AV: E=McAfee;i="6000,8403,9879"; a="160227288" X-IronPort-AV: E=Sophos;i="5.79,386,1602572400"; d="scan'208";a="160227288" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 09:23:24 -0800 IronPort-SDR: GO7Y3+5RdBjHWUBqa+nPhN8McZ8cZMRFCD6ebeUO6QrYWHfMQYUY8mG2DAlV32lpp2QyLvZA1j ajuMIvTDGCCw== X-IronPort-AV: E=Sophos;i="5.79,386,1602572400"; d="scan'208";a="389388793" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 09:23:22 -0800 Date: Fri, 29 Jan 2021 19:23:17 +0200 From: Imre Deak To: Ville Syrjala Message-ID: <20210129172317.GE183052@ideak-desk.fi.intel.com> References: <20210128155948.13678-1-ville.syrjala@linux.intel.com> <20210128155948.13678-5-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210128155948.13678-5-ville.syrjala@linux.intel.com> Subject: Re: [Intel-gfx] [PATCH 5/5] drm/i915: Don't check tc_mode unless dealing with a TC PHY X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Jan 28, 2021 at 05:59:48PM +0200, Ville Syrjala wrote: > From: Ville Syrj=E4l=E4 > = > We shouldn't really trust tc_mode on non-TC PHYs since we never > initialize it explicitly. So let's check for the PHY type first. > Fortunately TC_PORT_TBT_ALT happens to be zero so I don't think > there's an actual bug here, just a possibility for a future one > if someone rearranges the enum values. > = > Signed-off-by: Ville Syrj=E4l=E4 Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i= 915/display/intel_ddi.c > index efcdf5499903..5bc5033a2dea 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3463,10 +3463,12 @@ icl_program_mg_dp_mode(struct intel_digital_port = *dig_port, > { > struct drm_i915_private *dev_priv =3D to_i915(dig_port->base.base.dev); > enum tc_port tc_port =3D intel_port_to_tc(dev_priv, dig_port->base.port= ); > + enum phy phy =3D intel_port_to_phy(dev_priv, dig_port->base.port); > u32 ln0, ln1, pin_assignment; > u8 width; > = > - if (dig_port->tc_mode =3D=3D TC_PORT_TBT_ALT) > + if (!intel_phy_is_tc(dev_priv, phy) || > + dig_port->tc_mode =3D=3D TC_PORT_TBT_ALT) > return; > = > if (INTEL_GEN(dev_priv) >=3D 12) { > -- = > 2.26.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx