From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95023C433E0 for ; Thu, 11 Feb 2021 03:52:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4768864DEC for ; Thu, 11 Feb 2021 03:52:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4768864DEC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05D856EDE2; Thu, 11 Feb 2021 03:52:50 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9FAB6EDCC; Thu, 11 Feb 2021 03:52:48 +0000 (UTC) IronPort-SDR: IR+17WoEmKTql7bRyQr9H3fCR/vJwaxLSdaZpPQKnWvVrTQW2IAIcwsqrdHLH5rlcT2lnCEUbG w3dM0Ys7T4Mw== X-IronPort-AV: E=McAfee;i="6000,8403,9891"; a="243678014" X-IronPort-AV: E=Sophos;i="5.81,169,1610438400"; d="scan'208";a="243678014" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2021 19:52:47 -0800 IronPort-SDR: DFhb90rG7d/7EBknx6VJgS97m1G44IqmdjW3jeACpr1mEhvjQnRznkNSCub6FvVvVUf47EHE+L 5W3lvwYYScLQ== X-IronPort-AV: E=Sophos;i="5.81,169,1610438400"; d="scan'208";a="397074805" Received: from rontiver-mobl.amr.corp.intel.com (HELO intel.com) ([10.212.99.95]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2021 19:52:46 -0800 Date: Wed, 10 Feb 2021 22:52:45 -0500 From: Rodrigo Vivi To: Lyude Paul Message-ID: <20210211035245.GG82362@intel.com> References: <20210208233902.1289693-1-lyude@redhat.com> <20210208233902.1289693-9-lyude@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210208233902.1289693-9-lyude@redhat.com> Subject: Re: [Intel-gfx] [RFC v4 08/11] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, open list , dri-devel@lists.freedesktop.org, Sean Paul Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Feb 08, 2021 at 06:38:58PM -0500, Lyude Paul wrote: > If we can't read DP_EDP_PWMGEN_BIT_COUNT in > intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency > defined in the VBT, we'll keep going in the function until we inevitably > fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in > doing this, so just return early. > > Signed-off-by: Lyude Paul Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > index 611eb3a7cc08..a139f0e08839 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c > @@ -449,11 +449,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto > int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1; > u8 pn, pn_min, pn_max; > > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) { > - pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; > - max_backlight = (1 << pn) - 1; > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) { > + drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n"); > + return 0; > } > > + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; > + max_backlight = (1 << pn) - 1; > + > /* Find desired value of (F x P) > * Note that, if F x P is out of supported range, the maximum value or > * minimum value will applied automatically. So no need to check that. > -- > 2.29.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx