[Intel-gfx] [PATCH 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data

José Roberto de Souza
2021-07-22T05:39:35Z

Continuing the conversion from single integrated VBT data to two, now
handling PSR data.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +++++++++++++----------
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++----
drivers/gpu/drm/i915/i915_drv.h | 34 +++++------
4 files changed, 77 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f0d49af8be036..de690e96de723 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -729,15 +729,12 @@ parse_driver_features(struct drm_i915_private *i915,
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
i915->vbt.int_lvds_support = 0;
}
-
- if (bdb->version < 228)
- i915->vbt.psr.enable = driver->psr_enabled;
}

static void
-parse_driver_features_drrs_only(struct drm_i915_private *i915,
- const struct bdb_header *bdb,
- struct ddi_vbt_port_info *info)
+parse_driver_features_drrs_psr_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
{
const struct bdb_driver_features *driver;

@@ -757,6 +754,8 @@ parse_driver_features_drrs_only(struct drm_i915_private *i915,
*/
if (!driver->drrs_enabled)
info->drrs_type = DRRS_NOT_SUPPORTED;
+
+ info->psr.enable = driver->psr_enabled;
}

static void
@@ -774,7 +773,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
if (!power)
return;

- i915->vbt.psr.enable = power->psr & BIT(panel_index);
+ info->psr.enable = power->psr & BIT(panel_index);

/*
* If DRRS is not supported, drrs_type has to be set to 0.
@@ -905,11 +904,11 @@ parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
}

static void
-parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_psr *psr;
const struct psr_table *psr_table;
- int panel_type = i915->vbt.panel_type;

psr = find_section(bdb, BDB_PSR);
if (!psr) {
@@ -917,27 +916,27 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
return;
}

- psr_table = &psr->psr_table[panel_type];
+ psr_table = &psr->psr_table[panel_index];

- i915->vbt.psr.full_link = psr_table->full_link;
- i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+ info->psr.full_link = psr_table->full_link;
+ info->psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;

/* Allowed VBT values goes from 0 to 15 */
- i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+ info->psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;

switch (psr_table->lines_to_wait) {
case 0:
- i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
break;
case 1:
- i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
+ info->psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
break;
case 2:
- i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
break;
case 3:
- i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -954,13 +953,13 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
- i915->vbt.psr.tp1_wakeup_time_us = 500;
+ info->psr.tp1_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp1_wakeup_time_us = 100;
+ info->psr.tp1_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp1_wakeup_time_us = 0;
+ info->psr.tp1_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -968,19 +967,19 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
psr_table->tp1_wakeup_time);
fallthrough;
case 2:
- i915->vbt.psr.tp1_wakeup_time_us = 2500;
+ info->psr.tp1_wakeup_time_us = 2500;
break;
}

switch (psr_table->tp2_tp3_wakeup_time) {
case 0:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+ info->psr.tp2_tp3_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+ info->psr.tp2_tp3_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 0;
+ info->psr.tp2_tp3_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -988,18 +987,18 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
psr_table->tp2_tp3_wakeup_time);
fallthrough;
case 2:
- i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+ info->psr.tp2_tp3_wakeup_time_us = 2500;
break;
}
} else {
- i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
- i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+ info->psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+ info->psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
}

if (bdb->version >= 226) {
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;

- wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+ wakeup_time = (wakeup_time >> (2 * panel_index)) & 0x3;
switch (wakeup_time) {
case 0:
wakeup_time = 500;
@@ -1015,10 +1014,10 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
wakeup_time = 2500;
break;
}
- i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+ info->psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
} else {
/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
- i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us;
+ info->psr.psr2_tp2_tp3_wakeup_time_us = info->psr.tp2_tp3_wakeup_time_us;
}
}

@@ -1986,10 +1985,11 @@ static void parse_integrated_panel(struct drm_i915_private *i915,

parse_panel_options(i915, bdb, info, panel_index);
parse_power_conservation_features(i915, bdb, info, panel_index);
- parse_driver_features_drrs_only(i915, bdb, info);
+ parse_driver_features_drrs_psr_only(i915, bdb, info);
parse_panel_dtd(i915, bdb, info, panel_index);
parse_lfp_backlight(i915, bdb, info, panel_index);
parse_edp(i915, bdb, info, panel_index);
+ parse_psr(i915, bdb, info, panel_index);
}

static void parse_ddi_port(struct drm_i915_private *i915,
@@ -2486,7 +2486,6 @@ void intel_bios_init(struct drm_i915_private *i915)
parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
- parse_psr(i915, bdb);
parse_mipi_config(i915, bdb);
parse_mipi_sequence(i915, bdb);

@@ -3140,3 +3139,13 @@ intel_bios_edp_info(struct intel_encoder *encoder)

return &i915->vbt.ddi_port_info[encoder->port].edp;
}
+
+const struct vbt_psr_info *
+intel_bios_psr_info(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &dig_port->base;
+
+ return &i915->vbt.ddi_port_info[encoder->port].psr;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 8fd9b52f921f7..c701871d9a74d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,7 @@
struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
+struct intel_dp;
struct intel_encoder;
enum port;

@@ -270,5 +271,6 @@ enum drrs_support_type intel_bios_drrs_type(struct intel_encoder *encoder);
const struct drm_display_mode *intel_bios_lfp_lvds_info(struct intel_encoder *encoder);
const struct vbt_backlight_info *intel_bios_backlight_info(struct intel_encoder *encoder);
struct vbt_edp_info *intel_bios_edp_info(struct intel_encoder *encoder);
+const struct vbt_psr_info *intel_bios_psr_info(struct intel_dp *intel_dp);

#endif /* _INTEL_BIOS_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a54e71e4e568c..4be92ccfb0adf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -428,6 +428,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)

static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;

@@ -440,20 +441,20 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
goto check_tp3_sel;
}

- if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+ if (vbt_psr_info->tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
+ else if (vbt_psr_info->tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us;
- else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+ else if (vbt_psr_info->tp1_wakeup_time_us <= 500)
val |= EDP_PSR_TP1_TIME_500us;
else
val |= EDP_PSR_TP1_TIME_2500us;

- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+ if (vbt_psr_info->tp2_tp3_wakeup_time_us == 0)
val |= EDP_PSR_TP2_TP3_TIME_0us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+ else if (vbt_psr_info->tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ else if (vbt_psr_info->tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR_TP2_TP3_TIME_500us;
else
val |= EDP_PSR_TP2_TP3_TIME_2500us;
@@ -470,13 +471,14 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)

static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int idle_frames;

/* Let's use 6 as the minimum to cover all known cases including the
* off-by-one issue that HW has in some cases.
*/
- idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(6, vbt_psr_info->idle_frames);
idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);

if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
@@ -512,18 +514,19 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)

static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;

if (dev_priv->params.psr_safest_params)
return EDP_PSR2_TP2_TIME_2500us;

- if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
- dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
+ if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us >= 0 &&
+ vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
+ else if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us;
- else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
+ else if (vbt_psr_info->psr2_tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us;
else
val |= EDP_PSR2_TP2_TIME_2500us;
@@ -2154,6 +2157,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
*/
void intel_psr_init(struct intel_dp *intel_dp)
{
+ const struct vbt_psr_info *vbt_psr_info = intel_bios_psr_info(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

@@ -2186,7 +2190,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;

if (dev_priv->params.enable_psr == -1)
- if (DISPLAY_VER(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+ if (DISPLAY_VER(dev_priv) < 9 || !vbt_psr_info->enable)
dev_priv->params.enable_psr = 0;

/* Set link_standby x link_off defaults */
@@ -2195,7 +2199,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
intel_dp->psr.link_standby = false;
else if (DISPLAY_VER(dev_priv) < 12)
/* For new platforms up to TGL let's respect VBT back again */
- intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link;
+ intel_dp->psr.link_standby = vbt_psr_info->full_link;

INIT_WORK(&intel_dp->psr.work, intel_psr_work);
INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e957ba8046f2..233dfcf854b52 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -642,6 +642,13 @@ i915_fence_timeout(const struct drm_i915_private *i915)

#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))

+enum psr_lines_to_wait {
+ PSR_0_LINES_TO_WAIT = 0,
+ PSR_1_LINE_TO_WAIT,
+ PSR_4_LINES_TO_WAIT,
+ PSR_8_LINES_TO_WAIT
+};
+
struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata;
@@ -681,13 +688,17 @@ struct ddi_vbt_port_info {
struct edp_power_seq pps;
bool hobl;
} edp;
-};

-enum psr_lines_to_wait {
- PSR_0_LINES_TO_WAIT = 0,
- PSR_1_LINE_TO_WAIT,
- PSR_4_LINES_TO_WAIT,
- PSR_8_LINES_TO_WAIT
+ struct vbt_psr_info {
+ bool enable;
+ bool full_link;
+ bool require_aux_wakeup;
+ int idle_frames;
+ enum psr_lines_to_wait lines_to_wait;
+ int tp1_wakeup_time_us;
+ int tp2_tp3_wakeup_time_us;
+ int psr2_tp2_tp3_wakeup_time_us;
+ } psr;
};

struct intel_vbt_data {
@@ -708,17 +719,6 @@ struct intel_vbt_data {
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;

- struct {
- bool enable;
- bool full_link;
- bool require_aux_wakeup;
- int idle_frames;
- enum psr_lines_to_wait lines_to_wait;
- int tp1_wakeup_time_us;
- int tp2_tp3_wakeup_time_us;
- int psr2_tp2_tp3_wakeup_time_us;
- } psr;
-
/* MIPI DSI */
struct {
u16 panel_id;
--
2.32.0