From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDF90C4338F for ; Tue, 27 Jul 2021 22:50:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88BFE60F90 for ; Tue, 27 Jul 2021 22:50:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 88BFE60F90 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E8C16EB2B; Tue, 27 Jul 2021 22:50:33 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D4226EB2B; Tue, 27 Jul 2021 22:50:32 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10058"; a="209431461" X-IronPort-AV: E=Sophos;i="5.84,275,1620716400"; d="scan'208";a="209431461" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2021 15:50:31 -0700 X-IronPort-AV: E=Sophos;i="5.84,275,1620716400"; d="scan'208";a="517137526" Received: from dut151-iclu.fm.intel.com ([10.105.23.43]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2021 15:50:31 -0700 Date: Tue, 27 Jul 2021 22:50:30 +0000 From: Matthew Brost To: "Belgaumkar, Vinay" Message-ID: <20210727225030.GA49719@DUT151-ICLU.fm.intel.com> References: <20210726190800.26762-1-vinay.belgaumkar@intel.com> <20210726190800.26762-4-vinay.belgaumkar@intel.com> <20210727224402.GA49579@DUT151-ICLU.fm.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Subject: Re: [Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Jul 27, 2021 at 03:48:23PM -0700, Belgaumkar, Vinay wrote: > > > On 7/27/2021 3:44 PM, Matthew Brost wrote: > > On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote: > > > Also ensure uc_init is called before we initialize RPS so that we > > > can check for SLPC support. We do not need to enable up/down > > > interrupts when SLPC is enabled. However, we still need the ARAT > > > interrupt, which will be enabled separately later. > > > > > > > Do we not need a check for rps_uses_slpc in intel_rps_enable? I guessing > > there is a reason why we don't but can't seem to figure that out. > > Yeah, it's due to this check in there - > if (rps->max_freq <= rps->min_freq) > /* leave disabled, no room for dynamic reclocking */; > > With slpc, rps->max_freq and rps->min freq remain uninitialized, so the if > condition just falls through and returns with this- > if (!enabled) I'd add a comment explaining that or add an explict check. With that: Reviewed-by: Matthew Brost > return; > > Thanks, > Vinay. > > > > > Matt > > > > > Signed-off-by: Vinay Belgaumkar > > > Signed-off-by: Sundaresan Sujaritha > > > --- > > > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- > > > drivers/gpu/drm/i915/gt/intel_rps.c | 20 ++++++++++++++++++++ > > > 2 files changed, 21 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > > > index a64aa43f7cd9..04dd69bcf6cb 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > > > @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) > > > intel_gt_init_timelines(gt); > > > intel_gt_pm_init_early(gt); > > > - intel_rps_init_early(>->rps); > > > intel_uc_init_early(>->uc); > > > + intel_rps_init_early(>->rps); > > > } > > > int intel_gt_probe_lmem(struct intel_gt *gt) > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > > index 0c8e7f2b06f0..e858eeb2c59d 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > > @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) > > > return rps_to_gt(rps)->uncore; > > > } > > > +static bool rps_uses_slpc(struct intel_rps *rps) > > > +{ > > > + struct intel_gt *gt = rps_to_gt(rps); > > > + > > > + return intel_uc_uses_guc_slpc(>->uc); > > > +} > > > + > > > static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) > > > { > > > return mask & ~rps->pm_intrmsk_mbz; > > > @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps) > > > { > > > struct intel_gt *gt = rps_to_gt(rps); > > > + GEM_BUG_ON(rps_uses_slpc(rps)); > > > + > > > GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", > > > rps->pm_events, rps_pm_mask(rps, rps->last_freq)); > > > @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val) > > > struct drm_i915_private *i915 = rps_to_i915(rps); > > > u32 swreq; > > > + GEM_BUG_ON(rps_uses_slpc(rps)); > > > + > > > if (GRAPHICS_VER(i915) >= 9) > > > swreq = GEN9_FREQUENCY(val); > > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) > > > @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps) > > > { > > > int adj; > > > + if (!intel_rps_is_enabled(rps)) > > > + return; > > > + > > > GEM_BUG_ON(atomic_read(&rps->num_waiters)); > > > if (!intel_rps_clear_active(rps)) > > > @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps) > > > { > > > struct drm_i915_private *i915 = rps_to_i915(rps); > > > + if (rps_uses_slpc(rps)) > > > + return; > > > + > > > if (IS_CHERRYVIEW(i915)) > > > chv_rps_init(rps); > > > else if (IS_VALLEYVIEW(i915)) > > > @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps) > > > void intel_rps_sanitize(struct intel_rps *rps) > > > { > > > + if (rps_uses_slpc(rps)) > > > + return; > > > + > > > if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) > > > rps_disable_interrupts(rps); > > > } > > > -- > > > 2.25.0 > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx