Re: [Intel-gfx] [PATCH v4 04/18] drm/i915/dg2: Update LNCF steering ranges

Lucas De Marchi
2021-08-04T20:16:36Z

On Thu, Jul 29, 2021 at 09:59:54AM -0700, Matt Roper wrote:
>DG2's replicated register ranges are almost the same at XeHP SDV with
>the exception of one LNCF sub-range that switches to gslice steering.
>We can re-use the XeHP SDV mslice steering table and just provide a
>DG2-specific LNCF steering table.
>
>Bspec: 66534
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>index 8e13bfc81634..1971e34da254 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.c
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>@@ -103,6 +103,12 @@ static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
> {},
> };
>
>+static const struct intel_mmio_range dg2_lncf_steering_table[] = {
>+ { 0x00B000, 0x00B0FF },
>+ { 0x00D880, 0x00D8FF },
>+ {},
>+};
>+
> static u16 slicemask(struct intel_gt *gt, int count)
> {
> u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
>@@ -129,7 +135,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
>
>- if (IS_XEHPSDV(i915)) {
>+ if (IS_DG2(i915)) {
>+ gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;

a title "Update steering tables" would be more appropriate as this is
also setting the mslice table, even if just re-using from xehpsdv.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>+ gt->steering_table[LNCF] = dg2_lncf_steering_table;
>+ } else if (IS_XEHPSDV(i915)) {
> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
> } else if (GRAPHICS_VER(i915) >= 11 &&
>--
>2.25.4
>
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