[Intel-gfx] [PATCH v4 00/18] Begin enabling Xe_HP SDV and DG2 platforms

Matt Roper
2021-07-29T17:00:27Z

This series provides some of the initial enablement patches for two
upcoming discrete GPUs:
* XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP
* DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP

Both platforms will need additional enablement patches beyond what's
present in this series before they're truly usable, including various
LMEM and GuC work that's already happening separately. The new
features/functionality that these platforms bring (such as multi-tile
support, dedicated compute engines, etc.) may be referenced in passing
in some of these patches but will be fully enabled in future series.

v2:
- General rebase and incorporation of r-b's.
- Re-order intel_gt_info and intel_device_info structures to eliminate
some unnecessary padding after the size change of
intel_engine_mask_t. (Tvrtko)
- Use 'intel_step' mechanisms for revid->stepping mapping. (Jani)
- Drop the DSC patches for now; they need some rework. (Jani)

v3:
- About 20 of the patches have landed upstream now. Rebase and resend
the rest. Some of these are already reviewed, but have dependencies
on other unreviewed patches (e.g., the new engine definitions, the
initial SNPS PHY support, etc.).

v4:
- Several more patches have landed upstream; rebase and re-send the
rest. Some of the remaining patches are reviewed but still have
dependencies on non-reviewed patches, so the order is shuffled this
time to group patches by dependency rather than by xehp vs xehpsdv vs
dg2.
- Minor cleanup to "drm/i915/xehp: handle new steering options"
suggested by Caz.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>

Akeem G Abodunrin (1):
drm/i915/dg2: Add new LRI reg offsets

Ankit Nautiyal (1):
drm/i915/dg2: Configure PCON in DP pre-enable path

Daniele Ceraolo Spurio (1):
drm/i915/xehp: handle new steering options

Lucas De Marchi (2):
drm/i915/xehpsdv: Define MOCS table for XeHP SDV
drm/i915/xehpsdv: factor out function to read RP_STATE_CAP

Matt Roper (11):
drm/i915/xehpsdv: Define steering tables
drm/i915/dg2: Add forcewake table
drm/i915/dg2: Update LNCF steering ranges
drm/i915/dg2: Add SQIDI steering
drm/i915/xehp: Loop over all gslices for INSTDONE processing
drm/i915/dg2: Report INSTDONE_GEOM values in error state
drm/i915/xehpsdv: Add maximum sseu limits
drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
drm/i915/dg2: Define MOCS table for DG2
drm/i915/xehpsdv: Read correct RP_STATE_CAP register
drm/i915/dg2: Maintain backward-compatible nested batch behavior

Matthew Auld (1):
drm/i915/xehp: Changes to ss/eu definitions

Stuart Summers (1):
drm/i915/xehpsdv: Add compute DSS type

drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 55 ++--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 15 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 68 ++++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 85 +++++-
drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +++-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 19 +-
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 116 +++++--
drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +-
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 155 +++++++++-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_getparam.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 36 ++-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 15 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 305 ++++++++++---------
include/uapi/drm/i915_drm.h | 3 -
24 files changed, 771 insertions(+), 228 deletions(-)