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Fri, 10 Sep 2021 03:18:08 +0000 (UTC) From: Dave Airlie To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie , Jani Nikula Date: Fri, 10 Sep 2021 13:17:26 +1000 Message-Id: <20210910031741.3292388-11-airlied@gmail.com> In-Reply-To: <20210910031741.3292388-1-airlied@gmail.com> References: <20210910031741.3292388-1-airlied@gmail.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=airlied@gmail.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: gmail.com Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 10/25] drm/i915: split color functions from display vtable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dave Airlie These are only used internally in the color module Reviewed-by: Jani Nikula Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_color.c | 64 +++++++++++----------- drivers/gpu/drm/i915/i915_drv.h | 39 +++++++------ 2 files changed, 54 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i= 915/display/intel_color.c index afcb4bf3826c..ed79075158dd 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_= state *crtc_state) { =09struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->de= v); =20 -=09dev_priv->display.load_luts(crtc_state); +=09dev_priv->color_funcs.load_luts(crtc_state); } =20 void intel_color_commit(const struct intel_crtc_state *crtc_state) { =09struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->de= v); =20 -=09dev_priv->display.color_commit(crtc_state); +=09dev_priv->color_funcs.color_commit(crtc_state); } =20 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc= _state) @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc= _state) { =09struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->de= v); =20 -=09return dev_priv->display.color_check(crtc_state); +=09return dev_priv->color_funcs.color_check(crtc_state); } =20 void intel_color_get_config(struct intel_crtc_state *crtc_state) { =09struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc->de= v); =20 -=09if (dev_priv->display.read_luts) -=09=09dev_priv->display.read_luts(crtc_state); +=09if (dev_priv->color_funcs.read_luts) +=09=09dev_priv->color_funcs.read_luts(crtc_state); } =20 static bool need_plane_update(struct intel_plane *plane, @@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc) =20 =09if (HAS_GMCH(dev_priv)) { =09=09if (IS_CHERRYVIEW(dev_priv)) { -=09=09=09dev_priv->display.color_check =3D chv_color_check; -=09=09=09dev_priv->display.color_commit =3D i9xx_color_commit; -=09=09=09dev_priv->display.load_luts =3D chv_load_luts; -=09=09=09dev_priv->display.read_luts =3D chv_read_luts; +=09=09=09dev_priv->color_funcs.color_check =3D chv_color_check; +=09=09=09dev_priv->color_funcs.color_commit =3D i9xx_color_commit; +=09=09=09dev_priv->color_funcs.load_luts =3D chv_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D chv_read_luts; =09=09} else if (DISPLAY_VER(dev_priv) >=3D 4) { -=09=09=09dev_priv->display.color_check =3D i9xx_color_check; -=09=09=09dev_priv->display.color_commit =3D i9xx_color_commit; -=09=09=09dev_priv->display.load_luts =3D i965_load_luts; -=09=09=09dev_priv->display.read_luts =3D i965_read_luts; +=09=09=09dev_priv->color_funcs.color_check =3D i9xx_color_check; +=09=09=09dev_priv->color_funcs.color_commit =3D i9xx_color_commit; +=09=09=09dev_priv->color_funcs.load_luts =3D i965_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D i965_read_luts; =09=09} else { -=09=09=09dev_priv->display.color_check =3D i9xx_color_check; -=09=09=09dev_priv->display.color_commit =3D i9xx_color_commit; -=09=09=09dev_priv->display.load_luts =3D i9xx_load_luts; -=09=09=09dev_priv->display.read_luts =3D i9xx_read_luts; +=09=09=09dev_priv->color_funcs.color_check =3D i9xx_color_check; +=09=09=09dev_priv->color_funcs.color_commit =3D i9xx_color_commit; +=09=09=09dev_priv->color_funcs.load_luts =3D i9xx_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D i9xx_read_luts; =09=09} =09} else { =09=09if (DISPLAY_VER(dev_priv) >=3D 11) -=09=09=09dev_priv->display.color_check =3D icl_color_check; +=09=09=09dev_priv->color_funcs.color_check =3D icl_color_check; =09=09else if (DISPLAY_VER(dev_priv) >=3D 10) -=09=09=09dev_priv->display.color_check =3D glk_color_check; +=09=09=09dev_priv->color_funcs.color_check =3D glk_color_check; =09=09else if (DISPLAY_VER(dev_priv) >=3D 7) -=09=09=09dev_priv->display.color_check =3D ivb_color_check; +=09=09=09dev_priv->color_funcs.color_check =3D ivb_color_check; =09=09else -=09=09=09dev_priv->display.color_check =3D ilk_color_check; +=09=09=09dev_priv->color_funcs.color_check =3D ilk_color_check; =20 =09=09if (DISPLAY_VER(dev_priv) >=3D 9) -=09=09=09dev_priv->display.color_commit =3D skl_color_commit; +=09=09=09dev_priv->color_funcs.color_commit =3D skl_color_commit; =09=09else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) -=09=09=09dev_priv->display.color_commit =3D hsw_color_commit; +=09=09=09dev_priv->color_funcs.color_commit =3D hsw_color_commit; =09=09else -=09=09=09dev_priv->display.color_commit =3D ilk_color_commit; +=09=09=09dev_priv->color_funcs.color_commit =3D ilk_color_commit; =20 =09=09if (DISPLAY_VER(dev_priv) >=3D 11) { -=09=09=09dev_priv->display.load_luts =3D icl_load_luts; -=09=09=09dev_priv->display.read_luts =3D icl_read_luts; +=09=09=09dev_priv->color_funcs.load_luts =3D icl_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D icl_read_luts; =09=09} else if (DISPLAY_VER(dev_priv) =3D=3D 10) { -=09=09=09dev_priv->display.load_luts =3D glk_load_luts; -=09=09=09dev_priv->display.read_luts =3D glk_read_luts; +=09=09=09dev_priv->color_funcs.load_luts =3D glk_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D glk_read_luts; =09=09} else if (DISPLAY_VER(dev_priv) >=3D 8) { -=09=09=09dev_priv->display.load_luts =3D bdw_load_luts; +=09=09=09dev_priv->color_funcs.load_luts =3D bdw_load_luts; =09=09} else if (DISPLAY_VER(dev_priv) >=3D 7) { -=09=09=09dev_priv->display.load_luts =3D ivb_load_luts; +=09=09=09dev_priv->color_funcs.load_luts =3D ivb_load_luts; =09=09} else { -=09=09=09dev_priv->display.load_luts =3D ilk_load_luts; -=09=09=09dev_priv->display.read_luts =3D ilk_read_luts; +=09=09=09dev_priv->color_funcs.load_luts =3D ilk_load_luts; +=09=09=09dev_priv->color_funcs.read_luts =3D ilk_read_luts; =09=09} =09} =20 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index e70587cf8679..8930bf2db226 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -345,6 +345,25 @@ struct drm_i915_wm_disp_funcs { =09int (*compute_global_watermarks)(struct intel_atomic_state *state); }; =20 +struct intel_color_funcs { +=09int (*color_check)(struct intel_crtc_state *crtc_state); +=09/* +=09 * Program double buffered color management registers during +=09 * vblank evasion. The registers should then latch during the +=09 * next vblank start, alongside any other double buffered registers +=09 * involved with the same commit. +=09 */ +=09void (*color_commit)(const struct intel_crtc_state *crtc_state); +=09/* +=09 * Load LUTs (and other single buffered color management +=09 * registers). Will (hopefully) be called during the vblank +=09 * following the latching of any double buffered registers +=09 * involved with the same commit. +=09 */ +=09void (*load_luts)(const struct intel_crtc_state *crtc_state); +=09void (*read_luts)(struct intel_crtc_state *crtc_state); +}; + struct drm_i915_display_funcs { =09void (*get_cdclk)(struct drm_i915_private *dev_priv, =09=09=09 struct intel_cdclk_config *cdclk_config); @@ -381,23 +400,6 @@ struct drm_i915_display_funcs { =09/* render clock increase/decrease */ =09/* display clock increase/decrease */ =09/* pll clock increase/decrease */ - -=09int (*color_check)(struct intel_crtc_state *crtc_state); -=09/* -=09 * Program double buffered color management registers during -=09 * vblank evasion. The registers should then latch during the -=09 * next vblank start, alongside any other double buffered registers -=09 * involved with the same commit. -=09 */ -=09void (*color_commit)(const struct intel_crtc_state *crtc_state); -=09/* -=09 * Load LUTs (and other single buffered color management -=09 * registers). Will (hopefully) be called during the vblank -=09 * following the latching of any double buffered registers -=09 * involved with the same commit. -=09 */ -=09void (*load_luts)(const struct intel_crtc_state *crtc_state); -=09void (*read_luts)(struct intel_crtc_state *crtc_state); }; =20 =20 @@ -972,6 +974,9 @@ struct drm_i915_private { =09/* Display functions */ =09struct drm_i915_display_funcs display; =20 +=09/* Display internal color functions */ +=09struct intel_color_funcs color_funcs; + =09/* PCH chipset type */ =09enum intel_pch pch_type; =09unsigned short pch_id; --=20 2.31.1