From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A479C433FE for ; Tue, 28 Sep 2021 12:48:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1287E610CC for ; Tue, 28 Sep 2021 12:48:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1287E610CC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90A466E898; Tue, 28 Sep 2021 12:48:23 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74FB66E898 for ; Tue, 28 Sep 2021 12:48:22 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10120"; a="211771969" X-IronPort-AV: E=Sophos;i="5.85,329,1624345200"; d="scan'208";a="211771969" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 05:48:18 -0700 X-IronPort-AV: E=Sophos;i="5.85,329,1624345200"; d="scan'208";a="553980851" Received: from unknown (HELO intel.com) ([10.237.72.91]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 05:48:16 -0700 Date: Tue, 28 Sep 2021 15:49:11 +0300 From: "Lisovskiy, Stanislav" To: Matt Roper Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , intel-gfx@lists.freedesktop.org, jani.saarinen@intel.com, maarten.lankhorst@linux.intel.com Message-ID: <20210928124911.GA10399@intel.com> References: <20210923084858.5480-1-stanislav.lisovskiy@intel.com> <20210927182335.GY3389343@mdroper-desk1.amr.corp.intel.com> <20210928052411.GD3389343@mdroper-desk1.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210928052411.GD3389343@mdroper-desk1.amr.corp.intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote: > On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote: > > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote: > > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote: > > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote: > > > > > TileF(Tile4 in bspec) format is 4K tile organized into > > > > > 64B subtiles with same basic shape as for legacy TileY > > > > > which will be supported by Display13. > > > > > > > > Why we still haven't done the F->tile64 rename? > > > > > > > > This is the last chance to fix this before we bake > > > > this into the uapi and are stuck with a name that doesn't > > > > match the spec and will just confuse everyone. > > > > > > I think you're confusing the formats here. The bspec uses both terms > > > "TileF" and "Tile4" for the same format in different places. There's a > > > completely different format that's referred to as both "TileS" and > > > "Tile64" in the bspec that we don't use at the moment. So tile64 > > > wouldn't be a correct rename, but tile4 could be. > > > > Right, tile64 is the macro tile variant I think. So like Ys > > which we never bothered implementing, so I guess we''l not bother > > with tile64 either. > > > > > > > > In general Tile4 is much more common in the bspec than TileF is (TileF > > > terminology is mostly found in the media sections). And bspec 44917 is > > > the most authoritative bspec page on the subject, and it refers to it as > > > Tile4, so I agree that switching over "Tile4" would probably be a good > > > move. > > > > > > > > > > > > > > > ... > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > > index bde5860b3686..d7dc421c6134 100644 > > > > > --- a/include/uapi/drm/i915_drm.h > > > > > +++ b/include/uapi/drm/i915_drm.h > > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching { > > > > > #define I915_TILING_NONE 0 > > > > > #define I915_TILING_X 1 > > > > > #define I915_TILING_Y 2 > > > > > -#define I915_TILING_LAST I915_TILING_Y > > > > > +#define I915_TILING_F 3 > > > > > +#define I915_TILING_LAST I915_TILING_F > > > > > > > > fences... > > > > > > Recognizing TileF/Tile4 separately from TileY is important to code > > > outside of display as well. There are blitter instructions that require > > > different settings for TileY vs Tile4/F so if we drop the tracking of > > > this as a unique tiling type, it will break the blitting/copying and > > > some of the upcoming local memory support for Xe_HP-based platforms. > > > > These are uapi definitions for set_tiling(). You are not meant to add > > anything there. Just like we didn't add anything for Yf. > > Yeah, I think that's the real problem --- we define some values here in > the uapi header, but we also wind up using the same set of values for > driver-internal non-uapi purposes too rather than having a separate enum > (containing a superset of the uapi values) that can be used for those > other things. Display code can use FB modifiers for some things, but > core/lmem code needs a way to refer to Tile4 and such and doesn't have a > good way to do that today. > > I think most (all?) of the non-display code that's relying on a > definition of I915_TILING_F is in various selftests that are still being > prepared for upstreaming, so maybe there's a better way to handle the > selection of possible formats specifically in the selftest code itself. > That's really the only area of the kernel code that should need to be > aware of the specific internal layout of various buffers. So I will proceed with the renaming at least. Ville, suppose, I still need part of fencing related code? Stan > > > Matt > > > > > -- > > Ville Syrjälä > > Intel > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795