[Intel-gfx] [PATCH 0/6] drm/i915/dp: Fix link parameter use in lack of a valid DPCD

Imre Deak
2021-10-18T09:42:02Z

This patchset fixes a few issues, related to invalid accesses from the
intel_dp->common_rates[] array and in general the link rate, lane count
parameters being invalid until a valid DPCD is read from the sink.

One issue in intel_dp_sync_state() was caught by the CONFIG_UBSAN
feature. The first 3 patches are also needed for stable kernels.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Imre Deak (6):
drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
drm/i915/dp: Ensure sink rate values are always valid
drm/i915/dp: Ensure max link params are always valid
drm/i915/dp: Ensure sink/link max lane count values are always valid
drm/i915/dp: Sanitize sink rate DPCD register values
drm/i915/dp: Sanitize link common rate array lookups

.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 127 ++++++++++++++----
2 files changed, 101 insertions(+), 28 deletions(-)

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2.27.0